1 files changed, 0 insertions, 28 deletions
diff --git a/components.scala b/components.scala
index 9942e3a..d92f4ec 100644
--- a/components.scala
+++ b/components.scala
@@ -71,34 +71,6 @@ class RegisterFile() extends Module {
 
 }
 
-class ALU() extends Module {
-  val io = IO(new Bundle {
-    val op = Input(UInt(4.W))
-    val in1 = Input(UInt(32.W))
-    val in2 = Input(UInt(32.W))
-    val out = Output(UInt(32.W))
-    val output_valid = Output(Bool())
-  })
-
-  io.out := 0.U
-  io.output_valid := false.B
-  when(io.op === 0.U) {
-    io.out := io.in1 & io.in2;
-    io.output_valid := true.B
-  }.elsewhen(io.op === 1.U) {
-    io.out := io.in1 | io.in2;
-    io.output_valid := true.B
-  }.elsewhen(io.op === 2.U) {
-    io.out := io.in1 + io.in2;
-    io.output_valid := true.B
-  }.elsewhen(io.op === 6.U) {
-    io.out := io.in1 - io.in2
-    io.output_valid := true.B
-  }.otherwise {
-    io.output_valid := false.B
-  }
-}
-
 println(getVerilog(new ALU))
 
 // ChiselStage.emitChirrtl(new RegisterFile())