AbstractModule.scala


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package chiselTests

import chisel3._
import chisel3.stage.ChiselStage
import chisel3.MetaConnect._


object TypeArithmetic {
  implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b)
  implicit val f2: SomeTypeContainer => Unit => SomeTypeContainer = (a: SomeTypeContainer) => (b: Unit) => a
}

case class SomeTypeContainer(w: Int) extends UInt(w.W)

class AbstractModule[T <: Data](params: T) extends Module[T] {
  val node = IO(params)
}

class AbstractModuleContainer extends Module {
  val mod1 = Module(new AbstractModule[UInt](Input(UInt(4.W))))
  val mod2 = Module(new AbstractModule[UInt](Output(UInt(8.W))))

  val tc = SomeTypeContainer(16)
  val mod3 = Module(new AbstractModule[tc.type](Output(tc)))

  import TypeArithmetic._
  mod3.node.makeConnection(mod1.node.makeConnection(mod2.node))

  // goal is to get this to work:
  // mod1.node := mod2.node := mod3.node
}

object main {
  def main(args: Array[String]): Unit = {
    // println(getVerilogString(new Example))
    println(chisel3.stage.ChiselStage.emitVerilog(new AbstractModuleContainer))
  }
}