package chiselTests

import chisel3._
import chisel3.stage.ChiselStage

class AbstractModule[T <: Data](params: T) extends Module[T] {
  val node = IO(params)
}

class AbstractModuleContainer extends Module {
  val mod1 = Module(new AbstractModule[UInt](Input(UInt(0.W))))
  val mod2 = Module(new AbstractModule[UInt](Output(UInt(0.W))))
  mod2.node := mod1.node
}

object AbstractModuleSpec {
  def main(args: Array[String]): Unit = {
    // println(getVerilogString(new Example))
    println(chisel3.stage.ChiselStage.emitVerilog(new AbstractModuleContainer))
  }
}