// package chiselTests

// import chisel3._
// import chisel3.stage.ChiselStage
// import chisel3.MetaConnect._

// object TypeArithmetic {
//   // implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b)
//   implicit val f2: SomeTypeContainer => UInt => SomeTypeContainer = (a: SomeTypeContainer) => (b: UInt) => new SomeTypeContainer(b.litValue.toInt+a.w)
// }

// case class SomeTypeContainer(w: Int) extends UInt(w.W)

// class AbstractModuleContainer extends AbstractModule({
//   val mod1 = new AbstractInterface[UInt](Input(UInt(4.W)))
//   val mod2 = new AbstractInterface[UInt](Output(UInt(8.W)))
//   val mod3 = new AbstractInterface[SomeTypeContainer](Output(SomeTypeContainer(16)))

//   // import TypeArithmetic._
//   // val typeA = mod3.ioNode.makeConnection(mod2.ioNode)
//   // // val typeB = mod2.ioNode.makeConnection(mod3.ioNode)
//   // // println(s"\ttypeA: ${typeA}\n\ttypeB: ${typeB}")
//   // // need to create versions of mods1-3 with these new type params
//   // // similar to log aggregation writer monad? but more like type aggregation
//   // Seq(mod1, mod2, mod3)
// })

// class LowerableModule extends Module {
//   val innerModule = Module(new AbstractModuleContainer)
// }

// object main {
//   def main(args: Array[String]): Unit = {
//     println(chisel3.stage.ChiselStage.emitChirrtl(new LowerableModule))
//   }
// }