From f71b738e657ad783fa776a27b864eb93d55faa53 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Fri, 18 Sep 2015 13:29:16 -0700
Subject: Use FIRRTL idiom for SeqMem read-enables

Emit read-enables as mux(ren, addr, poison).
---
 src/main/scala/Chisel/Core.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 5565e87e..74f07756 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -168,7 +168,8 @@ object SeqMem {
 }
 
 sealed class SeqMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
-  def read(addr: UInt, enable: Bool): T = read(addr) // TODO read enable
+  def read(addr: UInt, enable: Bool): T =
+    read(Mux(enable, addr, Poison(addr)))
 }
 
 object Vec {
-- 
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