From f3ea8f1f7539d4afb50555df28dd16562c0ee256 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Wed, 27 Apr 2016 17:19:44 -0700 Subject: clock|reset to _clock|_reset, added explanatory comment @aswaterman closes #156 --- src/main/scala/Chisel/Module.scala | 8 +++++--- src/main/scala/Chisel/util/Decoupled.scala | 4 ++-- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala index 738863e3..3e839cac 100644 --- a/src/main/scala/Chisel/Module.scala +++ b/src/main/scala/Chisel/Module.scala @@ -38,9 +38,11 @@ object Module { abstract class Module( override_clock: Option[Clock]=None, override_reset: Option[Bool]=None) extends HasId { - def this(clock: Clock) = this(Some(clock), None) - def this(reset: Bool) = this(None, Some(reset)) - def this(clock: Clock, reset: Bool) = this(Some(clock), Some(reset)) + // _clock and _reset can be clock and reset in these 2ary constructors + // once chisel2 compatibility issues are resolved + def this(_clock: Clock) = this(Some(_clock), None) + def this(_reset: Bool) = this(None, Some(_reset)) + def this(_clock: Clock, _reset: Bool) = this(Some(_clock), Some(_reset)) private[Chisel] val _namespace = Builder.globalNamespace.child private[Chisel] val _commands = ArrayBuffer[Command]() diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala index 6c7787f8..8e045855 100644 --- a/src/main/scala/Chisel/util/Decoupled.scala +++ b/src/main/scala/Chisel/util/Decoupled.scala @@ -106,8 +106,8 @@ class Queue[T <: Data](gen: T, val entries: Int, flow: Boolean = false, override_reset: Option[Bool] = None) extends Module(override_reset=override_reset) { - def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, reset: Bool) = - this(gen, entries, pipe, flow, Some(reset)) + def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) = + this(gen, entries, pipe, flow, Some(_reset)) val io = new QueueIO(gen, entries) -- cgit v1.2.3