From d675043717593fb7e96fb0f1952debbeb7f20a57 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 21 Jun 2016 09:17:30 -0700
Subject: New Module, IO, Input/Output wrapping.

---
 src/main/scala/Chisel/testers/BasicTester.scala    |   2 +-
 src/main/scala/Chisel/util/Decoupled.scala         | 113 ++++++++++-----------
 src/main/scala/Chisel/util/Valid.scala             |  30 +++---
 src/test/scala/chiselTests/Assert.scala            |   2 +-
 src/test/scala/chiselTests/BundleWire.scala        |   8 +-
 src/test/scala/chiselTests/Decoder.scala           |   8 +-
 src/test/scala/chiselTests/DeqIOSpec.scala         |  11 +-
 .../scala/chiselTests/EnableShiftRegister.scala    |  10 +-
 src/test/scala/chiselTests/LFSR16.scala            |   8 +-
 src/test/scala/chiselTests/Module.scala            |  22 ++--
 src/test/scala/chiselTests/OptionBundle.scala      |   6 +-
 .../scala/chiselTests/ParameterizedModule.scala    |   8 +-
 src/test/scala/chiselTests/Risc.scala              |  16 +--
 src/test/scala/chiselTests/SIntOps.scala           |  36 +++----
 src/test/scala/chiselTests/Tbl.scala               |  14 +--
 src/test/scala/chiselTests/Vec.scala               |  30 ------
 src/test/scala/chiselTests/VendingMachine.scala    |   9 +-
 17 files changed, 147 insertions(+), 186 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/Chisel/testers/BasicTester.scala
index b8c1494a..94113836 100644
--- a/src/main/scala/Chisel/testers/BasicTester.scala
+++ b/src/main/scala/Chisel/testers/BasicTester.scala
@@ -12,7 +12,7 @@ import internal.sourceinfo.SourceInfo
 
 class BasicTester extends Module {
   // The testbench has no IOs, rather it should communicate using printf, assert, and stop.
-  val io = new Bundle()
+  val io = IO(new Bundle())
 
   def popCount(n: Long): Int = n.toBinaryString.count(_=='1')
 
diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala
index 8e045855..66b348e0 100644
--- a/src/main/scala/Chisel/util/Decoupled.scala
+++ b/src/main/scala/Chisel/util/Decoupled.scala
@@ -8,71 +8,62 @@ package Chisel
 /** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
 class DecoupledIO[+T <: Data](gen: T) extends Bundle
 {
-  val ready = Bool(INPUT)
-  val valid = Bool(OUTPUT)
-  val bits  = gen.cloneType.asOutput
-  def fire(dummy: Int = 0): Bool = ready && valid
-  override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type]
+  val ready = Input(Bool())
+  val valid = Output(Bool())
+  val bits  = Output(gen.newType)
+  override protected def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
 }
 
-/** Adds a ready-valid handshaking protocol to any interface.
-  * The standard used is that the consumer uses the flipped interface.
-  */
-object Decoupled {
+object DecoupledIO {
+  /** Adds a ready-valid handshaking protocol to any interface.
+    * The standard used is that the consumer uses the flipped interface.
+    */
   def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
-}
 
-/** An I/O bundle for enqueuing data with valid/ready handshaking
-  * Initialization must be handled, if necessary, by the parent circuit
-  */
-class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen)
-{
-  /** push dat onto the output bits of this interface to let the consumer know it has happened.
-    * @param dat the values to assign to bits.
-    * @return    dat.
-    */
-  def enq(dat: T): T = { valid := Bool(true); bits := dat; dat }
+  implicit class AddMethodsToDecoupled[T<:Data](val target: DecoupledIO[T]) extends AnyVal {
+    def firing: Bool = target.ready && target.valid
+
+    /** push dat onto the output bits of this interface to let the consumer know it has happened.
+      * @param dat the values to assign to bits.
+      * @return    dat.
+      */
+    def enq(dat: T): T = {
+      target.valid := true.asBool
+      target.bits := dat
+      dat
+    }
 
-  /** Initialize this Bundle.  Valid is set to false, and all bits are set to zero.
-    * NOTE: This method of initialization is still being discussed and could change in the
-    * future.
-    */
-  def init(): Unit = {
-    valid := Bool(false)
-    for (io <- bits.flatten)
-      io := UInt(0)
-  }
-  override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; }
-}
+    /** Indicate no enqueue occurs.  Valid is set to false, and all bits are set to zero.
+      */
+    def noenq(): Unit = {
+      target.valid := false.asBool
+      target.bits := target.bits.fromBits(0.asUInt)
+    }
 
-/** An I/O bundle for dequeuing data with valid/ready handshaking.
-  * Initialization must be handled, if necessary, by the parent circuit
-  */
-class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped
-{
-  /** Assert ready on this port and return the associated data bits.
-    * This is typically used when valid has been asserted by the producer side.
-    * @param b ignored
-    * @return the data for this device,
-    */
-  def deq(b: Boolean = false): T = { ready := Bool(true); bits }
+    /** Assert ready on this port and return the associated data bits.
+      * This is typically used when valid has been asserted by the producer side.
+      * @param b ignored
+      * @return the data for this device,
+      */
+    def deq(): T = {
+      target.ready := true.asBool
+      target.bits
+    }
 
-  /** Initialize this Bundle.
-    * NOTE: This method of initialization is still being discussed and could change in the
-    * future.
-    */
-  def init(): Unit = {
-    ready := Bool(false)
+    /** Indicate no dequeue occurs. Ready is set to false
+      */
+    def nodeq(): Unit = {
+      target.ready := false.asBool
+    }
   }
   override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
 }
 
-/** An I/O bundle for dequeuing data with valid/ready handshaking */
-class DecoupledIOC[+T <: Data](gen: T) extends Bundle
-{
-  val ready = Bool(INPUT)
-  val valid = Bool(OUTPUT)
-  val bits  = gen.cloneType.asOutput
+object EnqIO {
+  def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
+}
+object DeqIO {
+  def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
 }
 
 /** An I/O Bundle for Queues
@@ -81,11 +72,11 @@ class DecoupledIOC[+T <: Data](gen: T) extends Bundle
 class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
 {
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */
-  val enq   = Decoupled(gen.cloneType).flip()
+  val enq = EnqIO(gen)
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
-  val deq   = Decoupled(gen.cloneType)
+  val deq = DeqIO(gen)
   /** The current amount of data in the queue */
-  val count = UInt(OUTPUT, log2Up(entries + 1))
+  val count = Output(UInt(log2Up(entries + 1)))
 }
 
 /** A hardware module implementing a Queue
@@ -109,7 +100,7 @@ extends Module(override_reset=override_reset) {
   def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) =
     this(gen, entries, pipe, flow, Some(_reset))
   
-  val io = new QueueIO(gen, entries)
+  val io = IO(new QueueIO(gen, entries))
 
   val ram = Mem(entries, gen)
   val enq_ptr = Counter(entries)
@@ -119,8 +110,8 @@ extends Module(override_reset=override_reset) {
   val ptr_match = enq_ptr.value === deq_ptr.value
   val empty = ptr_match && !maybe_full
   val full = ptr_match && maybe_full
-  val do_enq = Wire(init=io.enq.fire())
-  val do_deq = Wire(init=io.deq.fire())
+  val do_enq = Wire(init=io.enq.firing)
+  val do_deq = Wire(init=io.deq.firing)
 
   when (do_enq) {
     ram(enq_ptr.value) := io.enq.bits
@@ -167,7 +158,7 @@ extends Module(override_reset=override_reset) {
   from the inputs.
 
   Example usage:
-     {{{ val q = Queue(Decoupled(UInt()), 16)
+     {{{ val q = Queue(DecoupledIO(UInt()), 16)
      q.io.enq <> producer.io.out
      consumer.io.in <> q.io.deq }}}
   */
diff --git a/src/main/scala/Chisel/util/Valid.scala b/src/main/scala/Chisel/util/Valid.scala
index 9e2202bb..38997cab 100644
--- a/src/main/scala/Chisel/util/Valid.scala
+++ b/src/main/scala/Chisel/util/Valid.scala
@@ -5,20 +5,18 @@
 
 package Chisel
 
-/** An I/O Bundle containing data and a signal determining if it is valid */
-class ValidIO[+T <: Data](gen2: T) extends Bundle
+/** An Bundle containing data and a signal determining if it is valid */
+class Valid[+T <: Data](gen: T) extends Bundle
 {
-  val valid = Bool(OUTPUT)
-  val bits = gen2.cloneType.asOutput
+  val valid = Output(Bool())
+  val bits  = Output(gen.cloneType)
   def fire(dummy: Int = 0): Bool = valid
-  override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type]
+  override def cloneType: this.type = Valid(gen).asInstanceOf[this.type]
 }
 
-/** Adds a valid protocol to any interface. The standard used is
-  that the consumer uses the flipped interface.
-*/
+/** Adds a valid protocol to any interface */
 object Valid {
-  def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen)
+  def apply[T <: Data](gen: T): Valid[T] = new Valid(gen)
 }
 
 /** A hardware module that delays data coming down the pipeline
@@ -32,7 +30,7 @@ object Valid {
   */
 object Pipe
 {
-  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = {
+  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): Valid[T] = {
     if (latency == 0) {
       val out = Wire(Valid(enqBits))
       out.valid <> enqValid
@@ -44,16 +42,16 @@ object Pipe
       apply(v, b, latency-1)
     }
   }
-  def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1)
-  def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency)
+  def apply[T <: Data](enqValid: Bool, enqBits: T): Valid[T] = apply(enqValid, enqBits, 1)
+  def apply[T <: Data](enq: Valid[T], latency: Int = 1): Valid[T] = apply(enq.valid, enq.bits, latency)
 }
 
 class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module
 {
-  val io = new Bundle {
-    val enq = Valid(gen).flip
-    val deq = Valid(gen)
-  }
+  val io = IO(new Bundle {
+    val enq = Input(Valid(gen))
+    val deq = Output(Valid(gen))
+  })
 
   io.deq <> Pipe(io.enq, latency)
 }
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 24eb8b55..750ed6e4 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -25,7 +25,7 @@ class SucceedingAssertTester() extends BasicTester {
 }
 
 class PipelinedResetModule extends Module {
-  val io = new Bundle { }
+  val io = IO(new Bundle { })
   val a = Reg(init = UInt(0xbeef))
   val b = Reg(init = UInt(0xbeef))
   assert(a === b)
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index d2e42fa9..147575e1 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -12,10 +12,10 @@ class Coord extends Bundle {
 }
 
 class BundleWire(n: Int) extends Module {
-  val io = new Bundle {
-    val in   = (new Coord).asInput
-    val outs = Vec(n, new Coord).asOutput
-  }
+  val io = IO(new Bundle {
+    val in   = Input(new Coord)
+    val outs = Output(Vec(n, new Coord))
+  })
   val coords = Wire(Vec(n, new Coord))
   for (i <- 0 until n) {
     coords(i)  := io.in
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index e5cdfd07..07622667 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -8,10 +8,10 @@ import org.scalacheck._
 import Chisel.testers.BasicTester
 
 class Decoder(bitpats: List[String]) extends Module {
-  val io = new Bundle {
-    val inst  = UInt(INPUT, 32)
-    val matched = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val inst  = Input(UInt(32))
+    val matched = Output(Bool())
+  })
   io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
 }
 
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 8f7937ab..38e00690 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -15,17 +15,17 @@ class UsesDeqIOInfo extends Bundle {
 }
 
 class UsesDeqIO extends Module {
-  val io = new Bundle {
-    val in = new DeqIO(new UsesDeqIOInfo)
-    val out = new EnqIO(new UsesDeqIOInfo)
-  }
+  val io = IO(new Bundle {
+    val in = DeqIO(new UsesDeqIOInfo)
+    val out = EnqIO(new UsesDeqIOInfo)
+  })
 }
 
 class DeqIOSpec extends ChiselFlatSpec {
   runTester {
     new BasicTester {
       val dut = new UsesDeqIO
-
+/*
       "DeqIO" should "set the direction of it's parameter to INPUT" in {
         assert(dut.io.in.bits.info_data.dir === INPUT)
       }
@@ -55,6 +55,7 @@ class DeqIOSpec extends ChiselFlatSpec {
         assert(dut.io.out.ready.dir == out_clone.ready.dir)
         assert(dut.io.out.valid.dir == out_clone.valid.dir)
       }
+      */
     }
   }
 }
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 6600df2a..11e8b70b 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -5,11 +5,11 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class EnableShiftRegister extends Module {
-  val io = new Bundle {
-    val in    = UInt(INPUT, 4)
-    val shift = Bool(INPUT)
-    val out   = UInt(OUTPUT, 4)
-  }
+  val io = IO(new Bundle {
+    val in    = Input(UInt(4))
+    val shift = Input(Bool())
+    val out   = Output(UInt(4))
+  })
   val r0 = Reg(init = UInt(0, 4))
   val r1 = Reg(init = UInt(0, 4))
   val r2 = Reg(init = UInt(0, 4))
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index ed76a296..54144bea 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -5,10 +5,10 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class LFSR16 extends Module {
-  val io = new Bundle {
-    val inc = Bool(INPUT)
-    val out = UInt(OUTPUT, 16)
-  }
+  val io = IO(new Bundle {
+    val inc = Input(Bool())
+    val out = Output(UInt(16))
+  })
   val res = Reg(init = UInt(1, 16))
   when (io.inc) {
     val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 88ba795b..ba251916 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -4,20 +4,20 @@ package chiselTests
 import Chisel._
 
 class SimpleIO extends Bundle {
-  val in  = UInt(INPUT,  32)
-  val out = UInt(OUTPUT, 32)
+  val in  = Input(UInt(32))
+  val out = Output(UInt(32))
 }
 
 class PlusOne extends Module {
-  val io = new SimpleIO
+  val io = IO(new SimpleIO)
   io.out := io.in + UInt(1)
 }
 
 class ModuleVec(val n: Int) extends Module {
-  val io = new Bundle {
-    val ins  = Vec(n, UInt(INPUT,  32))
-    val outs = Vec(n, UInt(OUTPUT, 32))
-  }
+  val io = IO(new Bundle {
+    val ins  = Input(Vec(n, UInt(32)))
+    val outs = Output(Vec(n, UInt(32)))
+  })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
     pluses(i).in := io.ins(i)
@@ -39,8 +39,8 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
 */
 
 class ModuleWire extends Module {
-  val io = new SimpleIO
-  val inc = Wire(Module(new PlusOne).io)
+  val io = IO(new SimpleIO)
+  val inc = Wire(Module(new PlusOne).io.newType)
   inc.in := io.in
   io.out := inc.out
 }
@@ -57,10 +57,10 @@ class ModuleWireTester(c: ModuleWire) extends Tester(c) {
 */
 
 class ModuleWhen extends Module {
-  val io = new Bundle {
+  val io = IO(new Bundle {
     val s = new SimpleIO
     val en = Bool()
-  }
+  })
   when(io.en) {
     val inc = Module(new PlusOne).io
     inc.in := io.s.in
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index c5a347e6..ad694925 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -8,15 +8,15 @@ import Chisel.testers.BasicTester
 
 class OptionBundle(hasIn: Boolean) extends Bundle {
   val in = if (hasIn) {
-    Some(Bool(INPUT))
+    Some(Input(Bool()))
   } else {
     None
   }
-  val out = Bool(OUTPUT)
+  val out = Output(Bool())
 }
 
 class OptionBundleModule(hasIn: Boolean) extends Module {
-  val io = new OptionBundle(hasIn)
+  val io = IO(new OptionBundle(hasIn))
   if (hasIn) {
     io.out := io.in.get
   } else {
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index 35e3ba78..f682f310 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -7,10 +7,10 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class ParameterizedModule(invert: Boolean) extends Module {
-  val io = new Bundle {
-    val in = new Bool(INPUT)
-    val out = new Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val in  = Input(Bool())
+    val out = Output(Bool())
+  })
   if (invert) {
     io.out := !io.in
   } else {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 3daa5bd2..670aa703 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -4,14 +4,14 @@ package chiselTests
 import Chisel._
 
 class Risc extends Module {
-  val io = new Bundle {
-    val isWr   = Bool(INPUT)
-    val wrAddr = UInt(INPUT, 8)
-    val wrData = Bits(INPUT, 32)
-    val boot   = Bool(INPUT)
-    val valid  = Bool(OUTPUT)
-    val out    = Bits(OUTPUT, 32)
-  }
+  val io = IO(new Bundle {
+    val isWr   = Input(Bool())
+    val wrAddr = Input(UInt(8))
+    val wrData = Input(Bits(32))
+    val boot   = Input(Bool())
+    val valid  = Output(Bool())
+    val out    = Output(Bits(32))
+  })
   val memSize = 256
   val file = Mem(memSize, Bits(width = 32))
   val code = Mem(memSize, Bits(width = 32))
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 0835fb4d..934c66a4 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -5,24 +5,24 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class SIntOps extends Module {
-  val io = new Bundle {
-    val a = SInt(INPUT, 16)
-    val b = SInt(INPUT, 16)
-    val addout = SInt(OUTPUT, 16)
-    val subout = SInt(OUTPUT, 16)
-    val timesout = SInt(OUTPUT, 16)
-    val divout = SInt(OUTPUT, 16)
-    val modout = SInt(OUTPUT, 16)
-    val lshiftout = SInt(OUTPUT, 16)
-    val rshiftout = SInt(OUTPUT, 16)
-    val lessout = Bool(OUTPUT)
-    val greatout = Bool(OUTPUT)
-    val eqout = Bool(OUTPUT)
-    val noteqout = Bool(OUTPUT)
-    val lesseqout = Bool(OUTPUT)
-    val greateqout = Bool(OUTPUT)
-    val negout = SInt(OUTPUT, 16)
-  }
+  val io = IO(new Bundle {
+    val a = Input(SInt(16))
+    val b = Input(SInt(16))
+    val addout = Output(SInt(16))
+    val subout = Output(SInt(16))
+    val timesout = Output(SInt(16))
+    val divout = Output(SInt(16))
+    val modout = Output(SInt(16))
+    val lshiftout = Output(SInt(16))
+    val rshiftout = Output(SInt(16))
+    val lessout = Output(Bool())
+    val greatout = Output(Bool())
+    val eqout = Output(Bool())
+    val noteqout = Output(Bool())
+    val lesseqout = Output(Bool())
+    val greateqout = Output(Bool())
+    val negout = Output(SInt(16))
+  })
 
   val a = io.a
   val b = io.b
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index c79eb8a4..751dc127 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -8,13 +8,13 @@ import org.scalatest.prop._
 import Chisel.testers.BasicTester
 
 class Tbl(w: Int, n: Int) extends Module {
-  val io = new Bundle {
-    val wi  = UInt(INPUT, log2Up(n))
-    val ri  = UInt(INPUT, log2Up(n))
-    val we  = Bool(INPUT)
-    val  d  = UInt(INPUT, w)
-    val  o  = UInt(OUTPUT, w)
-  }
+  val io = IO(new Bundle {
+    val wi  = Input(UInt(log2Up(n)))
+    val ri  = Input(UInt(log2Up(n)))
+    val we  = Input(Bool())
+    val  d  = Input(UInt(w))
+    val  o  = Output(UInt(w))
+  })
   val m = Mem(n, UInt(width = w))
   io.o := m(io.ri)
   when (io.we) {
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 943d9e4b..5239c6ba 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -41,32 +41,6 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
   }
 }
 
-class FunBundle extends Bundle {
-  val stuff = UInt(width = 10)
-}
-
-class ZeroModule extends Module {
-  val io = new Bundle {
-    val mem = UInt(width = 10)
-    val interrupts = Vec(2, Bool()).asInput
-    val mmio_axi = Vec(0, new FunBundle)
-    val mmio_ahb = Vec(0, new FunBundle).flip
-  }
-  
-  io.mmio_axi <> io.mmio_ahb
-  
-  io.mem := UInt(0)
-  when (io.interrupts(0)) { io.mem := UInt(1) }
-  when (io.interrupts(1)) { io.mem := UInt(2) }
-}
-
-class ZeroTester extends BasicTester {
-  val foo = Module(new ZeroModule)
-  foo.io.interrupts := Vec.tabulate(2) { _ => Bool(true) }
-  assert (foo.io.mem === UInt(2))
-  stop()
-}
-
 class VecSpec extends ChiselPropSpec {
   property("Vecs should be assignable") {
     forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) =>
@@ -81,8 +55,4 @@ class VecSpec extends ChiselPropSpec {
   property("Regs of vecs should be usable as shift registers") {
     forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } }
   }
-  
-  property("Dual empty Vectors") {
-    assertTesterPasses{ new ZeroTester }
-  }
 }
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 012fc493..5baff275 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -4,10 +4,11 @@ package chiselTests
 import Chisel._
 
 class VendingMachine extends Module {
-  val io = new Bundle {
-    val nickel = Bool(dir = INPUT)
-    val dime   = Bool(dir = INPUT)
-    val valid  = Bool(dir = OUTPUT) }
+  val io = IO(new Bundle {
+    val nickel = Input(Bool())
+    val dime   = Input(Bool())
+    val valid  = Output(Bool())
+  })
   val c = UInt(5, width = 3)
   val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
   val state = Reg(init = sIdle)
-- 
cgit v1.2.3


From 083610b2faa456dfccc4365dd115565d36e522fa Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 21 Jun 2016 10:13:51 -0700
Subject: Most of the remaining tests with Module, IO wrapping.

---
 src/main/scala/Chisel/util/Arbiter.scala        | 14 +++----
 src/test/scala/chiselTests/BlackBox.scala       | 32 ++++++++--------
 src/test/scala/chiselTests/ComplexAssign.scala  | 10 ++---
 src/test/scala/chiselTests/Direction.scala      |  8 ++--
 src/test/scala/chiselTests/GCD.scala            | 14 +++----
 src/test/scala/chiselTests/MemorySearch.scala   | 12 +++---
 src/test/scala/chiselTests/MulLookup.scala      | 10 ++---
 src/test/scala/chiselTests/Padding.scala        | 10 ++---
 src/test/scala/chiselTests/Stack.scala          | 14 +++----
 src/test/scala/chiselTests/UIntOps.scala        | 50 ++++++++++++-------------
 src/test/scala/chiselTests/VectorPacketIO.scala |  9 +++--
 11 files changed, 92 insertions(+), 91 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/Chisel/util/Arbiter.scala
index 16ae9be5..5cef4b24 100644
--- a/src/main/scala/Chisel/util/Arbiter.scala
+++ b/src/main/scala/Chisel/util/Arbiter.scala
@@ -7,9 +7,9 @@ package Chisel
 
 /** An I/O bundle for the Arbiter */
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
-  val in  = Vec(n, Decoupled(gen)).flip
-  val out = Decoupled(gen)
-  val chosen = UInt(OUTPUT, log2Up(n))
+  val in  = Flipped(Vec(n, DecoupledIO(gen)))
+  val out = DecoupledIO(gen)
+  val chosen = Output(UInt(log2Up(n)))
 }
 
 /** Arbiter Control determining which producer has access */
@@ -25,7 +25,7 @@ private object ArbiterCtrl
 abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module {
   def grant: Seq[Bool]
   def choice: UInt
-  val io = new ArbiterIO(gen, n)
+  val io = IO(new ArbiterIO(gen, n))
 
   io.chosen := choice
   io.out.valid := io.in(io.chosen).valid
@@ -37,7 +37,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
     val locked = lockCount.value =/= UInt(0)
     val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
 
-    when (io.out.fire() && wantsLock) {
+    when (io.out.firing && wantsLock) {
       lockIdx := io.chosen
       lockCount.inc()
     }
@@ -53,7 +53,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
-  lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
+  lazy val lastGrant = RegEnable(io.chosen, io.out.firing)
   lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
   lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
 
@@ -99,7 +99,7 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
    consumer.io.in <> arb.io.out
  */
 class Arbiter[T <: Data](gen: T, n: Int) extends Module {
-  val io = new ArbiterIO(gen, n)
+  val io = IO(new ArbiterIO(gen, n))
 
   io.chosen := UInt(n-1)
   io.out.bits := io.in(n-1).bits
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index ca94087c..5877149f 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -8,25 +8,25 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class BlackBoxInverter extends BlackBox {
-  val io = new Bundle() {
-    val in = Bool(INPUT)
-    val out = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle() {
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
 }
 
 class BlackBoxPassthrough extends BlackBox {
-  val io = new Bundle() {
-    val in = Bool(INPUT)
-    val out = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle() {
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
 }
 
 class BlackBoxRegister extends BlackBox {
-  val io = new Bundle() {
-    val clock = Clock().asInput
-    val in = Bool(INPUT)
-    val out = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle() {
+    val clock = Input(Clock())
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
 }
 
 class BlackBoxTester extends BasicTester {
@@ -84,9 +84,9 @@ class BlackBoxWithClockTester extends BasicTester {
 /*
 // Must determine how to handle parameterized Verilog
 class BlackBoxConstant(value: Int) extends BlackBox {
-  val io = new Bundle() {
-    val out = UInt(width=log2Up(value)).asOutput
-  }
+  val io = IO(new Bundle() {
+    val out = Output(UInt(width=log2Up(value)))
+  })
   override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) "
 }
 
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index d79a2625..58f26c1f 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -13,11 +13,11 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
 }
 
 class ComplexAssign(w: Int) extends Module {
-  val io = new Bundle {
-    val e   = new Bool(INPUT)
-    val in  = new Complex(UInt(width = w), UInt(width = w)).asInput
-    val out = new Complex(UInt(width = w), UInt(width = w)).asOutput
-  }
+  val io = IO(new Bundle {
+    val e   = Input(Bool())
+    val in  = Input(new Complex(UInt(width = w), UInt(width = w)))
+    val out = Output(new Complex(UInt(width = w), UInt(width = w)))
+  })
   when (io.e) {
     val tmp = Wire(new Complex(UInt(width = w), UInt(width = w)))
     tmp := io.in
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index dd2f6572..28b00adb 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -8,10 +8,10 @@ import org.scalatest.prop._
 import Chisel.testers.BasicTester
 
 class DirectionHaver extends Module {
-  val io = new Bundle {
-    val in = UInt(INPUT, 32)
-    val out = UInt(OUTPUT, 32)
-  }
+  val io = IO(new Bundle {
+    val in = Input(UInt(32))
+    val out = Output(UInt(32))
+  })
 }
 
 class GoodDirection extends DirectionHaver {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index a1bfffda..edb8c80f 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -8,13 +8,13 @@ import org.scalatest._
 import org.scalatest.prop._
 
 class GCD extends Module {
-  val io = new Bundle {
-    val a  = UInt(INPUT, 32)
-    val b  = UInt(INPUT, 32)
-    val e  = Bool(INPUT)
-    val z  = UInt(OUTPUT, 32)
-    val v  = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val a  = Input(UInt(32))
+    val b  = Input(UInt(32))
+    val e  = Input(Bool())
+    val z  = Output(UInt(32))
+    val v  = Output(Bool())
+  })
   val x = Reg(UInt(width = 32))
   val y = Reg(UInt(width = 32))
   when (x > y)   { x := x -% y }
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 55b704a0..a321522b 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -5,12 +5,12 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class MemorySearch extends Module {
-  val io = new Bundle {
-    val target  = UInt(INPUT,  4)
-    val en      = Bool(INPUT)
-    val done    = Bool(OUTPUT)
-    val address = UInt(OUTPUT, 3)
-  }
+  val io = IO(new Bundle {
+    val target  = Input(UInt(4))
+    val en      = Input(Bool())
+    val done    = Output(Bool())
+    val address = Output(UInt(3))
+  })
   val vals  = Array(0, 4, 15, 14, 2, 5, 13)
   val index = Reg(init = UInt(0, width = 3))
   val elts  = Vec(vals.map(UInt(_,4)))
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 49ba13c7..1e5ee798 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -8,11 +8,11 @@ import org.scalatest.prop._
 import Chisel.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
-  val io = new Bundle {
-    val x   = UInt(INPUT,  w)
-    val y   = UInt(INPUT,  w)
-    val z   = UInt(OUTPUT, 2 * w)
-  }
+  val io = IO(new Bundle {
+    val x   = Input(UInt(w))
+    val y   = Input(UInt(w))
+    val z   = Output(UInt(2 * w))
+  })
   val tbl = Vec(
     for {
       i <- 0 until 1 << w
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 999b7d36..1f33f8ab 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -4,11 +4,11 @@ package chiselTests
 import Chisel._
 
 class Padder extends Module {
-  val io = new Bundle {
-    val a   = Bits(INPUT,  4)
-    val asp = SInt(OUTPUT, 8)
-    val aup = UInt(OUTPUT, 8)
-  }
+  val io = IO(new Bundle {
+    val a   = Input(UInt(4))
+    val asp = Output(SInt(8))
+    val aup = Output(UInt(8))
+  })
   io.asp := io.a.asSInt
   io.aup := io.a.asUInt
 }
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ac799c8a..46e5dc23 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -5,13 +5,13 @@ import scala.collection.mutable.Stack
 import Chisel._
 
 class ChiselStack(val depth: Int) extends Module {
-  val io = new Bundle {
-    val push    = Bool(INPUT)
-    val pop     = Bool(INPUT)
-    val en      = Bool(INPUT)
-    val dataIn  = UInt(INPUT,  32)
-    val dataOut = UInt(OUTPUT, 32)
-  }
+  val io = IO(new Bundle {
+    val push    = Input(Bool())
+    val pop     = Input(Bool())
+    val en      = Input(Bool())
+    val dataIn  = Input(UInt(32))
+    val dataOut = Output(UInt(32))
+  })
 
   val stack_mem = Mem(depth, UInt(width = 32))
   val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index bb0b0f06..4e8506cf 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -6,23 +6,23 @@ import org.scalatest._
 import Chisel.testers.BasicTester
 
 class UIntOps extends Module {
-  val io = new Bundle {
-    val a = UInt(INPUT, 16)
-    val b = UInt(INPUT, 16)
-    val addout = UInt(OUTPUT, 16)
-    val subout = UInt(OUTPUT, 16)
-    val timesout = UInt(OUTPUT, 16)
-    val divout = UInt(OUTPUT, 16)
-    val modout = UInt(OUTPUT, 16)
-    val lshiftout = UInt(OUTPUT, 16)
-    val rshiftout = UInt(OUTPUT, 16)
-    val lessout = Bool(OUTPUT)
-    val greatout = Bool(OUTPUT)
-    val eqout = Bool(OUTPUT)
-    val noteqout = Bool(OUTPUT)
-    val lesseqout = Bool(OUTPUT)
-    val greateqout = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val a = Input(UInt(16))
+    val b = Input(UInt(16))
+    val addout = Output(UInt(16))
+    val subout = Output(UInt(16))
+    val timesout = Output(UInt(16))
+    val divout = Output(UInt(16))
+    val modout = Output(UInt(16))
+    val lshiftout = Output(UInt(16))
+    val rshiftout = Output(UInt(16))
+    val lessout = Output(Bool())
+    val greatout = Output(Bool())
+    val eqout = Output(Bool())
+    val noteqout = Output(Bool())
+    val lesseqout = Output(Bool())
+    val greateqout = Output(Bool())
+  })
 
   val a = io.a
   val b = io.b
@@ -76,18 +76,18 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) {
 */
 
 class GoodBoolConversion extends Module {
-  val io = new Bundle {
-    val u = UInt(1, width = 1).asInput
-    val b = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val u = Input(UInt(1))
+    val b = Output(Bool())
+  })
   io.b := io.u.toBool
 }
 
 class BadBoolConversion extends Module {
-  val io = new Bundle {
-    val u = UInt(1, width = 5).asInput
-    val b = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val u = Input(UInt(width = 5))
+    val b = Output(Bool())
+  })
   io.b := io.u.toBool
 }
 
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 99ec66a6..936541c0 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -27,8 +27,8 @@ class Packet extends Bundle {
   * The problem does not occur if the Vec is taken out
   */
 class VectorPacketIO(n: Int) extends Bundle {
-  val ins  = Vec(n, new DeqIO(new Packet()))
-  val outs = Vec(n, new EnqIO(new Packet()))
+  val ins  = Vec(n, DeqIO(new Packet()))
+  val outs = Vec(n, EnqIO(new Packet()))
 }
 
 /**
@@ -37,10 +37,11 @@ class VectorPacketIO(n: Int) extends Bundle {
   */
 class BrokenVectorPacketModule extends Module {
   val n  = 4
-  val io = new VectorPacketIO(n)
+  val io = IO(new VectorPacketIO(n))
 
   /* the following method of initializing the circuit may change in the future */
-  io.outs.foreach(_.init())
+  io.ins.foreach(_.noenq())
+  io.outs.foreach(_.nodeq())
 }
 
 class VectorPacketIOUnitTester extends BasicTester {
-- 
cgit v1.2.3


From c5f9ea3133ef363ff8944e17d94fea79767b6bed Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 10:01:23 -0700
Subject: Rename "Chisel" to "chisel3" (only git mv).

---
 src/main/scala/Chisel/BitPat.scala                 |  88 ----------
 src/main/scala/Chisel/Driver.scala                 | 132 ---------------
 src/main/scala/Chisel/FileSystemUtilities.scala    |  10 --
 src/main/scala/Chisel/ImplicitConversions.scala    |   8 -
 src/main/scala/Chisel/Main.scala                   |  17 --
 .../scala/Chisel/internal/firrtl/Emitter.scala     | 112 -------------
 src/main/scala/Chisel/package.scala                |  31 ----
 src/main/scala/Chisel/testers/BasicTester.scala    |  38 -----
 src/main/scala/Chisel/testers/TesterDriver.scala   |  68 --------
 src/main/scala/Chisel/throwException.scala         |  12 --
 src/main/scala/Chisel/util/Arbiter.scala           | 117 -------------
 src/main/scala/Chisel/util/Bitwise.scala           |  71 --------
 src/main/scala/Chisel/util/Cat.scala               |  18 --
 src/main/scala/Chisel/util/CircuitMath.scala       |  26 ---
 src/main/scala/Chisel/util/Conditional.scala       |  69 --------
 src/main/scala/Chisel/util/Counter.scala           |  44 -----
 src/main/scala/Chisel/util/Decoupled.scala         | 183 ---------------------
 src/main/scala/Chisel/util/Enum.scala              |  21 ---
 src/main/scala/Chisel/util/LFSR.scala              |  22 ---
 src/main/scala/Chisel/util/Lookup.scala            |  17 --
 src/main/scala/Chisel/util/Math.scala              |  42 -----
 src/main/scala/Chisel/util/Mux.scala               |  61 -------
 src/main/scala/Chisel/util/OneHot.scala            |  62 -------
 src/main/scala/Chisel/util/Reg.scala               |  55 -------
 src/main/scala/Chisel/util/TransitName.scala       |  21 ---
 src/main/scala/Chisel/util/Valid.scala             |  59 -------
 src/main/scala/chisel3/Driver.scala                | 132 +++++++++++++++
 .../compatibility/FileSystemUtilities.scala        |  10 ++
 src/main/scala/chisel3/compatibility/Main.scala    |  17 ++
 .../chisel3/compatibility/throwException.scala     |  12 ++
 .../scala/chisel3/internal/firrtl/Emitter.scala    | 112 +++++++++++++
 src/main/scala/chisel3/package.scala               |  31 ++++
 src/main/scala/chisel3/testers/BasicTester.scala   |  38 +++++
 src/main/scala/chisel3/testers/TesterDriver.scala  |  68 ++++++++
 src/main/scala/chisel3/util/Arbiter.scala          | 117 +++++++++++++
 src/main/scala/chisel3/util/BitPat.scala           |  88 ++++++++++
 src/main/scala/chisel3/util/Bitwise.scala          |  71 ++++++++
 src/main/scala/chisel3/util/Cat.scala              |  18 ++
 src/main/scala/chisel3/util/CircuitMath.scala      |  26 +++
 src/main/scala/chisel3/util/Conditional.scala      |  69 ++++++++
 src/main/scala/chisel3/util/Counter.scala          |  44 +++++
 src/main/scala/chisel3/util/Decoupled.scala        | 183 +++++++++++++++++++++
 src/main/scala/chisel3/util/Enum.scala             |  21 +++
 .../scala/chisel3/util/ImplicitConversions.scala   |   8 +
 src/main/scala/chisel3/util/LFSR.scala             |  22 +++
 src/main/scala/chisel3/util/Lookup.scala           |  17 ++
 src/main/scala/chisel3/util/Math.scala             |  42 +++++
 src/main/scala/chisel3/util/Mux.scala              |  61 +++++++
 src/main/scala/chisel3/util/OneHot.scala           |  62 +++++++
 src/main/scala/chisel3/util/Reg.scala              |  55 +++++++
 src/main/scala/chisel3/util/TransitName.scala      |  21 +++
 src/main/scala/chisel3/util/Valid.scala            |  59 +++++++
 52 files changed, 1404 insertions(+), 1404 deletions(-)
 delete mode 100644 src/main/scala/Chisel/BitPat.scala
 delete mode 100644 src/main/scala/Chisel/Driver.scala
 delete mode 100644 src/main/scala/Chisel/FileSystemUtilities.scala
 delete mode 100644 src/main/scala/Chisel/ImplicitConversions.scala
 delete mode 100644 src/main/scala/Chisel/Main.scala
 delete mode 100644 src/main/scala/Chisel/internal/firrtl/Emitter.scala
 delete mode 100644 src/main/scala/Chisel/package.scala
 delete mode 100644 src/main/scala/Chisel/testers/BasicTester.scala
 delete mode 100644 src/main/scala/Chisel/testers/TesterDriver.scala
 delete mode 100644 src/main/scala/Chisel/throwException.scala
 delete mode 100644 src/main/scala/Chisel/util/Arbiter.scala
 delete mode 100644 src/main/scala/Chisel/util/Bitwise.scala
 delete mode 100644 src/main/scala/Chisel/util/Cat.scala
 delete mode 100644 src/main/scala/Chisel/util/CircuitMath.scala
 delete mode 100644 src/main/scala/Chisel/util/Conditional.scala
 delete mode 100644 src/main/scala/Chisel/util/Counter.scala
 delete mode 100644 src/main/scala/Chisel/util/Decoupled.scala
 delete mode 100644 src/main/scala/Chisel/util/Enum.scala
 delete mode 100644 src/main/scala/Chisel/util/LFSR.scala
 delete mode 100644 src/main/scala/Chisel/util/Lookup.scala
 delete mode 100644 src/main/scala/Chisel/util/Math.scala
 delete mode 100644 src/main/scala/Chisel/util/Mux.scala
 delete mode 100644 src/main/scala/Chisel/util/OneHot.scala
 delete mode 100644 src/main/scala/Chisel/util/Reg.scala
 delete mode 100644 src/main/scala/Chisel/util/TransitName.scala
 delete mode 100644 src/main/scala/Chisel/util/Valid.scala
 create mode 100644 src/main/scala/chisel3/Driver.scala
 create mode 100644 src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
 create mode 100644 src/main/scala/chisel3/compatibility/Main.scala
 create mode 100644 src/main/scala/chisel3/compatibility/throwException.scala
 create mode 100644 src/main/scala/chisel3/internal/firrtl/Emitter.scala
 create mode 100644 src/main/scala/chisel3/package.scala
 create mode 100644 src/main/scala/chisel3/testers/BasicTester.scala
 create mode 100644 src/main/scala/chisel3/testers/TesterDriver.scala
 create mode 100644 src/main/scala/chisel3/util/Arbiter.scala
 create mode 100644 src/main/scala/chisel3/util/BitPat.scala
 create mode 100644 src/main/scala/chisel3/util/Bitwise.scala
 create mode 100644 src/main/scala/chisel3/util/Cat.scala
 create mode 100644 src/main/scala/chisel3/util/CircuitMath.scala
 create mode 100644 src/main/scala/chisel3/util/Conditional.scala
 create mode 100644 src/main/scala/chisel3/util/Counter.scala
 create mode 100644 src/main/scala/chisel3/util/Decoupled.scala
 create mode 100644 src/main/scala/chisel3/util/Enum.scala
 create mode 100644 src/main/scala/chisel3/util/ImplicitConversions.scala
 create mode 100644 src/main/scala/chisel3/util/LFSR.scala
 create mode 100644 src/main/scala/chisel3/util/Lookup.scala
 create mode 100644 src/main/scala/chisel3/util/Math.scala
 create mode 100644 src/main/scala/chisel3/util/Mux.scala
 create mode 100644 src/main/scala/chisel3/util/OneHot.scala
 create mode 100644 src/main/scala/chisel3/util/Reg.scala
 create mode 100644 src/main/scala/chisel3/util/TransitName.scala
 create mode 100644 src/main/scala/chisel3/util/Valid.scala

(limited to 'src')

diff --git a/src/main/scala/Chisel/BitPat.scala b/src/main/scala/Chisel/BitPat.scala
deleted file mode 100644
index 96206f63..00000000
--- a/src/main/scala/Chisel/BitPat.scala
+++ /dev/null
@@ -1,88 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-import scala.language.experimental.macros
-
-import Chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-
-object BitPat {
-  /** Parses a bit pattern string into (bits, mask, width).
-    *
-    * @return bits the literal value, with don't cares being 0
-    * @return mask the mask bits, with don't cares being 0 and cares being 1
-    * @return width the number of bits in the literal, including values and
-    * don't cares.
-    */
-  private def parse(x: String): (BigInt, BigInt, Int) = {
-    // Notes:
-    // While Verilog Xs also handle octal and hex cases, there isn't a
-    // compelling argument and no one has asked for it.
-    // If ? parsing is to be exposed, the return API needs further scrutiny
-    // (especially with things like mask polarity).
-    require(x.head == 'b', "BitPats must be in binary and be prefixed with 'b'")
-    var bits = BigInt(0)
-    var mask = BigInt(0)
-    for (d <- x.tail) {
-      if (d != '_') {
-        require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d)
-        mask = (mask << 1) + (if (d == '?') 0 else 1)
-        bits = (bits << 1) + (if (d == '1') 1 else 0)
-      }
-    }
-    (bits, mask, x.length - 1)
-  }
-
-  /** Creates a [[BitPat]] literal from a string.
-   *
-    * @param n the literal value as a string, in binary, prefixed with 'b'
-    * @note legal characters are '0', '1', and '?', as well as '_' as white
-    * space (which are ignored)
-    */
-  def apply(n: String): BitPat = {
-    val (bits, mask, width) = parse(n)
-    new BitPat(bits, mask, width)
-  }
-
-  /** Creates a [[BitPat]] of all don't cares of the specified bitwidth. */
-  def dontCare(width: Int): BitPat = BitPat("b" + ("?" * width))
-
-  @deprecated("Use BitPat.dontCare", "chisel3")
-  def DC(width: Int): BitPat = dontCare(width)  // scalastyle:ignore method.name
-
-  /** Allows BitPats to be used where a UInt is expected.
-    *
-    * @note the BitPat must not have don't care bits (will error out otherwise)
-    */
-  def bitPatToUInt(x: BitPat): UInt = {
-    require(x.mask == (BigInt(1) << x.getWidth) - 1)
-    UInt(x.value, x.getWidth)
-  }
-
-  /** Allows UInts to be used where a BitPat is expected, useful for when an
-    * interface is defined with BitPats but not all cases need the partial
-    * matching capability.
-    *
-    * @note the UInt must be a literal
-    */
-  def apply(x: UInt): BitPat = {
-    require(x.isLit)
-    BitPat("b" + x.litValue.toString(2))
-  }
-}
-
-// TODO: Break out of Core? (this doesn't involve FIRRTL generation)
-/** Bit patterns are literals with masks, used to represent values with don't
-  * cares. Equality comparisons will ignore don't care bits (for example,
-  * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)).
-  */
-sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
-  def getWidth: Int = width
-  def === (that: UInt): Bool = macro SourceInfoTransform.thatArg
-  def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
-  def != (that: UInt): Bool = macro SourceInfoTransform.thatArg
-
-  def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask))
-  def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that)
-  def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that
-}
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
deleted file mode 100644
index 02204684..00000000
--- a/src/main/scala/Chisel/Driver.scala
+++ /dev/null
@@ -1,132 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-import scala.sys.process._
-import java.io._
-
-import internal._
-import internal.firrtl._
-
-trait BackendCompilationUtilities {
-  /** Create a temporary directory with the prefix name. Exists here because it doesn't in Java 6.
-    */
-  def createTempDirectory(prefix: String): File = {
-    val temp = File.createTempFile(prefix, "")
-    if (!temp.delete()) {
-      throw new IOException(s"Unable to delete temp file '$temp'")
-    }
-    if (!temp.mkdir()) {
-      throw new IOException(s"Unable to create temp directory '$temp'")
-    }
-    temp
-  }
-
-  def makeHarness(template: String => String, post: String)(f: File): File = {
-    val prefix = f.toString.split("/").last
-    val vf = new File(f.toString + post)
-    val w = new FileWriter(vf)
-    w.write(template(prefix))
-    w.close()
-    vf
-  }
-
-  def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder = {
-    Process(
-      Seq("firrtl",
-          "-i", s"$prefix.fir",
-          "-o", s"$prefix.v",
-          "-X", "verilog"),
-      dir)
-  }
-
-  /** Generates a Verilator invocation to convert Verilog sources to C++
-    * simulation sources.
-    *
-    * The Verilator prefix will be V$dutFile, and running this will generate
-    * C++ sources and headers as well as a makefile to compile them.
-    *
-    * @param dutFile name of the DUT .v without the .v extension
-    * @param name of the top-level module in the design
-    * @param dir output directory
-    * @param vSources list of additional Verilog sources to compile
-    * @param cppHarness C++ testharness to compile/link against
-    */
-  def verilogToCpp(
-      dutFile: String,
-      topModule: String,
-      dir: File,
-      vSources: Seq[File],
-      cppHarness: File
-                  ): ProcessBuilder = {
-    val command = Seq("verilator",
-      "--cc", s"$dutFile.v") ++
-      vSources.map(file => Seq("-v", file.toString)).flatten ++
-      Seq("--assert",
-        "-Wno-fatal",
-        "-Wno-WIDTH",
-        "-Wno-STMTDLY",
-        "--trace",
-        "-O2",
-        "--top-module", topModule,
-        "+define+TOP_TYPE=V" + dutFile,
-        s"+define+PRINTF_COND=!$topModule.reset",
-        "-CFLAGS",
-        s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
-        "-Mdir", dir.toString,
-        "--exe", cppHarness.toString)
-    System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex
-    command
-  }
-
-  def cppToExe(prefix: String, dir: File): ProcessBuilder =
-    Seq("make", "-C", dir.toString, "-j", "-f", s"V${prefix}.mk", s"V${prefix}")
-
-  def executeExpectingFailure(
-      prefix: String,
-      dir: File,
-      assertionMsg: String = "Assertion failed"): Boolean = {
-    var triggered = false
-    val e = Process(s"./V${prefix}", dir) !
-      ProcessLogger(line => {
-        triggered = triggered || line.contains(assertionMsg)
-        System.out.println(line) // scalastyle:ignore regex
-      })
-    triggered
-  }
-
-  def executeExpectingSuccess(prefix: String, dir: File): Boolean = {
-    !executeExpectingFailure(prefix, dir)
-  }
-}
-
-object Driver extends BackendCompilationUtilities {
-
-  /** Elaborates the Module specified in the gen function into a Circuit
-    *
-    *  @param gen a function that creates a Module hierarchy
-    *  @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR)
-    */
-  def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen()))
-
-  def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen))
-
-  def dumpFirrtl(ir: Circuit, optName: Option[File]): File = {
-    val f = optName.getOrElse(new File(ir.name + ".fir"))
-    val w = new FileWriter(f)
-    w.write(Emitter.emit(ir))
-    w.close()
-    f
-  }
-
-  private var target_dir: Option[String] = None
-  def parseArgs(args: Array[String]): Unit = {
-    for (i <- 0 until args.size) {
-      if (args(i) == "--targetDir") {
-        target_dir = Some(args(i + 1))
-      }
-    }
-  }
-
-  def targetDir(): String = { target_dir getOrElse new File(".").getCanonicalPath }
-}
diff --git a/src/main/scala/Chisel/FileSystemUtilities.scala b/src/main/scala/Chisel/FileSystemUtilities.scala
deleted file mode 100644
index 575ae138..00000000
--- a/src/main/scala/Chisel/FileSystemUtilities.scala
+++ /dev/null
@@ -1,10 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-@deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0")
-trait FileSystemUtilities {
-  def createOutputFile(name: String): java.io.FileWriter  = {
-    new java.io.FileWriter(Driver.targetDir + "/" + name)
-  }
-}
diff --git a/src/main/scala/Chisel/ImplicitConversions.scala b/src/main/scala/Chisel/ImplicitConversions.scala
deleted file mode 100644
index 6a230022..00000000
--- a/src/main/scala/Chisel/ImplicitConversions.scala
+++ /dev/null
@@ -1,8 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-object ImplicitConversions {
-  implicit def intToUInt(x: Int): UInt = UInt(x)
-  implicit def booleanToBool(x: Boolean): Bool = Bool(x)
-}
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala
deleted file mode 100644
index a72debc3..00000000
--- a/src/main/scala/Chisel/Main.scala
+++ /dev/null
@@ -1,17 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-import java.io.File
-
-@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
-  def apply[T <: Module](args: Array[String], gen: () => T): Unit =
-    Predef.assert(false, "No more chiselMain in Chisel3")
-
-  def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
-    val circuit = Driver.elaborate(gen)
-    Driver.parseArgs(args)
-    val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
-    Driver.dumpFirrtl(circuit, Option(output_file))
-  }
-}
diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/Chisel/internal/firrtl/Emitter.scala
deleted file mode 100644
index 7ca3268a..00000000
--- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ /dev/null
@@ -1,112 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel.internal.firrtl
-import Chisel._
-import Chisel.internal.sourceinfo.{NoSourceInfo, SourceLine}
-
-private[Chisel] object Emitter {
-  def emit(circuit: Circuit): String = new Emitter(circuit).toString
-}
-
-private class Emitter(circuit: Circuit) {
-  override def toString: String = res.toString
-
-  private def emitPort(e: Port): String =
-    s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}"
-  private def emit(e: Command, ctx: Component): String = {
-    val firrtlLine = e match {
-      case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
-      case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
-      case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}"
-      case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
-      case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]"
-      case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]"
-      case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
-      case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
-      case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
-      case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})"
-      case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})"""
-      case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
-      case e: DefInstance => {
-        val modName = moduleMap.get(e.id.name).get
-        s"inst ${e.name} of $modName"
-      }
-
-      case w: WhenBegin =>
-        indent()
-        s"when ${w.pred.fullName(ctx)} :"
-      case _: WhenEnd =>
-        unindent()
-        s"skip"
-    }
-    e.sourceInfo match {
-      case SourceLine(filename, line, col) => s"${firrtlLine} @[${filename} ${line}:${col}] "
-      case _: NoSourceInfo => firrtlLine
-    }
-  }
-
-  // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.
-  private val defnMap = collection.mutable.HashMap[String, String]()
-  // Map of Component name to FIRRTL id.
-  private val moduleMap = collection.mutable.HashMap[String, String]()
-
-  /** Generates the FIRRTL module definition with a specified name.
-    */
-  private def moduleDefn(m: Component, name: String): String = {
-    val body = new StringBuilder
-    m.id match {
-      case _: BlackBox => body ++= newline + s"extmodule $name : "
-      case _: Module => body ++= newline + s"module $name : "
-    }
-    withIndent {
-      for (p <- m.ports)
-        body ++= newline + emitPort(p)
-      body ++= newline
-
-      m.id match {
-        case _: BlackBox =>
-          // TODO: BlackBoxes should be empty, but funkiness in Module() means
-          // it's not for now. Eventually, this should assert out.
-        case _: Module => for (cmd <- m.commands) {
-          body ++= newline + emit(cmd, m)
-        }
-      }
-      body ++= newline
-    }
-    body.toString()
-  }
-
-  /** Returns the FIRRTL declaration and body of a module, or nothing if it's a
-    * duplicate of something already emitted (on the basis of simple string
-    * matching).
-    */
-  private def emit(m: Component): String = {
-    // Generate the body.
-    val moduleName = m.id.getClass.getName.split('.').last
-    val defn = moduleDefn(m, moduleName)
-
-    defnMap get defn match {
-      case Some(deduplicatedName) =>
-        moduleMap(m.name) = deduplicatedName
-        ""
-      case None =>
-        require(!(moduleMap contains m.name),
-            "emitting module with same name but different contents")
-
-        moduleMap(m.name) = m.name
-        defnMap(defn) = m.name
-
-        moduleDefn(m, m.name)
-    }
-  }
-
-  private var indentLevel = 0
-  private def newline = "\n" + ("  " * indentLevel)
-  private def indent(): Unit = indentLevel += 1
-  private def unindent() { require(indentLevel > 0); indentLevel -= 1 }
-  private def withIndent(f: => Unit) { indent(); f; unindent() }
-
-  private val res = new StringBuilder(s"circuit ${circuit.name} : ")
-  withIndent { circuit.components.foreach(c => res ++= emit(c)) }
-  res ++= newline
-}
diff --git a/src/main/scala/Chisel/package.scala b/src/main/scala/Chisel/package.scala
deleted file mode 100644
index f05e8b5d..00000000
--- a/src/main/scala/Chisel/package.scala
+++ /dev/null
@@ -1,31 +0,0 @@
-package object Chisel {
-  import scala.language.experimental.macros
-  
-  import internal.firrtl.Width
-  import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-  
-  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
-    def U: UInt = UInt(x, Width())
-    def S: SInt = SInt(x, Width())
-  }
-  implicit class fromIntToLiteral(val x: Int) extends AnyVal {
-    def U: UInt = UInt(BigInt(x), Width())
-    def S: SInt = SInt(BigInt(x), Width())
-  }
-  implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt(x)
-  }
-  implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
-    def B: Bool = Bool(x)
-  }
-  
-  implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
-    final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-    final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-    final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-  
-    def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x
-    def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
-    def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
-  }
-}
diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/Chisel/testers/BasicTester.scala
deleted file mode 100644
index b8c1494a..00000000
--- a/src/main/scala/Chisel/testers/BasicTester.scala
+++ /dev/null
@@ -1,38 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel.testers
-import Chisel._
-
-import scala.language.experimental.macros
-
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
-
-class BasicTester extends Module {
-  // The testbench has no IOs, rather it should communicate using printf, assert, and stop.
-  val io = new Bundle()
-
-  def popCount(n: Long): Int = n.toBinaryString.count(_=='1')
-
-  /** Ends the test reporting success.
-    *
-    * Does not fire when in reset (defined as the encapsulating Module's
-    * reset). If your definition of reset is not the encapsulating Module's
-    * reset, you will need to gate this externally.
-    */
-  def stop()(implicit sourceInfo: SourceInfo) {
-    // TODO: rewrite this using library-style SourceInfo passing.
-    when (!reset) {
-      pushCommand(Stop(sourceInfo, Node(clock), 0))
-    }
-  }
-
-  /** The finish method provides a hook that subclasses of BasicTester can use to
-    * alter a circuit after their constructor has been called.
-    * For example, a specialized tester subclassing BasicTester could override finish in order to
-    * add flow control logic for a decoupled io port of a device under test
-    */
-  def finish(): Unit = {}
-}
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala
deleted file mode 100644
index a56bb8b7..00000000
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ /dev/null
@@ -1,68 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel.testers
-import Chisel._
-import scala.io.Source
-import scala.sys.process._
-import java.io._
-
-object TesterDriver extends BackendCompilationUtilities {
-  /** Copy the contents of a resource to a destination file.
-    */
-  def copyResourceToFile(name: String, file: File) {
-    val in = getClass().getResourceAsStream(name)
-    if (in == null) {
-      throw new FileNotFoundException(s"Resource '$name'")
-    }
-    val out = new FileOutputStream(file)
-    Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write)
-    out.close()
-  }
-
-  /** For use with modules that should successfully be elaborated by the
-    * frontend, and which can be turned into executables with assertions. */
-  def execute(t: () => BasicTester, additionalVResources: Seq[String] = Seq()): Boolean = {
-    // Invoke the chisel compiler to get the circuit's IR
-    val circuit = Driver.elaborate(finishWrapper(t))
-
-    // Set up a bunch of file handlers based on a random temp filename,
-    // plus the quirks of Verilator's naming conventions
-    val target = circuit.name
-
-    val path = createTempDirectory(target)
-    val fname = new File(path, target)
-
-    // For now, dump the IR out to a file
-    Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
-
-    // Copy CPP harness and other Verilog sources from resources into files
-    val cppHarness =  new File(path, "top.cpp")
-    copyResourceToFile("/top.cpp", cppHarness)
-    val additionalVFiles = additionalVResources.map((name: String) => {
-      val mangledResourceName = name.replace("/", "_")
-      val out = new File(path, mangledResourceName)
-      copyResourceToFile(name, out)
-      out
-    })
-
-    // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-    if ((firrtlToVerilog(target, path) #&&
-        verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&&
-        cppToExe(target, path)).! == 0) {
-      executeExpectingSuccess(target, path)
-    } else {
-      false
-    }
-  }
-  /**
-    * Calls the finish method of an BasicTester or a class that extends it.
-    * The finish method is a hook for code that augments the circuit built in the constructor.
-    */
-  def finishWrapper(test: () => BasicTester): () => BasicTester = {
-    () => {
-      val tester = test()
-      tester.finish()
-      tester
-    }
-  }
-}
diff --git a/src/main/scala/Chisel/throwException.scala b/src/main/scala/Chisel/throwException.scala
deleted file mode 100644
index 702884aa..00000000
--- a/src/main/scala/Chisel/throwException.scala
+++ /dev/null
@@ -1,12 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-@deprecated("throwException doesn't exist in Chisel3", "3.0.0")
-@throws(classOf[Exception])
-object throwException {
-  def apply(s: String, t: Throwable = null) = {
-    val xcpt = new Exception(s, t)
-    throw xcpt
-  }
-}
diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/Chisel/util/Arbiter.scala
deleted file mode 100644
index 16ae9be5..00000000
--- a/src/main/scala/Chisel/util/Arbiter.scala
+++ /dev/null
@@ -1,117 +0,0 @@
-// See LICENSE for license details.
-
-/** Arbiters in all shapes and sizes.
-  */
-
-package Chisel
-
-/** An I/O bundle for the Arbiter */
-class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
-  val in  = Vec(n, Decoupled(gen)).flip
-  val out = Decoupled(gen)
-  val chosen = UInt(OUTPUT, log2Up(n))
-}
-
-/** Arbiter Control determining which producer has access */
-private object ArbiterCtrl
-{
-  def apply(request: Seq[Bool]): Seq[Bool] = request.length match {
-    case 0 => Seq()
-    case 1 => Seq(Bool(true))
-    case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
-  }
-}
-
-abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module {
-  def grant: Seq[Bool]
-  def choice: UInt
-  val io = new ArbiterIO(gen, n)
-
-  io.chosen := choice
-  io.out.valid := io.in(io.chosen).valid
-  io.out.bits := io.in(io.chosen).bits
-
-  if (count > 1) {
-    val lockCount = Counter(count)
-    val lockIdx = Reg(UInt())
-    val locked = lockCount.value =/= UInt(0)
-    val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
-
-    when (io.out.fire() && wantsLock) {
-      lockIdx := io.chosen
-      lockCount.inc()
-    }
-
-    when (locked) { io.chosen := lockIdx }
-    for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
-      in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
-  } else {
-    for ((in, g) <- io.in zip grant)
-      in.ready := g && io.out.ready
-  }
-}
-
-class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
-    extends LockingArbiterLike[T](gen, n, count, needsLock) {
-  lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
-  lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
-  lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
-
-  override def grant: Seq[Bool] = {
-    val ctrl = ArbiterCtrl((0 until n).map(i => validMask(i)) ++ io.in.map(_.valid))
-    (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
-  }
-
-  override lazy val choice = Wire(init=UInt(n-1))
-  for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
-  for (i <- n-1 to 1 by -1)
-    when (validMask(i)) { choice := UInt(i) }
-}
-
-class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
-    extends LockingArbiterLike[T](gen, n, count, needsLock) {
-  def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
-
-  override lazy val choice = Wire(init=UInt(n-1))
-  for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
-}
-
-/** Hardware module that is used to sequence n producers into 1 consumer.
-  Producers are chosen in round robin order.
-
-  Example usage:
-    val arb = new RRArbiter(2, UInt())
-    arb.io.in(0) <> producer0.io.out
-    arb.io.in(1) <> producer1.io.out
-    consumer.io.in <> arb.io.out
-  */
-class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
-
-/** Hardware module that is used to sequence n producers into 1 consumer.
- Priority is given to lower producer
-
- Example usage:
-   val arb = Module(new Arbiter(2, UInt()))
-   arb.io.in(0) <> producer0.io.out
-   arb.io.in(1) <> producer1.io.out
-   consumer.io.in <> arb.io.out
- */
-class Arbiter[T <: Data](gen: T, n: Int) extends Module {
-  val io = new ArbiterIO(gen, n)
-
-  io.chosen := UInt(n-1)
-  io.out.bits := io.in(n-1).bits
-  for (i <- n-2 to 0 by -1) {
-    when (io.in(i).valid) {
-      io.chosen := UInt(i)
-      io.out.bits := io.in(i).bits
-    }
-  }
-
-  val grant = ArbiterCtrl(io.in.map(_.valid))
-  for ((in, g) <- io.in zip grant)
-    in.ready := g && io.out.ready
-  io.out.valid := !grant.last || io.in.last.valid
-}
diff --git a/src/main/scala/Chisel/util/Bitwise.scala b/src/main/scala/Chisel/util/Bitwise.scala
deleted file mode 100644
index 239a295e..00000000
--- a/src/main/scala/Chisel/util/Bitwise.scala
+++ /dev/null
@@ -1,71 +0,0 @@
-// See LICENSE for license details.
-
-/** Miscellaneous circuit generators operating on bits.
-  */
-
-package Chisel
-
-object FillInterleaved
-{
-  def apply(n: Int, in: UInt): UInt = apply(n, in.toBools)
-  def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits
-}
-
-/** Returns the number of bits set (i.e value is 1) in the input signal.
-  */
-object PopCount
-{
-  def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq)
-  def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_)))
-}
-
-/** Fill fans out a UInt to multiple copies */
-object Fill {
-  /** Fan out x n times */
-  def apply(n: Int, x: UInt): UInt = {
-    n match {
-      case 0 => UInt(width=0)
-      case 1 => x
-      case y if n > 1 =>
-        val p2 = Array.ofDim[UInt](log2Up(n + 1))
-        p2(0) = x
-        for (i <- 1 until p2.length)
-          p2(i) = Cat(p2(i-1), p2(i-1))
-        Cat((0 until log2Up(y + 1)).filter(i => (y & (1 << i)) != 0).map(p2(_)))
-      case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.")
-    }
-  }
-  /** Fan out x n times */
-  def apply(n: Int, x: Bool): UInt =
-    if (n > 1) {
-      UInt(0,n) - x
-    } else {
-      apply(n, x: UInt)
-    }
-}
-
-/** Litte/big bit endian convertion: reverse the order of the bits in a UInt.
-*/
-object Reverse
-{
-  private def doit(in: UInt, length: Int): UInt = {
-    if (length == 1) {
-      in
-    } else if (isPow2(length) && length >= 8 && length <= 64) {
-      // This esoterica improves simulation performance
-      var res = in
-      var shift = length >> 1
-      var mask = UInt((BigInt(1) << length) - 1, length)
-      do {
-        mask = mask ^ (mask(length-shift-1,0) << shift)
-        res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask)
-        shift = shift >> 1
-      } while (shift > 0)
-      res
-    } else {
-      val half = (1 << log2Up(length))/2
-      Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half))
-    }
-  }
-  def apply(in: UInt): UInt = doit(in, in.getWidth)
-}
diff --git a/src/main/scala/Chisel/util/Cat.scala b/src/main/scala/Chisel/util/Cat.scala
deleted file mode 100644
index dd706e62..00000000
--- a/src/main/scala/Chisel/util/Cat.scala
+++ /dev/null
@@ -1,18 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-object Cat {
-  /** Combine data elements together
-    * @param a Data to combine with
-    * @param r any number of other Data elements to be combined in order
-    * @return A UInt which is all of the bits combined together
-    */
-  def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList)
-
-  /** Combine data elements together
-    * @param r any number of other Data elements to be combined in order
-    * @return A UInt which is all of the bits combined together
-    */
-  def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse)
-}
diff --git a/src/main/scala/Chisel/util/CircuitMath.scala b/src/main/scala/Chisel/util/CircuitMath.scala
deleted file mode 100644
index 06cab903..00000000
--- a/src/main/scala/Chisel/util/CircuitMath.scala
+++ /dev/null
@@ -1,26 +0,0 @@
-// See LICENSE for license details.
-
-/** Circuit-land math operations.
-  */
-
-package Chisel
-
-/** Compute Log2 with truncation of a UInt in hardware using a Mux Tree
-  * An alternative interpretation is it computes the minimum number of bits needed to represent x
-  * @example
-  * {{{ data_out := Log2(data_in) }}}
-  * @note Truncation is used so Log2(UInt(12412)) = 13*/
-object Log2 {
-  /** Compute the Log2 on the least significant n bits of x */
-  def apply(x: Bits, width: Int): UInt = {
-    if (width < 2) {
-      UInt(0)
-    } else if (width == 2) {
-      x(1)
-    } else {
-      Mux(x(width-1), UInt(width-1), apply(x, width-1))
-    }
-  }
-
-  def apply(x: Bits): UInt = apply(x, x.getWidth)
-}
diff --git a/src/main/scala/Chisel/util/Conditional.scala b/src/main/scala/Chisel/util/Conditional.scala
deleted file mode 100644
index 9cab25ef..00000000
--- a/src/main/scala/Chisel/util/Conditional.scala
+++ /dev/null
@@ -1,69 +0,0 @@
-// See LICENSE for license details.
-
-/** Conditional blocks.
-  */
-
-package Chisel
-
-import scala.language.reflectiveCalls
-import scala.language.experimental.macros
-import scala.reflect.runtime.universe._
-import scala.reflect.macros.blackbox._
-
-/** This is identical to [[Chisel.when when]] with the condition inverted */
-object unless {  // scalastyle:ignore object.name
-  def apply(c: Bool)(block: => Unit) {
-    when (!c) { block }
-  }
-}
-
-class SwitchContext[T <: Bits](cond: T) {
-  def is(v: Iterable[T])(block: => Unit) {
-    if (!v.isEmpty) when (v.map(_.asUInt === cond.asUInt).reduce(_||_)) { block }
-  }
-  def is(v: T)(block: => Unit) { is(Seq(v))(block) }
-  def is(v: T, vr: T*)(block: => Unit) { is(v :: vr.toList)(block) }
-}
-
-/** An object for separate cases in [[Chisel.switch switch]]
-  * It is equivalent to a [[Chisel.when$ when]] block comparing to the condition
-  * Use outside of a switch statement is illegal */
-object is {   // scalastyle:ignore object.name
-  // Begin deprecation of non-type-parameterized is statements.
-  def apply(v: Iterable[Bits])(block: => Unit) {
-    require(false, "The 'is' keyword may not be used outside of a switch.")
-  }
-
-  def apply(v: Bits)(block: => Unit) {
-    require(false, "The 'is' keyword may not be used outside of a switch.")
-  }
-
-  def apply(v: Bits, vr: Bits*)(block: => Unit) {
-    require(false, "The 'is' keyword may not be used outside of a switch.")
-  }
-}
-
-/** Conditional logic to form a switch block
-  * @example
-  * {{{ ... // default values here
-  * switch ( myState ) {
-  *   is( state1 ) {
-  *     ... // some logic here
-  *   }
-  *   is( state2 ) {
-  *     ... // some logic here
-  *   }
-  * } }}}*/
-object switch {  // scalastyle:ignore object.name
-  def apply[T <: Bits](cond: T)(x: => Unit): Unit = macro impl
-  def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
-    val sc = c.universe.internal.reificationSupport.freshTermName("sc")
-    def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match {
-      case q"Chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
-      case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
-    }
-    val q"..$body" = x
-    val ises = body.flatMap(extractIsStatement(_))
-    q"""{ val $sc = new SwitchContext($cond); ..$ises }"""
-  }
-}
diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/Chisel/util/Counter.scala
deleted file mode 100644
index 872e830a..00000000
--- a/src/main/scala/Chisel/util/Counter.scala
+++ /dev/null
@@ -1,44 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-/** A counter module
-  * @param n number of counts before the counter resets (or one more than the
-  * maximum output value of the counter), need not be a power of two
-  */
-class Counter(val n: Int) {
-  require(n >= 0)
-  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
-  /** Increment the counter, returning whether the counter currently is at the
-    * maximum and will wrap. The incremented value is registered and will be
-    * visible on the next cycle.
-    */
-  def inc(): Bool = {
-    if (n > 1) {
-      val wrap = value === UInt(n-1)
-      value := value + UInt(1)
-      if (!isPow2(n)) {
-        when (wrap) { value := UInt(0) }
-      }
-      wrap
-    } else {
-      Bool(true)
-    }
-  }
-}
-
-/** Counter Object
-  * Example Usage:
-  * {{{ val countOn = Bool(true) // increment counter every clock cycle
-  * val myCounter = Counter(countOn, n)
-  * when ( myCounter.value === UInt(3) ) { ... } }}}*/
-object Counter
-{
-  def apply(n: Int): Counter = new Counter(n)
-  def apply(cond: Bool, n: Int): (UInt, Bool) = {
-    val c = new Counter(n)
-    var wrap: Bool = null
-    when (cond) { wrap = c.inc() }
-    (c.value, cond && wrap)
-  }
-}
diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala
deleted file mode 100644
index 8e045855..00000000
--- a/src/main/scala/Chisel/util/Decoupled.scala
+++ /dev/null
@@ -1,183 +0,0 @@
-// See LICENSE for license details.
-
-/** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them.
-  */
-
-package Chisel
-
-/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
-class DecoupledIO[+T <: Data](gen: T) extends Bundle
-{
-  val ready = Bool(INPUT)
-  val valid = Bool(OUTPUT)
-  val bits  = gen.cloneType.asOutput
-  def fire(dummy: Int = 0): Bool = ready && valid
-  override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type]
-}
-
-/** Adds a ready-valid handshaking protocol to any interface.
-  * The standard used is that the consumer uses the flipped interface.
-  */
-object Decoupled {
-  def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
-}
-
-/** An I/O bundle for enqueuing data with valid/ready handshaking
-  * Initialization must be handled, if necessary, by the parent circuit
-  */
-class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen)
-{
-  /** push dat onto the output bits of this interface to let the consumer know it has happened.
-    * @param dat the values to assign to bits.
-    * @return    dat.
-    */
-  def enq(dat: T): T = { valid := Bool(true); bits := dat; dat }
-
-  /** Initialize this Bundle.  Valid is set to false, and all bits are set to zero.
-    * NOTE: This method of initialization is still being discussed and could change in the
-    * future.
-    */
-  def init(): Unit = {
-    valid := Bool(false)
-    for (io <- bits.flatten)
-      io := UInt(0)
-  }
-  override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; }
-}
-
-/** An I/O bundle for dequeuing data with valid/ready handshaking.
-  * Initialization must be handled, if necessary, by the parent circuit
-  */
-class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped
-{
-  /** Assert ready on this port and return the associated data bits.
-    * This is typically used when valid has been asserted by the producer side.
-    * @param b ignored
-    * @return the data for this device,
-    */
-  def deq(b: Boolean = false): T = { ready := Bool(true); bits }
-
-  /** Initialize this Bundle.
-    * NOTE: This method of initialization is still being discussed and could change in the
-    * future.
-    */
-  def init(): Unit = {
-    ready := Bool(false)
-  }
-  override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
-}
-
-/** An I/O bundle for dequeuing data with valid/ready handshaking */
-class DecoupledIOC[+T <: Data](gen: T) extends Bundle
-{
-  val ready = Bool(INPUT)
-  val valid = Bool(OUTPUT)
-  val bits  = gen.cloneType.asOutput
-}
-
-/** An I/O Bundle for Queues
-  * @param gen The type of data to queue
-  * @param entries The max number of entries in the queue */
-class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
-{
-  /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */
-  val enq   = Decoupled(gen.cloneType).flip()
-  /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
-  val deq   = Decoupled(gen.cloneType)
-  /** The current amount of data in the queue */
-  val count = UInt(OUTPUT, log2Up(entries + 1))
-}
-
-/** A hardware module implementing a Queue
-  * @param gen The type of data to queue
-  * @param entries The max number of entries in the queue
-  * @param pipe True if a single entry queue can run at full throughput (like a pipeline). The ''ready'' signals are
-  * combinationally coupled.
-  * @param flow True if the inputs can be consumed on the same cycle (the inputs "flow" through the queue immediately).
-  * The ''valid'' signals are coupled.
-  *
-  * Example usage:
-  *    {{{ val q = new Queue(UInt(), 16)
-  *    q.io.enq <> producer.io.out
-  *    consumer.io.in <> q.io.deq }}}
-  */
-class Queue[T <: Data](gen: T, val entries: Int,
-                       pipe: Boolean = false,
-                       flow: Boolean = false,
-                       override_reset: Option[Bool] = None)
-extends Module(override_reset=override_reset) {
-  def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) =
-    this(gen, entries, pipe, flow, Some(_reset))
-  
-  val io = new QueueIO(gen, entries)
-
-  val ram = Mem(entries, gen)
-  val enq_ptr = Counter(entries)
-  val deq_ptr = Counter(entries)
-  val maybe_full = Reg(init=Bool(false))
-
-  val ptr_match = enq_ptr.value === deq_ptr.value
-  val empty = ptr_match && !maybe_full
-  val full = ptr_match && maybe_full
-  val do_enq = Wire(init=io.enq.fire())
-  val do_deq = Wire(init=io.deq.fire())
-
-  when (do_enq) {
-    ram(enq_ptr.value) := io.enq.bits
-    enq_ptr.inc()
-  }
-  when (do_deq) {
-    deq_ptr.inc()
-  }
-  when (do_enq != do_deq) {
-    maybe_full := do_enq
-  }
-
-  io.deq.valid := !empty
-  io.enq.ready := !full
-  io.deq.bits := ram(deq_ptr.value)
-
-  if (flow) {
-    when (io.enq.valid) { io.deq.valid := Bool(true) }
-    when (empty) {
-      io.deq.bits := io.enq.bits
-      do_deq := Bool(false)
-      when (io.deq.ready) { do_enq := Bool(false) }
-    }
-  }
-
-  if (pipe) {
-    when (io.deq.ready) { io.enq.ready := Bool(true) }
-  }
-
-  val ptr_diff = enq_ptr.value - deq_ptr.value
-  if (isPow2(entries)) {
-    io.count := Cat(maybe_full && ptr_match, ptr_diff)
-  } else {
-    io.count := Mux(ptr_match,
-                    Mux(maybe_full,
-                      UInt(entries), UInt(0)),
-                    Mux(deq_ptr.value > enq_ptr.value,
-                      UInt(entries) + ptr_diff, ptr_diff))
-  }
-}
-
-/** Generic hardware queue. Required parameter entries controls
-  the depth of the queues. The width of the queue is determined
-  from the inputs.
-
-  Example usage:
-     {{{ val q = Queue(Decoupled(UInt()), 16)
-     q.io.enq <> producer.io.out
-     consumer.io.in <> q.io.deq }}}
-  */
-object Queue
-{
-  def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T]  = {
-    val q = Module(new Queue(enq.bits.cloneType, entries, pipe))
-    q.io.enq.valid := enq.valid // not using <> so that override is allowed
-    q.io.enq.bits := enq.bits
-    enq.ready := q.io.enq.ready
-    TransitName(q.io.deq, q)
-  }
-}
diff --git a/src/main/scala/Chisel/util/Enum.scala b/src/main/scala/Chisel/util/Enum.scala
deleted file mode 100644
index 20057197..00000000
--- a/src/main/scala/Chisel/util/Enum.scala
+++ /dev/null
@@ -1,21 +0,0 @@
-// See LICENSE for license details.
-
-/** Enum generators, allowing circuit constants to have more meaningful names.
-  */
-
-package Chisel
-
-object Enum {
-  /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
-  private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] =
-    (0 until n).map(x => nodeType.fromInt(x, log2Up(n)))
-
-  /** create n enum values of given type */
-  def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList
-
-  /** create enum values of given type and names */
-  def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap
-
-  /** create enum values of given type and names */
-  def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap
-}
diff --git a/src/main/scala/Chisel/util/LFSR.scala b/src/main/scala/Chisel/util/LFSR.scala
deleted file mode 100644
index 839b1d1f..00000000
--- a/src/main/scala/Chisel/util/LFSR.scala
+++ /dev/null
@@ -1,22 +0,0 @@
-// See LICENSE for license details.
-
-/** LFSRs in all shapes and sizes.
-  */
-
-package Chisel
-
-// scalastyle:off magic.number
-/** linear feedback shift register
-  */
-object LFSR16
-{
-  def apply(increment: Bool = Bool(true)): UInt =
-  {
-    val width = 16
-    val lfsr = Reg(init=UInt(1, width))
-    when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
-    lfsr
-  }
-}
-// scalastyle:on magic.number
-
diff --git a/src/main/scala/Chisel/util/Lookup.scala b/src/main/scala/Chisel/util/Lookup.scala
deleted file mode 100644
index 54922fc4..00000000
--- a/src/main/scala/Chisel/util/Lookup.scala
+++ /dev/null
@@ -1,17 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-object ListLookup {
-  def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = {
-    val map = mapping.map(m => (m._1 === addr, m._2))
-    default.zipWithIndex map { case (d, i) =>
-      map.foldRight(d)((m, n) => Mux(m._1, m._2(i), n))
-    }
-  }
-}
-
-object Lookup {
-  def apply[T <: Bits](addr: UInt, default: T, mapping: Seq[(BitPat, T)]): T =
-    ListLookup(addr, List(default), mapping.map(m => (m._1, List(m._2))).toArray).head
-}
diff --git a/src/main/scala/Chisel/util/Math.scala b/src/main/scala/Chisel/util/Math.scala
deleted file mode 100644
index 5f8212d8..00000000
--- a/src/main/scala/Chisel/util/Math.scala
+++ /dev/null
@@ -1,42 +0,0 @@
-// See LICENSE for license details.
-
-/** Scala-land math helper functions, like logs.
-  */
-
-package Chisel
-
-/** Compute the log2 rounded up with min value of 1 */
-object log2Up {
-  def apply(in: BigInt): Int = {
-    require(in >= 0)
-    1 max (in-1).bitLength
-  }
-  def apply(in: Int): Int = apply(BigInt(in))
-}
-
-/** Compute the log2 rounded up */
-object log2Ceil {
-  def apply(in: BigInt): Int = {
-    require(in > 0)
-    (in-1).bitLength
-  }
-  def apply(in: Int): Int = apply(BigInt(in))
-}
-
-/** Compute the log2 rounded down with min value of 1 */
-object log2Down {
-  def apply(in: BigInt): Int = log2Up(in) - (if (isPow2(in)) 0 else 1)
-  def apply(in: Int): Int = apply(BigInt(in))
-}
-
-/** Compute the log2 rounded down */
-object log2Floor {
-  def apply(in: BigInt): Int = log2Ceil(in) - (if (isPow2(in)) 0 else 1)
-  def apply(in: Int): Int = apply(BigInt(in))
-}
-
-/** Check if an Integer is a power of 2 */
-object isPow2 {
-  def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0)
-  def apply(in: Int): Boolean = apply(BigInt(in))
-}
diff --git a/src/main/scala/Chisel/util/Mux.scala b/src/main/scala/Chisel/util/Mux.scala
deleted file mode 100644
index 9d92321a..00000000
--- a/src/main/scala/Chisel/util/Mux.scala
+++ /dev/null
@@ -1,61 +0,0 @@
-// See LICENSE for license details.
-
-/** Mux circuit generators.
-  */
-
-package Chisel
-
-/** Builds a Mux tree out of the input signal vector using a one hot encoded
-  select signal. Returns the output of the Mux tree.
-  */
-object Mux1H
-{
-  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T =
-    apply(sel zip in)
-  def apply[T <: Data](in: Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in)
-  def apply[T <: Data](sel: UInt, in: Seq[T]): T =
-    apply((0 until in.size).map(sel(_)), in)
-  def apply(sel: UInt, in: UInt): Bool = (sel & in).orR
-}
-
-/** Builds a Mux tree under the assumption that multiple select signals
-  can be enabled. Priority is given to the first select signal.
-
-  Returns the output of the Mux tree.
-  */
-object PriorityMux
-{
-  def apply[T <: Data](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in)
-  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in)
-  def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in)
-}
-
-/** MuxLookup creates a cascade of n Muxs to search for a key value */
-object MuxLookup {
-  /** @param key a key to search for
-    * @param default a default value if nothing is found
-    * @param mapping a sequence to search of keys and values
-    * @return the value found or the default if not
-    */
-  def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = {
-    var res = default
-    for ((k, v) <- mapping.reverse)
-      res = Mux(k === key, v, res)
-    res
-  }
-
-}
-
-/** MuxCase returns the first value that is enabled in a map of values */
-object MuxCase {
-  /** @param default the default value if none are enabled
-    * @param mapping a set of data values with associated enables
-    * @return the first value in mapping that is enabled */
-  def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = {
-    var res = default
-    for ((t, v) <- mapping.reverse){
-      res = Mux(t, v, res)
-    }
-    res
-  }
-}
diff --git a/src/main/scala/Chisel/util/OneHot.scala b/src/main/scala/Chisel/util/OneHot.scala
deleted file mode 100644
index 73f27403..00000000
--- a/src/main/scala/Chisel/util/OneHot.scala
+++ /dev/null
@@ -1,62 +0,0 @@
-// See LICENSE for license details.
-
-/** Circuit generators for working with one-hot representations.
-  */
-
-package Chisel
-
-/** Converts from One Hot Encoding to a UInt indicating which bit is active
-  * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/
-object OHToUInt {
-  def apply(in: Seq[Bool]): UInt = apply(Vec(in))
-  def apply(in: Vec[Bool]): UInt = apply(in.toBits, in.size)
-  def apply(in: Bits): UInt = apply(in, in.getWidth)
-
-  def apply(in: Bits, width: Int): UInt = {
-    if (width <= 2) {
-      Log2(in, width)
-    } else {
-      val mid = 1 << (log2Up(width)-1)
-      val hi = in(width-1, mid)
-      val lo = in(mid-1, 0)
-      Cat(hi.orR, apply(hi | lo, mid))
-    }
-  }
-}
-
-/** @return the bit position of the trailing 1 in the input vector
-  * with the assumption that multiple bits of the input bit vector can be set
-  * @example {{{ data_out := PriorityEncoder(data_in) }}}
-  */
-object PriorityEncoder {
-  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
-  def apply(in: Bits): UInt = apply(in.toBools)
-}
-
-/** Returns the one hot encoding of the input UInt.
-  */
-object UIntToOH
-{
-  def apply(in: UInt, width: Int = -1): UInt =
-    if (width == -1) {
-      UInt(1) << in
-    } else {
-      (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
-    }
-}
-
-/** Returns a bit vector in which only the least-significant 1 bit in
-  the input vector, if any, is set.
-  */
-object PriorityEncoderOH
-{
-  private def encode(in: Seq[Bool]): UInt = {
-    val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size))
-    PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size))
-  }
-  def apply(in: Seq[Bool]): Seq[Bool] = {
-    val enc = encode(in)
-    Seq.tabulate(in.size)(enc(_))
-  }
-  def apply(in: Bits): UInt = encode((0 until in.getWidth).map(i => in(i)))
-}
diff --git a/src/main/scala/Chisel/util/Reg.scala b/src/main/scala/Chisel/util/Reg.scala
deleted file mode 100644
index 6584a4bf..00000000
--- a/src/main/scala/Chisel/util/Reg.scala
+++ /dev/null
@@ -1,55 +0,0 @@
-// See LICENSE for license details.
-
-/** Variations and helpers for registers.
-  */
-
-package Chisel
-
-object RegNext {
-
-  def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T])
-
-  def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init)
-
-}
-
-object RegInit {
-
-  def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init)
-
-}
-
-/** A register with an Enable signal */
-object RegEnable
-{
-  def apply[T <: Data](updateData: T, enable: Bool): T = {
-    val r = Reg(updateData)
-    when (enable) { r := updateData }
-    r
-  }
-  def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
-    val r = RegInit(resetData)
-    when (enable) { r := updateData }
-    r
-  }
-}
-
-/** Returns the n-cycle delayed version of the input signal.
-  */
-object ShiftRegister
-{
-  /** @param in input to delay
-    * @param n number of cycles to delay
-    * @param en enable the shift */
-  def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T =
-  {
-    // The order of tests reflects the expected use cases.
-    if (n == 1) {
-      RegEnable(in, en)
-    } else if (n != 0) {
-      RegNext(apply(in, n-1, en))
-    } else {
-      in
-    }
-  }
-}
diff --git a/src/main/scala/Chisel/util/TransitName.scala b/src/main/scala/Chisel/util/TransitName.scala
deleted file mode 100644
index ec5a11cc..00000000
--- a/src/main/scala/Chisel/util/TransitName.scala
+++ /dev/null
@@ -1,21 +0,0 @@
-package Chisel
-
-import internal.HasId
-
-object TransitName {
-  // The purpose of this is to allow a library to 'move' a name call to a more
-  // appropriate place.
-  // For example, a library factory function may create a module and return
-  // the io. The only user-exposed field is that given IO, which can't use
-  // any name supplied by the user. This can add a hook so that the supplied
-  // name then names the Module.
-  // See Queue companion object for working example
-  def apply[T<:HasId](from: T, to: HasId): T = {
-    from.addPostnameHook((given_name: String) => {to.suggestName(given_name)})
-    from
-  }
-  def withSuffix[T<:HasId](suffix: String)(from: T, to: HasId): T = {
-    from.addPostnameHook((given_name: String) => {to.suggestName(given_name+suffix)})
-    from
-  }
-}
diff --git a/src/main/scala/Chisel/util/Valid.scala b/src/main/scala/Chisel/util/Valid.scala
deleted file mode 100644
index 9e2202bb..00000000
--- a/src/main/scala/Chisel/util/Valid.scala
+++ /dev/null
@@ -1,59 +0,0 @@
-// See LICENSE for license details.
-
-/** Wrappers for valid interfaces and associated circuit generators using them.
-  */
-
-package Chisel
-
-/** An I/O Bundle containing data and a signal determining if it is valid */
-class ValidIO[+T <: Data](gen2: T) extends Bundle
-{
-  val valid = Bool(OUTPUT)
-  val bits = gen2.cloneType.asOutput
-  def fire(dummy: Int = 0): Bool = valid
-  override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type]
-}
-
-/** Adds a valid protocol to any interface. The standard used is
-  that the consumer uses the flipped interface.
-*/
-object Valid {
-  def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen)
-}
-
-/** A hardware module that delays data coming down the pipeline
-  by the number of cycles set by the latency parameter. Functionality
-  is similar to ShiftRegister but this exposes a Pipe interface.
-
-  Example usage:
-    val pipe = new Pipe(UInt())
-    pipe.io.enq <> produce.io.out
-    consumer.io.in <> pipe.io.deq
-  */
-object Pipe
-{
-  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = {
-    if (latency == 0) {
-      val out = Wire(Valid(enqBits))
-      out.valid <> enqValid
-      out.bits <> enqBits
-      out
-    } else {
-      val v = Reg(Bool(), next=enqValid, init=Bool(false))
-      val b = RegEnable(enqBits, enqValid)
-      apply(v, b, latency-1)
-    }
-  }
-  def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1)
-  def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency)
-}
-
-class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module
-{
-  val io = new Bundle {
-    val enq = Valid(gen).flip
-    val deq = Valid(gen)
-  }
-
-  io.deq <> Pipe(io.enq, latency)
-}
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
new file mode 100644
index 00000000..02204684
--- /dev/null
+++ b/src/main/scala/chisel3/Driver.scala
@@ -0,0 +1,132 @@
+// See LICENSE for license details.
+
+package Chisel
+
+import scala.sys.process._
+import java.io._
+
+import internal._
+import internal.firrtl._
+
+trait BackendCompilationUtilities {
+  /** Create a temporary directory with the prefix name. Exists here because it doesn't in Java 6.
+    */
+  def createTempDirectory(prefix: String): File = {
+    val temp = File.createTempFile(prefix, "")
+    if (!temp.delete()) {
+      throw new IOException(s"Unable to delete temp file '$temp'")
+    }
+    if (!temp.mkdir()) {
+      throw new IOException(s"Unable to create temp directory '$temp'")
+    }
+    temp
+  }
+
+  def makeHarness(template: String => String, post: String)(f: File): File = {
+    val prefix = f.toString.split("/").last
+    val vf = new File(f.toString + post)
+    val w = new FileWriter(vf)
+    w.write(template(prefix))
+    w.close()
+    vf
+  }
+
+  def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder = {
+    Process(
+      Seq("firrtl",
+          "-i", s"$prefix.fir",
+          "-o", s"$prefix.v",
+          "-X", "verilog"),
+      dir)
+  }
+
+  /** Generates a Verilator invocation to convert Verilog sources to C++
+    * simulation sources.
+    *
+    * The Verilator prefix will be V$dutFile, and running this will generate
+    * C++ sources and headers as well as a makefile to compile them.
+    *
+    * @param dutFile name of the DUT .v without the .v extension
+    * @param name of the top-level module in the design
+    * @param dir output directory
+    * @param vSources list of additional Verilog sources to compile
+    * @param cppHarness C++ testharness to compile/link against
+    */
+  def verilogToCpp(
+      dutFile: String,
+      topModule: String,
+      dir: File,
+      vSources: Seq[File],
+      cppHarness: File
+                  ): ProcessBuilder = {
+    val command = Seq("verilator",
+      "--cc", s"$dutFile.v") ++
+      vSources.map(file => Seq("-v", file.toString)).flatten ++
+      Seq("--assert",
+        "-Wno-fatal",
+        "-Wno-WIDTH",
+        "-Wno-STMTDLY",
+        "--trace",
+        "-O2",
+        "--top-module", topModule,
+        "+define+TOP_TYPE=V" + dutFile,
+        s"+define+PRINTF_COND=!$topModule.reset",
+        "-CFLAGS",
+        s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
+        "-Mdir", dir.toString,
+        "--exe", cppHarness.toString)
+    System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex
+    command
+  }
+
+  def cppToExe(prefix: String, dir: File): ProcessBuilder =
+    Seq("make", "-C", dir.toString, "-j", "-f", s"V${prefix}.mk", s"V${prefix}")
+
+  def executeExpectingFailure(
+      prefix: String,
+      dir: File,
+      assertionMsg: String = "Assertion failed"): Boolean = {
+    var triggered = false
+    val e = Process(s"./V${prefix}", dir) !
+      ProcessLogger(line => {
+        triggered = triggered || line.contains(assertionMsg)
+        System.out.println(line) // scalastyle:ignore regex
+      })
+    triggered
+  }
+
+  def executeExpectingSuccess(prefix: String, dir: File): Boolean = {
+    !executeExpectingFailure(prefix, dir)
+  }
+}
+
+object Driver extends BackendCompilationUtilities {
+
+  /** Elaborates the Module specified in the gen function into a Circuit
+    *
+    *  @param gen a function that creates a Module hierarchy
+    *  @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR)
+    */
+  def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen()))
+
+  def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen))
+
+  def dumpFirrtl(ir: Circuit, optName: Option[File]): File = {
+    val f = optName.getOrElse(new File(ir.name + ".fir"))
+    val w = new FileWriter(f)
+    w.write(Emitter.emit(ir))
+    w.close()
+    f
+  }
+
+  private var target_dir: Option[String] = None
+  def parseArgs(args: Array[String]): Unit = {
+    for (i <- 0 until args.size) {
+      if (args(i) == "--targetDir") {
+        target_dir = Some(args(i + 1))
+      }
+    }
+  }
+
+  def targetDir(): String = { target_dir getOrElse new File(".").getCanonicalPath }
+}
diff --git a/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
new file mode 100644
index 00000000..575ae138
--- /dev/null
+++ b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
@@ -0,0 +1,10 @@
+// See LICENSE for license details.
+
+package Chisel
+
+@deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0")
+trait FileSystemUtilities {
+  def createOutputFile(name: String): java.io.FileWriter  = {
+    new java.io.FileWriter(Driver.targetDir + "/" + name)
+  }
+}
diff --git a/src/main/scala/chisel3/compatibility/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala
new file mode 100644
index 00000000..a72debc3
--- /dev/null
+++ b/src/main/scala/chisel3/compatibility/Main.scala
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+
+package Chisel
+
+import java.io.File
+
+@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
+  def apply[T <: Module](args: Array[String], gen: () => T): Unit =
+    Predef.assert(false, "No more chiselMain in Chisel3")
+
+  def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
+    val circuit = Driver.elaborate(gen)
+    Driver.parseArgs(args)
+    val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+    Driver.dumpFirrtl(circuit, Option(output_file))
+  }
+}
diff --git a/src/main/scala/chisel3/compatibility/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala
new file mode 100644
index 00000000..702884aa
--- /dev/null
+++ b/src/main/scala/chisel3/compatibility/throwException.scala
@@ -0,0 +1,12 @@
+// See LICENSE for license details.
+
+package Chisel
+
+@deprecated("throwException doesn't exist in Chisel3", "3.0.0")
+@throws(classOf[Exception])
+object throwException {
+  def apply(s: String, t: Throwable = null) = {
+    val xcpt = new Exception(s, t)
+    throw xcpt
+  }
+}
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
new file mode 100644
index 00000000..7ca3268a
--- /dev/null
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -0,0 +1,112 @@
+// See LICENSE for license details.
+
+package Chisel.internal.firrtl
+import Chisel._
+import Chisel.internal.sourceinfo.{NoSourceInfo, SourceLine}
+
+private[Chisel] object Emitter {
+  def emit(circuit: Circuit): String = new Emitter(circuit).toString
+}
+
+private class Emitter(circuit: Circuit) {
+  override def toString: String = res.toString
+
+  private def emitPort(e: Port): String =
+    s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}"
+  private def emit(e: Command, ctx: Component): String = {
+    val firrtlLine = e match {
+      case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
+      case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
+      case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}"
+      case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
+      case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]"
+      case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]"
+      case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
+      case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
+      case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
+      case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})"
+      case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})"""
+      case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
+      case e: DefInstance => {
+        val modName = moduleMap.get(e.id.name).get
+        s"inst ${e.name} of $modName"
+      }
+
+      case w: WhenBegin =>
+        indent()
+        s"when ${w.pred.fullName(ctx)} :"
+      case _: WhenEnd =>
+        unindent()
+        s"skip"
+    }
+    e.sourceInfo match {
+      case SourceLine(filename, line, col) => s"${firrtlLine} @[${filename} ${line}:${col}] "
+      case _: NoSourceInfo => firrtlLine
+    }
+  }
+
+  // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.
+  private val defnMap = collection.mutable.HashMap[String, String]()
+  // Map of Component name to FIRRTL id.
+  private val moduleMap = collection.mutable.HashMap[String, String]()
+
+  /** Generates the FIRRTL module definition with a specified name.
+    */
+  private def moduleDefn(m: Component, name: String): String = {
+    val body = new StringBuilder
+    m.id match {
+      case _: BlackBox => body ++= newline + s"extmodule $name : "
+      case _: Module => body ++= newline + s"module $name : "
+    }
+    withIndent {
+      for (p <- m.ports)
+        body ++= newline + emitPort(p)
+      body ++= newline
+
+      m.id match {
+        case _: BlackBox =>
+          // TODO: BlackBoxes should be empty, but funkiness in Module() means
+          // it's not for now. Eventually, this should assert out.
+        case _: Module => for (cmd <- m.commands) {
+          body ++= newline + emit(cmd, m)
+        }
+      }
+      body ++= newline
+    }
+    body.toString()
+  }
+
+  /** Returns the FIRRTL declaration and body of a module, or nothing if it's a
+    * duplicate of something already emitted (on the basis of simple string
+    * matching).
+    */
+  private def emit(m: Component): String = {
+    // Generate the body.
+    val moduleName = m.id.getClass.getName.split('.').last
+    val defn = moduleDefn(m, moduleName)
+
+    defnMap get defn match {
+      case Some(deduplicatedName) =>
+        moduleMap(m.name) = deduplicatedName
+        ""
+      case None =>
+        require(!(moduleMap contains m.name),
+            "emitting module with same name but different contents")
+
+        moduleMap(m.name) = m.name
+        defnMap(defn) = m.name
+
+        moduleDefn(m, m.name)
+    }
+  }
+
+  private var indentLevel = 0
+  private def newline = "\n" + ("  " * indentLevel)
+  private def indent(): Unit = indentLevel += 1
+  private def unindent() { require(indentLevel > 0); indentLevel -= 1 }
+  private def withIndent(f: => Unit) { indent(); f; unindent() }
+
+  private val res = new StringBuilder(s"circuit ${circuit.name} : ")
+  withIndent { circuit.components.foreach(c => res ++= emit(c)) }
+  res ++= newline
+}
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
new file mode 100644
index 00000000..f05e8b5d
--- /dev/null
+++ b/src/main/scala/chisel3/package.scala
@@ -0,0 +1,31 @@
+package object Chisel {
+  import scala.language.experimental.macros
+  
+  import internal.firrtl.Width
+  import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+  
+  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
+    def U: UInt = UInt(x, Width())
+    def S: SInt = SInt(x, Width())
+  }
+  implicit class fromIntToLiteral(val x: Int) extends AnyVal {
+    def U: UInt = UInt(BigInt(x), Width())
+    def S: SInt = SInt(BigInt(x), Width())
+  }
+  implicit class fromStringToLiteral(val x: String) extends AnyVal {
+    def U: UInt = UInt(x)
+  }
+  implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
+    def B: Bool = Bool(x)
+  }
+  
+  implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
+    final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+    final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+    final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+  
+    def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x
+    def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
+    def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
+  }
+}
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
new file mode 100644
index 00000000..b8c1494a
--- /dev/null
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -0,0 +1,38 @@
+// See LICENSE for license details.
+
+package Chisel.testers
+import Chisel._
+
+import scala.language.experimental.macros
+
+import internal._
+import internal.Builder.pushCommand
+import internal.firrtl._
+import internal.sourceinfo.SourceInfo
+
+class BasicTester extends Module {
+  // The testbench has no IOs, rather it should communicate using printf, assert, and stop.
+  val io = new Bundle()
+
+  def popCount(n: Long): Int = n.toBinaryString.count(_=='1')
+
+  /** Ends the test reporting success.
+    *
+    * Does not fire when in reset (defined as the encapsulating Module's
+    * reset). If your definition of reset is not the encapsulating Module's
+    * reset, you will need to gate this externally.
+    */
+  def stop()(implicit sourceInfo: SourceInfo) {
+    // TODO: rewrite this using library-style SourceInfo passing.
+    when (!reset) {
+      pushCommand(Stop(sourceInfo, Node(clock), 0))
+    }
+  }
+
+  /** The finish method provides a hook that subclasses of BasicTester can use to
+    * alter a circuit after their constructor has been called.
+    * For example, a specialized tester subclassing BasicTester could override finish in order to
+    * add flow control logic for a decoupled io port of a device under test
+    */
+  def finish(): Unit = {}
+}
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
new file mode 100644
index 00000000..a56bb8b7
--- /dev/null
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -0,0 +1,68 @@
+// See LICENSE for license details.
+
+package Chisel.testers
+import Chisel._
+import scala.io.Source
+import scala.sys.process._
+import java.io._
+
+object TesterDriver extends BackendCompilationUtilities {
+  /** Copy the contents of a resource to a destination file.
+    */
+  def copyResourceToFile(name: String, file: File) {
+    val in = getClass().getResourceAsStream(name)
+    if (in == null) {
+      throw new FileNotFoundException(s"Resource '$name'")
+    }
+    val out = new FileOutputStream(file)
+    Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write)
+    out.close()
+  }
+
+  /** For use with modules that should successfully be elaborated by the
+    * frontend, and which can be turned into executables with assertions. */
+  def execute(t: () => BasicTester, additionalVResources: Seq[String] = Seq()): Boolean = {
+    // Invoke the chisel compiler to get the circuit's IR
+    val circuit = Driver.elaborate(finishWrapper(t))
+
+    // Set up a bunch of file handlers based on a random temp filename,
+    // plus the quirks of Verilator's naming conventions
+    val target = circuit.name
+
+    val path = createTempDirectory(target)
+    val fname = new File(path, target)
+
+    // For now, dump the IR out to a file
+    Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
+
+    // Copy CPP harness and other Verilog sources from resources into files
+    val cppHarness =  new File(path, "top.cpp")
+    copyResourceToFile("/top.cpp", cppHarness)
+    val additionalVFiles = additionalVResources.map((name: String) => {
+      val mangledResourceName = name.replace("/", "_")
+      val out = new File(path, mangledResourceName)
+      copyResourceToFile(name, out)
+      out
+    })
+
+    // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
+    if ((firrtlToVerilog(target, path) #&&
+        verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&&
+        cppToExe(target, path)).! == 0) {
+      executeExpectingSuccess(target, path)
+    } else {
+      false
+    }
+  }
+  /**
+    * Calls the finish method of an BasicTester or a class that extends it.
+    * The finish method is a hook for code that augments the circuit built in the constructor.
+    */
+  def finishWrapper(test: () => BasicTester): () => BasicTester = {
+    () => {
+      val tester = test()
+      tester.finish()
+      tester
+    }
+  }
+}
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
new file mode 100644
index 00000000..16ae9be5
--- /dev/null
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -0,0 +1,117 @@
+// See LICENSE for license details.
+
+/** Arbiters in all shapes and sizes.
+  */
+
+package Chisel
+
+/** An I/O bundle for the Arbiter */
+class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
+  val in  = Vec(n, Decoupled(gen)).flip
+  val out = Decoupled(gen)
+  val chosen = UInt(OUTPUT, log2Up(n))
+}
+
+/** Arbiter Control determining which producer has access */
+private object ArbiterCtrl
+{
+  def apply(request: Seq[Bool]): Seq[Bool] = request.length match {
+    case 0 => Seq()
+    case 1 => Seq(Bool(true))
+    case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
+  }
+}
+
+abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module {
+  def grant: Seq[Bool]
+  def choice: UInt
+  val io = new ArbiterIO(gen, n)
+
+  io.chosen := choice
+  io.out.valid := io.in(io.chosen).valid
+  io.out.bits := io.in(io.chosen).bits
+
+  if (count > 1) {
+    val lockCount = Counter(count)
+    val lockIdx = Reg(UInt())
+    val locked = lockCount.value =/= UInt(0)
+    val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
+
+    when (io.out.fire() && wantsLock) {
+      lockIdx := io.chosen
+      lockCount.inc()
+    }
+
+    when (locked) { io.chosen := lockIdx }
+    for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
+      in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
+  } else {
+    for ((in, g) <- io.in zip grant)
+      in.ready := g && io.out.ready
+  }
+}
+
+class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
+    extends LockingArbiterLike[T](gen, n, count, needsLock) {
+  lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
+  lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
+  lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
+
+  override def grant: Seq[Bool] = {
+    val ctrl = ArbiterCtrl((0 until n).map(i => validMask(i)) ++ io.in.map(_.valid))
+    (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
+  }
+
+  override lazy val choice = Wire(init=UInt(n-1))
+  for (i <- n-2 to 0 by -1)
+    when (io.in(i).valid) { choice := UInt(i) }
+  for (i <- n-1 to 1 by -1)
+    when (validMask(i)) { choice := UInt(i) }
+}
+
+class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
+    extends LockingArbiterLike[T](gen, n, count, needsLock) {
+  def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
+
+  override lazy val choice = Wire(init=UInt(n-1))
+  for (i <- n-2 to 0 by -1)
+    when (io.in(i).valid) { choice := UInt(i) }
+}
+
+/** Hardware module that is used to sequence n producers into 1 consumer.
+  Producers are chosen in round robin order.
+
+  Example usage:
+    val arb = new RRArbiter(2, UInt())
+    arb.io.in(0) <> producer0.io.out
+    arb.io.in(1) <> producer1.io.out
+    consumer.io.in <> arb.io.out
+  */
+class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
+
+/** Hardware module that is used to sequence n producers into 1 consumer.
+ Priority is given to lower producer
+
+ Example usage:
+   val arb = Module(new Arbiter(2, UInt()))
+   arb.io.in(0) <> producer0.io.out
+   arb.io.in(1) <> producer1.io.out
+   consumer.io.in <> arb.io.out
+ */
+class Arbiter[T <: Data](gen: T, n: Int) extends Module {
+  val io = new ArbiterIO(gen, n)
+
+  io.chosen := UInt(n-1)
+  io.out.bits := io.in(n-1).bits
+  for (i <- n-2 to 0 by -1) {
+    when (io.in(i).valid) {
+      io.chosen := UInt(i)
+      io.out.bits := io.in(i).bits
+    }
+  }
+
+  val grant = ArbiterCtrl(io.in.map(_.valid))
+  for ((in, g) <- io.in zip grant)
+    in.ready := g && io.out.ready
+  io.out.valid := !grant.last || io.in.last.valid
+}
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
new file mode 100644
index 00000000..96206f63
--- /dev/null
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -0,0 +1,88 @@
+// See LICENSE for license details.
+
+package Chisel
+
+import scala.language.experimental.macros
+
+import Chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+
+object BitPat {
+  /** Parses a bit pattern string into (bits, mask, width).
+    *
+    * @return bits the literal value, with don't cares being 0
+    * @return mask the mask bits, with don't cares being 0 and cares being 1
+    * @return width the number of bits in the literal, including values and
+    * don't cares.
+    */
+  private def parse(x: String): (BigInt, BigInt, Int) = {
+    // Notes:
+    // While Verilog Xs also handle octal and hex cases, there isn't a
+    // compelling argument and no one has asked for it.
+    // If ? parsing is to be exposed, the return API needs further scrutiny
+    // (especially with things like mask polarity).
+    require(x.head == 'b', "BitPats must be in binary and be prefixed with 'b'")
+    var bits = BigInt(0)
+    var mask = BigInt(0)
+    for (d <- x.tail) {
+      if (d != '_') {
+        require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d)
+        mask = (mask << 1) + (if (d == '?') 0 else 1)
+        bits = (bits << 1) + (if (d == '1') 1 else 0)
+      }
+    }
+    (bits, mask, x.length - 1)
+  }
+
+  /** Creates a [[BitPat]] literal from a string.
+   *
+    * @param n the literal value as a string, in binary, prefixed with 'b'
+    * @note legal characters are '0', '1', and '?', as well as '_' as white
+    * space (which are ignored)
+    */
+  def apply(n: String): BitPat = {
+    val (bits, mask, width) = parse(n)
+    new BitPat(bits, mask, width)
+  }
+
+  /** Creates a [[BitPat]] of all don't cares of the specified bitwidth. */
+  def dontCare(width: Int): BitPat = BitPat("b" + ("?" * width))
+
+  @deprecated("Use BitPat.dontCare", "chisel3")
+  def DC(width: Int): BitPat = dontCare(width)  // scalastyle:ignore method.name
+
+  /** Allows BitPats to be used where a UInt is expected.
+    *
+    * @note the BitPat must not have don't care bits (will error out otherwise)
+    */
+  def bitPatToUInt(x: BitPat): UInt = {
+    require(x.mask == (BigInt(1) << x.getWidth) - 1)
+    UInt(x.value, x.getWidth)
+  }
+
+  /** Allows UInts to be used where a BitPat is expected, useful for when an
+    * interface is defined with BitPats but not all cases need the partial
+    * matching capability.
+    *
+    * @note the UInt must be a literal
+    */
+  def apply(x: UInt): BitPat = {
+    require(x.isLit)
+    BitPat("b" + x.litValue.toString(2))
+  }
+}
+
+// TODO: Break out of Core? (this doesn't involve FIRRTL generation)
+/** Bit patterns are literals with masks, used to represent values with don't
+  * cares. Equality comparisons will ignore don't care bits (for example,
+  * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)).
+  */
+sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
+  def getWidth: Int = width
+  def === (that: UInt): Bool = macro SourceInfoTransform.thatArg
+  def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
+  def != (that: UInt): Bool = macro SourceInfoTransform.thatArg
+
+  def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask))
+  def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that)
+  def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that
+}
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
new file mode 100644
index 00000000..239a295e
--- /dev/null
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -0,0 +1,71 @@
+// See LICENSE for license details.
+
+/** Miscellaneous circuit generators operating on bits.
+  */
+
+package Chisel
+
+object FillInterleaved
+{
+  def apply(n: Int, in: UInt): UInt = apply(n, in.toBools)
+  def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits
+}
+
+/** Returns the number of bits set (i.e value is 1) in the input signal.
+  */
+object PopCount
+{
+  def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq)
+  def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_)))
+}
+
+/** Fill fans out a UInt to multiple copies */
+object Fill {
+  /** Fan out x n times */
+  def apply(n: Int, x: UInt): UInt = {
+    n match {
+      case 0 => UInt(width=0)
+      case 1 => x
+      case y if n > 1 =>
+        val p2 = Array.ofDim[UInt](log2Up(n + 1))
+        p2(0) = x
+        for (i <- 1 until p2.length)
+          p2(i) = Cat(p2(i-1), p2(i-1))
+        Cat((0 until log2Up(y + 1)).filter(i => (y & (1 << i)) != 0).map(p2(_)))
+      case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.")
+    }
+  }
+  /** Fan out x n times */
+  def apply(n: Int, x: Bool): UInt =
+    if (n > 1) {
+      UInt(0,n) - x
+    } else {
+      apply(n, x: UInt)
+    }
+}
+
+/** Litte/big bit endian convertion: reverse the order of the bits in a UInt.
+*/
+object Reverse
+{
+  private def doit(in: UInt, length: Int): UInt = {
+    if (length == 1) {
+      in
+    } else if (isPow2(length) && length >= 8 && length <= 64) {
+      // This esoterica improves simulation performance
+      var res = in
+      var shift = length >> 1
+      var mask = UInt((BigInt(1) << length) - 1, length)
+      do {
+        mask = mask ^ (mask(length-shift-1,0) << shift)
+        res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask)
+        shift = shift >> 1
+      } while (shift > 0)
+      res
+    } else {
+      val half = (1 << log2Up(length))/2
+      Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half))
+    }
+  }
+  def apply(in: UInt): UInt = doit(in, in.getWidth)
+}
diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
new file mode 100644
index 00000000..dd706e62
--- /dev/null
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -0,0 +1,18 @@
+// See LICENSE for license details.
+
+package Chisel
+
+object Cat {
+  /** Combine data elements together
+    * @param a Data to combine with
+    * @param r any number of other Data elements to be combined in order
+    * @return A UInt which is all of the bits combined together
+    */
+  def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList)
+
+  /** Combine data elements together
+    * @param r any number of other Data elements to be combined in order
+    * @return A UInt which is all of the bits combined together
+    */
+  def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse)
+}
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
new file mode 100644
index 00000000..06cab903
--- /dev/null
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -0,0 +1,26 @@
+// See LICENSE for license details.
+
+/** Circuit-land math operations.
+  */
+
+package Chisel
+
+/** Compute Log2 with truncation of a UInt in hardware using a Mux Tree
+  * An alternative interpretation is it computes the minimum number of bits needed to represent x
+  * @example
+  * {{{ data_out := Log2(data_in) }}}
+  * @note Truncation is used so Log2(UInt(12412)) = 13*/
+object Log2 {
+  /** Compute the Log2 on the least significant n bits of x */
+  def apply(x: Bits, width: Int): UInt = {
+    if (width < 2) {
+      UInt(0)
+    } else if (width == 2) {
+      x(1)
+    } else {
+      Mux(x(width-1), UInt(width-1), apply(x, width-1))
+    }
+  }
+
+  def apply(x: Bits): UInt = apply(x, x.getWidth)
+}
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
new file mode 100644
index 00000000..9cab25ef
--- /dev/null
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -0,0 +1,69 @@
+// See LICENSE for license details.
+
+/** Conditional blocks.
+  */
+
+package Chisel
+
+import scala.language.reflectiveCalls
+import scala.language.experimental.macros
+import scala.reflect.runtime.universe._
+import scala.reflect.macros.blackbox._
+
+/** This is identical to [[Chisel.when when]] with the condition inverted */
+object unless {  // scalastyle:ignore object.name
+  def apply(c: Bool)(block: => Unit) {
+    when (!c) { block }
+  }
+}
+
+class SwitchContext[T <: Bits](cond: T) {
+  def is(v: Iterable[T])(block: => Unit) {
+    if (!v.isEmpty) when (v.map(_.asUInt === cond.asUInt).reduce(_||_)) { block }
+  }
+  def is(v: T)(block: => Unit) { is(Seq(v))(block) }
+  def is(v: T, vr: T*)(block: => Unit) { is(v :: vr.toList)(block) }
+}
+
+/** An object for separate cases in [[Chisel.switch switch]]
+  * It is equivalent to a [[Chisel.when$ when]] block comparing to the condition
+  * Use outside of a switch statement is illegal */
+object is {   // scalastyle:ignore object.name
+  // Begin deprecation of non-type-parameterized is statements.
+  def apply(v: Iterable[Bits])(block: => Unit) {
+    require(false, "The 'is' keyword may not be used outside of a switch.")
+  }
+
+  def apply(v: Bits)(block: => Unit) {
+    require(false, "The 'is' keyword may not be used outside of a switch.")
+  }
+
+  def apply(v: Bits, vr: Bits*)(block: => Unit) {
+    require(false, "The 'is' keyword may not be used outside of a switch.")
+  }
+}
+
+/** Conditional logic to form a switch block
+  * @example
+  * {{{ ... // default values here
+  * switch ( myState ) {
+  *   is( state1 ) {
+  *     ... // some logic here
+  *   }
+  *   is( state2 ) {
+  *     ... // some logic here
+  *   }
+  * } }}}*/
+object switch {  // scalastyle:ignore object.name
+  def apply[T <: Bits](cond: T)(x: => Unit): Unit = macro impl
+  def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
+    val sc = c.universe.internal.reificationSupport.freshTermName("sc")
+    def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match {
+      case q"Chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
+    }
+    val q"..$body" = x
+    val ises = body.flatMap(extractIsStatement(_))
+    q"""{ val $sc = new SwitchContext($cond); ..$ises }"""
+  }
+}
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
new file mode 100644
index 00000000..872e830a
--- /dev/null
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -0,0 +1,44 @@
+// See LICENSE for license details.
+
+package Chisel
+
+/** A counter module
+  * @param n number of counts before the counter resets (or one more than the
+  * maximum output value of the counter), need not be a power of two
+  */
+class Counter(val n: Int) {
+  require(n >= 0)
+  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
+  /** Increment the counter, returning whether the counter currently is at the
+    * maximum and will wrap. The incremented value is registered and will be
+    * visible on the next cycle.
+    */
+  def inc(): Bool = {
+    if (n > 1) {
+      val wrap = value === UInt(n-1)
+      value := value + UInt(1)
+      if (!isPow2(n)) {
+        when (wrap) { value := UInt(0) }
+      }
+      wrap
+    } else {
+      Bool(true)
+    }
+  }
+}
+
+/** Counter Object
+  * Example Usage:
+  * {{{ val countOn = Bool(true) // increment counter every clock cycle
+  * val myCounter = Counter(countOn, n)
+  * when ( myCounter.value === UInt(3) ) { ... } }}}*/
+object Counter
+{
+  def apply(n: Int): Counter = new Counter(n)
+  def apply(cond: Bool, n: Int): (UInt, Bool) = {
+    val c = new Counter(n)
+    var wrap: Bool = null
+    when (cond) { wrap = c.inc() }
+    (c.value, cond && wrap)
+  }
+}
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
new file mode 100644
index 00000000..8e045855
--- /dev/null
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -0,0 +1,183 @@
+// See LICENSE for license details.
+
+/** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them.
+  */
+
+package Chisel
+
+/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
+class DecoupledIO[+T <: Data](gen: T) extends Bundle
+{
+  val ready = Bool(INPUT)
+  val valid = Bool(OUTPUT)
+  val bits  = gen.cloneType.asOutput
+  def fire(dummy: Int = 0): Bool = ready && valid
+  override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type]
+}
+
+/** Adds a ready-valid handshaking protocol to any interface.
+  * The standard used is that the consumer uses the flipped interface.
+  */
+object Decoupled {
+  def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
+}
+
+/** An I/O bundle for enqueuing data with valid/ready handshaking
+  * Initialization must be handled, if necessary, by the parent circuit
+  */
+class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen)
+{
+  /** push dat onto the output bits of this interface to let the consumer know it has happened.
+    * @param dat the values to assign to bits.
+    * @return    dat.
+    */
+  def enq(dat: T): T = { valid := Bool(true); bits := dat; dat }
+
+  /** Initialize this Bundle.  Valid is set to false, and all bits are set to zero.
+    * NOTE: This method of initialization is still being discussed and could change in the
+    * future.
+    */
+  def init(): Unit = {
+    valid := Bool(false)
+    for (io <- bits.flatten)
+      io := UInt(0)
+  }
+  override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; }
+}
+
+/** An I/O bundle for dequeuing data with valid/ready handshaking.
+  * Initialization must be handled, if necessary, by the parent circuit
+  */
+class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped
+{
+  /** Assert ready on this port and return the associated data bits.
+    * This is typically used when valid has been asserted by the producer side.
+    * @param b ignored
+    * @return the data for this device,
+    */
+  def deq(b: Boolean = false): T = { ready := Bool(true); bits }
+
+  /** Initialize this Bundle.
+    * NOTE: This method of initialization is still being discussed and could change in the
+    * future.
+    */
+  def init(): Unit = {
+    ready := Bool(false)
+  }
+  override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
+}
+
+/** An I/O bundle for dequeuing data with valid/ready handshaking */
+class DecoupledIOC[+T <: Data](gen: T) extends Bundle
+{
+  val ready = Bool(INPUT)
+  val valid = Bool(OUTPUT)
+  val bits  = gen.cloneType.asOutput
+}
+
+/** An I/O Bundle for Queues
+  * @param gen The type of data to queue
+  * @param entries The max number of entries in the queue */
+class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
+{
+  /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */
+  val enq   = Decoupled(gen.cloneType).flip()
+  /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
+  val deq   = Decoupled(gen.cloneType)
+  /** The current amount of data in the queue */
+  val count = UInt(OUTPUT, log2Up(entries + 1))
+}
+
+/** A hardware module implementing a Queue
+  * @param gen The type of data to queue
+  * @param entries The max number of entries in the queue
+  * @param pipe True if a single entry queue can run at full throughput (like a pipeline). The ''ready'' signals are
+  * combinationally coupled.
+  * @param flow True if the inputs can be consumed on the same cycle (the inputs "flow" through the queue immediately).
+  * The ''valid'' signals are coupled.
+  *
+  * Example usage:
+  *    {{{ val q = new Queue(UInt(), 16)
+  *    q.io.enq <> producer.io.out
+  *    consumer.io.in <> q.io.deq }}}
+  */
+class Queue[T <: Data](gen: T, val entries: Int,
+                       pipe: Boolean = false,
+                       flow: Boolean = false,
+                       override_reset: Option[Bool] = None)
+extends Module(override_reset=override_reset) {
+  def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) =
+    this(gen, entries, pipe, flow, Some(_reset))
+  
+  val io = new QueueIO(gen, entries)
+
+  val ram = Mem(entries, gen)
+  val enq_ptr = Counter(entries)
+  val deq_ptr = Counter(entries)
+  val maybe_full = Reg(init=Bool(false))
+
+  val ptr_match = enq_ptr.value === deq_ptr.value
+  val empty = ptr_match && !maybe_full
+  val full = ptr_match && maybe_full
+  val do_enq = Wire(init=io.enq.fire())
+  val do_deq = Wire(init=io.deq.fire())
+
+  when (do_enq) {
+    ram(enq_ptr.value) := io.enq.bits
+    enq_ptr.inc()
+  }
+  when (do_deq) {
+    deq_ptr.inc()
+  }
+  when (do_enq != do_deq) {
+    maybe_full := do_enq
+  }
+
+  io.deq.valid := !empty
+  io.enq.ready := !full
+  io.deq.bits := ram(deq_ptr.value)
+
+  if (flow) {
+    when (io.enq.valid) { io.deq.valid := Bool(true) }
+    when (empty) {
+      io.deq.bits := io.enq.bits
+      do_deq := Bool(false)
+      when (io.deq.ready) { do_enq := Bool(false) }
+    }
+  }
+
+  if (pipe) {
+    when (io.deq.ready) { io.enq.ready := Bool(true) }
+  }
+
+  val ptr_diff = enq_ptr.value - deq_ptr.value
+  if (isPow2(entries)) {
+    io.count := Cat(maybe_full && ptr_match, ptr_diff)
+  } else {
+    io.count := Mux(ptr_match,
+                    Mux(maybe_full,
+                      UInt(entries), UInt(0)),
+                    Mux(deq_ptr.value > enq_ptr.value,
+                      UInt(entries) + ptr_diff, ptr_diff))
+  }
+}
+
+/** Generic hardware queue. Required parameter entries controls
+  the depth of the queues. The width of the queue is determined
+  from the inputs.
+
+  Example usage:
+     {{{ val q = Queue(Decoupled(UInt()), 16)
+     q.io.enq <> producer.io.out
+     consumer.io.in <> q.io.deq }}}
+  */
+object Queue
+{
+  def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T]  = {
+    val q = Module(new Queue(enq.bits.cloneType, entries, pipe))
+    q.io.enq.valid := enq.valid // not using <> so that override is allowed
+    q.io.enq.bits := enq.bits
+    enq.ready := q.io.enq.ready
+    TransitName(q.io.deq, q)
+  }
+}
diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
new file mode 100644
index 00000000..20057197
--- /dev/null
+++ b/src/main/scala/chisel3/util/Enum.scala
@@ -0,0 +1,21 @@
+// See LICENSE for license details.
+
+/** Enum generators, allowing circuit constants to have more meaningful names.
+  */
+
+package Chisel
+
+object Enum {
+  /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
+  private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] =
+    (0 until n).map(x => nodeType.fromInt(x, log2Up(n)))
+
+  /** create n enum values of given type */
+  def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList
+
+  /** create enum values of given type and names */
+  def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap
+
+  /** create enum values of given type and names */
+  def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap
+}
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
new file mode 100644
index 00000000..6a230022
--- /dev/null
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -0,0 +1,8 @@
+// See LICENSE for license details.
+
+package Chisel
+
+object ImplicitConversions {
+  implicit def intToUInt(x: Int): UInt = UInt(x)
+  implicit def booleanToBool(x: Boolean): Bool = Bool(x)
+}
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
new file mode 100644
index 00000000..839b1d1f
--- /dev/null
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -0,0 +1,22 @@
+// See LICENSE for license details.
+
+/** LFSRs in all shapes and sizes.
+  */
+
+package Chisel
+
+// scalastyle:off magic.number
+/** linear feedback shift register
+  */
+object LFSR16
+{
+  def apply(increment: Bool = Bool(true)): UInt =
+  {
+    val width = 16
+    val lfsr = Reg(init=UInt(1, width))
+    when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
+    lfsr
+  }
+}
+// scalastyle:on magic.number
+
diff --git a/src/main/scala/chisel3/util/Lookup.scala b/src/main/scala/chisel3/util/Lookup.scala
new file mode 100644
index 00000000..54922fc4
--- /dev/null
+++ b/src/main/scala/chisel3/util/Lookup.scala
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+
+package Chisel
+
+object ListLookup {
+  def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = {
+    val map = mapping.map(m => (m._1 === addr, m._2))
+    default.zipWithIndex map { case (d, i) =>
+      map.foldRight(d)((m, n) => Mux(m._1, m._2(i), n))
+    }
+  }
+}
+
+object Lookup {
+  def apply[T <: Bits](addr: UInt, default: T, mapping: Seq[(BitPat, T)]): T =
+    ListLookup(addr, List(default), mapping.map(m => (m._1, List(m._2))).toArray).head
+}
diff --git a/src/main/scala/chisel3/util/Math.scala b/src/main/scala/chisel3/util/Math.scala
new file mode 100644
index 00000000..5f8212d8
--- /dev/null
+++ b/src/main/scala/chisel3/util/Math.scala
@@ -0,0 +1,42 @@
+// See LICENSE for license details.
+
+/** Scala-land math helper functions, like logs.
+  */
+
+package Chisel
+
+/** Compute the log2 rounded up with min value of 1 */
+object log2Up {
+  def apply(in: BigInt): Int = {
+    require(in >= 0)
+    1 max (in-1).bitLength
+  }
+  def apply(in: Int): Int = apply(BigInt(in))
+}
+
+/** Compute the log2 rounded up */
+object log2Ceil {
+  def apply(in: BigInt): Int = {
+    require(in > 0)
+    (in-1).bitLength
+  }
+  def apply(in: Int): Int = apply(BigInt(in))
+}
+
+/** Compute the log2 rounded down with min value of 1 */
+object log2Down {
+  def apply(in: BigInt): Int = log2Up(in) - (if (isPow2(in)) 0 else 1)
+  def apply(in: Int): Int = apply(BigInt(in))
+}
+
+/** Compute the log2 rounded down */
+object log2Floor {
+  def apply(in: BigInt): Int = log2Ceil(in) - (if (isPow2(in)) 0 else 1)
+  def apply(in: Int): Int = apply(BigInt(in))
+}
+
+/** Check if an Integer is a power of 2 */
+object isPow2 {
+  def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0)
+  def apply(in: Int): Boolean = apply(BigInt(in))
+}
diff --git a/src/main/scala/chisel3/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala
new file mode 100644
index 00000000..9d92321a
--- /dev/null
+++ b/src/main/scala/chisel3/util/Mux.scala
@@ -0,0 +1,61 @@
+// See LICENSE for license details.
+
+/** Mux circuit generators.
+  */
+
+package Chisel
+
+/** Builds a Mux tree out of the input signal vector using a one hot encoded
+  select signal. Returns the output of the Mux tree.
+  */
+object Mux1H
+{
+  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T =
+    apply(sel zip in)
+  def apply[T <: Data](in: Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in)
+  def apply[T <: Data](sel: UInt, in: Seq[T]): T =
+    apply((0 until in.size).map(sel(_)), in)
+  def apply(sel: UInt, in: UInt): Bool = (sel & in).orR
+}
+
+/** Builds a Mux tree under the assumption that multiple select signals
+  can be enabled. Priority is given to the first select signal.
+
+  Returns the output of the Mux tree.
+  */
+object PriorityMux
+{
+  def apply[T <: Data](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in)
+  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in)
+  def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in)
+}
+
+/** MuxLookup creates a cascade of n Muxs to search for a key value */
+object MuxLookup {
+  /** @param key a key to search for
+    * @param default a default value if nothing is found
+    * @param mapping a sequence to search of keys and values
+    * @return the value found or the default if not
+    */
+  def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = {
+    var res = default
+    for ((k, v) <- mapping.reverse)
+      res = Mux(k === key, v, res)
+    res
+  }
+
+}
+
+/** MuxCase returns the first value that is enabled in a map of values */
+object MuxCase {
+  /** @param default the default value if none are enabled
+    * @param mapping a set of data values with associated enables
+    * @return the first value in mapping that is enabled */
+  def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = {
+    var res = default
+    for ((t, v) <- mapping.reverse){
+      res = Mux(t, v, res)
+    }
+    res
+  }
+}
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
new file mode 100644
index 00000000..73f27403
--- /dev/null
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -0,0 +1,62 @@
+// See LICENSE for license details.
+
+/** Circuit generators for working with one-hot representations.
+  */
+
+package Chisel
+
+/** Converts from One Hot Encoding to a UInt indicating which bit is active
+  * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/
+object OHToUInt {
+  def apply(in: Seq[Bool]): UInt = apply(Vec(in))
+  def apply(in: Vec[Bool]): UInt = apply(in.toBits, in.size)
+  def apply(in: Bits): UInt = apply(in, in.getWidth)
+
+  def apply(in: Bits, width: Int): UInt = {
+    if (width <= 2) {
+      Log2(in, width)
+    } else {
+      val mid = 1 << (log2Up(width)-1)
+      val hi = in(width-1, mid)
+      val lo = in(mid-1, 0)
+      Cat(hi.orR, apply(hi | lo, mid))
+    }
+  }
+}
+
+/** @return the bit position of the trailing 1 in the input vector
+  * with the assumption that multiple bits of the input bit vector can be set
+  * @example {{{ data_out := PriorityEncoder(data_in) }}}
+  */
+object PriorityEncoder {
+  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
+  def apply(in: Bits): UInt = apply(in.toBools)
+}
+
+/** Returns the one hot encoding of the input UInt.
+  */
+object UIntToOH
+{
+  def apply(in: UInt, width: Int = -1): UInt =
+    if (width == -1) {
+      UInt(1) << in
+    } else {
+      (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
+    }
+}
+
+/** Returns a bit vector in which only the least-significant 1 bit in
+  the input vector, if any, is set.
+  */
+object PriorityEncoderOH
+{
+  private def encode(in: Seq[Bool]): UInt = {
+    val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size))
+    PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size))
+  }
+  def apply(in: Seq[Bool]): Seq[Bool] = {
+    val enc = encode(in)
+    Seq.tabulate(in.size)(enc(_))
+  }
+  def apply(in: Bits): UInt = encode((0 until in.getWidth).map(i => in(i)))
+}
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
new file mode 100644
index 00000000..6584a4bf
--- /dev/null
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -0,0 +1,55 @@
+// See LICENSE for license details.
+
+/** Variations and helpers for registers.
+  */
+
+package Chisel
+
+object RegNext {
+
+  def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T])
+
+  def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init)
+
+}
+
+object RegInit {
+
+  def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init)
+
+}
+
+/** A register with an Enable signal */
+object RegEnable
+{
+  def apply[T <: Data](updateData: T, enable: Bool): T = {
+    val r = Reg(updateData)
+    when (enable) { r := updateData }
+    r
+  }
+  def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
+    val r = RegInit(resetData)
+    when (enable) { r := updateData }
+    r
+  }
+}
+
+/** Returns the n-cycle delayed version of the input signal.
+  */
+object ShiftRegister
+{
+  /** @param in input to delay
+    * @param n number of cycles to delay
+    * @param en enable the shift */
+  def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T =
+  {
+    // The order of tests reflects the expected use cases.
+    if (n == 1) {
+      RegEnable(in, en)
+    } else if (n != 0) {
+      RegNext(apply(in, n-1, en))
+    } else {
+      in
+    }
+  }
+}
diff --git a/src/main/scala/chisel3/util/TransitName.scala b/src/main/scala/chisel3/util/TransitName.scala
new file mode 100644
index 00000000..ec5a11cc
--- /dev/null
+++ b/src/main/scala/chisel3/util/TransitName.scala
@@ -0,0 +1,21 @@
+package Chisel
+
+import internal.HasId
+
+object TransitName {
+  // The purpose of this is to allow a library to 'move' a name call to a more
+  // appropriate place.
+  // For example, a library factory function may create a module and return
+  // the io. The only user-exposed field is that given IO, which can't use
+  // any name supplied by the user. This can add a hook so that the supplied
+  // name then names the Module.
+  // See Queue companion object for working example
+  def apply[T<:HasId](from: T, to: HasId): T = {
+    from.addPostnameHook((given_name: String) => {to.suggestName(given_name)})
+    from
+  }
+  def withSuffix[T<:HasId](suffix: String)(from: T, to: HasId): T = {
+    from.addPostnameHook((given_name: String) => {to.suggestName(given_name+suffix)})
+    from
+  }
+}
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
new file mode 100644
index 00000000..9e2202bb
--- /dev/null
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -0,0 +1,59 @@
+// See LICENSE for license details.
+
+/** Wrappers for valid interfaces and associated circuit generators using them.
+  */
+
+package Chisel
+
+/** An I/O Bundle containing data and a signal determining if it is valid */
+class ValidIO[+T <: Data](gen2: T) extends Bundle
+{
+  val valid = Bool(OUTPUT)
+  val bits = gen2.cloneType.asOutput
+  def fire(dummy: Int = 0): Bool = valid
+  override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type]
+}
+
+/** Adds a valid protocol to any interface. The standard used is
+  that the consumer uses the flipped interface.
+*/
+object Valid {
+  def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen)
+}
+
+/** A hardware module that delays data coming down the pipeline
+  by the number of cycles set by the latency parameter. Functionality
+  is similar to ShiftRegister but this exposes a Pipe interface.
+
+  Example usage:
+    val pipe = new Pipe(UInt())
+    pipe.io.enq <> produce.io.out
+    consumer.io.in <> pipe.io.deq
+  */
+object Pipe
+{
+  def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = {
+    if (latency == 0) {
+      val out = Wire(Valid(enqBits))
+      out.valid <> enqValid
+      out.bits <> enqBits
+      out
+    } else {
+      val v = Reg(Bool(), next=enqValid, init=Bool(false))
+      val b = RegEnable(enqBits, enqValid)
+      apply(v, b, latency-1)
+    }
+  }
+  def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1)
+  def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency)
+}
+
+class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module
+{
+  val io = new Bundle {
+    val enq = Valid(gen).flip
+    val deq = Valid(gen)
+  }
+
+  io.deq <> Pipe(io.enq, latency)
+}
-- 
cgit v1.2.3


From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 09:31:47 -0700
Subject: Update Chisel -> chisel3 references.

---
 src/main/scala/chisel3/Driver.scala                |  3 +-
 .../compatibility/FileSystemUtilities.scala        |  4 +-
 src/main/scala/chisel3/compatibility/Main.scala    |  4 +-
 .../chisel3/compatibility/throwException.scala     |  4 +-
 .../scala/chisel3/internal/firrtl/Emitter.scala    |  8 +--
 src/main/scala/chisel3/package.scala               | 82 +++++++++++++++++++++-
 src/main/scala/chisel3/testers/BasicTester.scala   |  4 +-
 src/main/scala/chisel3/testers/TesterDriver.scala  |  5 +-
 src/main/scala/chisel3/util/Arbiter.scala          |  4 +-
 src/main/scala/chisel3/util/BitPat.scala           |  5 +-
 src/main/scala/chisel3/util/Bitwise.scala          |  5 +-
 src/main/scala/chisel3/util/Cat.scala              |  5 +-
 src/main/scala/chisel3/util/CircuitMath.scala      |  4 +-
 src/main/scala/chisel3/util/Conditional.scala      |  8 ++-
 src/main/scala/chisel3/util/Counter.scala          |  4 +-
 src/main/scala/chisel3/util/Decoupled.scala        |  4 +-
 src/main/scala/chisel3/util/Enum.scala             |  4 +-
 .../scala/chisel3/util/ImplicitConversions.scala   |  4 +-
 src/main/scala/chisel3/util/LFSR.scala             |  4 +-
 src/main/scala/chisel3/util/Lookup.scala           |  4 +-
 src/main/scala/chisel3/util/Math.scala             |  4 +-
 src/main/scala/chisel3/util/Mux.scala              |  9 ++-
 src/main/scala/chisel3/util/OneHot.scala           |  4 +-
 src/main/scala/chisel3/util/Reg.scala              |  4 +-
 src/main/scala/chisel3/util/TransitName.scala      |  3 +-
 src/main/scala/chisel3/util/Valid.scala            |  4 +-
 src/test/scala/chiselTests/Assert.scala            |  5 +-
 src/test/scala/chiselTests/BitwiseOps.scala        |  4 +-
 src/test/scala/chiselTests/BlackBox.scala          |  6 +-
 src/test/scala/chiselTests/BundleWire.scala        |  4 +-
 src/test/scala/chiselTests/ChiselSpec.scala        |  4 +-
 src/test/scala/chiselTests/ComplexAssign.scala     |  6 +-
 src/test/scala/chiselTests/Counter.scala           |  7 +-
 src/test/scala/chiselTests/Decoder.scala           |  7 +-
 src/test/scala/chiselTests/DeqIOSpec.scala         |  5 +-
 src/test/scala/chiselTests/Direction.scala         |  4 +-
 .../scala/chiselTests/EnableShiftRegister.scala    |  4 +-
 src/test/scala/chiselTests/GCD.scala               |  4 +-
 src/test/scala/chiselTests/Harness.scala           |  5 +-
 src/test/scala/chiselTests/LFSR16.scala            |  8 ++-
 src/test/scala/chiselTests/MemorySearch.scala      |  5 +-
 src/test/scala/chiselTests/Module.scala            |  3 +-
 src/test/scala/chiselTests/MulLookup.scala         |  4 +-
 src/test/scala/chiselTests/MultiAssign.scala       | 22 +++---
 src/test/scala/chiselTests/OptionBundle.scala      |  4 +-
 src/test/scala/chiselTests/Padding.scala           |  3 +-
 .../scala/chiselTests/ParameterizedModule.scala    |  4 +-
 src/test/scala/chiselTests/Printf.scala            |  4 +-
 src/test/scala/chiselTests/Reg.scala               |  5 +-
 src/test/scala/chiselTests/Risc.scala              |  4 +-
 src/test/scala/chiselTests/SIntOps.scala           |  5 +-
 src/test/scala/chiselTests/Stack.scala             |  5 +-
 src/test/scala/chiselTests/Stop.scala              |  4 +-
 src/test/scala/chiselTests/Tbl.scala               |  6 +-
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  5 +-
 src/test/scala/chiselTests/UIntOps.scala           |  5 +-
 src/test/scala/chiselTests/Vec.scala               |  6 +-
 src/test/scala/chiselTests/VectorPacketIO.scala    |  5 +-
 src/test/scala/chiselTests/VendingMachine.scala    |  4 +-
 src/test/scala/chiselTests/When.scala              |  6 +-
 60 files changed, 270 insertions(+), 109 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 02204684..0979314f 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3
 
 import scala.sys.process._
 import java.io._
@@ -71,6 +71,7 @@ trait BackendCompilationUtilities {
         "--top-module", topModule,
         "+define+TOP_TYPE=V" + dutFile,
         s"+define+PRINTF_COND=!$topModule.reset",
+        s"+define+STOP_COND=!$topModule.reset",
         "-CFLAGS",
         s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
         "-Mdir", dir.toString,
diff --git a/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
index 575ae138..cd47c731 100644
--- a/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
+++ b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.compatibility
+
+import chisel3._
 
 @deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0")
 trait FileSystemUtilities {
diff --git a/src/main/scala/chisel3/compatibility/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala
index a72debc3..a41599a3 100644
--- a/src/main/scala/chisel3/compatibility/Main.scala
+++ b/src/main/scala/chisel3/compatibility/Main.scala
@@ -1,9 +1,11 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.compatibility
 
 import java.io.File
 
+import chisel3._
+
 @deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
   def apply[T <: Module](args: Array[String], gen: () => T): Unit =
     Predef.assert(false, "No more chiselMain in Chisel3")
diff --git a/src/main/scala/chisel3/compatibility/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala
index 702884aa..3e8b33e6 100644
--- a/src/main/scala/chisel3/compatibility/throwException.scala
+++ b/src/main/scala/chisel3/compatibility/throwException.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.compatibility
+
+import chisel3._
 
 @deprecated("throwException doesn't exist in Chisel3", "3.0.0")
 @throws(classOf[Exception])
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 7ca3268a..08646cf9 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package Chisel.internal.firrtl
-import Chisel._
-import Chisel.internal.sourceinfo.{NoSourceInfo, SourceLine}
+package chisel3.internal.firrtl
+import chisel3._
+import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine}
 
-private[Chisel] object Emitter {
+private[chisel3] object Emitter {
   def emit(circuit: Circuit): String = new Emitter(circuit).toString
 }
 
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index f05e8b5d..35bbd1c4 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,12 +1,88 @@
-package object Chisel {
+package object chisel3 {
   import scala.language.experimental.macros
-  
+
   import internal.firrtl.Width
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
   
   implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
     def U: UInt = UInt(x, Width())
     def S: SInt = SInt(x, Width())
+
+  import util.BitPat
+
+
+  type Direction = chisel3.core.Direction
+  type Data = chisel3.core.Data
+  val Wire = chisel3.core.Wire
+  val Clock = chisel3.core.Clock
+  type Clock = chisel3.core.Clock
+
+  type Aggregate = chisel3.core.Aggregate
+  val Vec = chisel3.core.Vec
+  type Vec[T <: Data] = chisel3.core.Vec[T]
+  type VecLike[T <: Data] = chisel3.core.VecLike[T]
+  type Bundle = chisel3.core.Bundle
+
+  val assert = chisel3.core.assert
+
+  type Element = chisel3.core.Element
+  type Bits = chisel3.core.Bits
+  val Bits = chisel3.core.Bits
+  type Num[T <: Data] = chisel3.core.Num[T]
+  type UInt = chisel3.core.UInt
+  val UInt = chisel3.core.UInt
+  type SInt = chisel3.core.SInt
+  val SInt = chisel3.core.SInt
+  type Bool = chisel3.core.Bool
+  val Bool = chisel3.core.Bool
+  val Mux = chisel3.core.Mux
+
+  type BlackBox = chisel3.core.BlackBox
+
+  val Mem = chisel3.core.Mem
+  type MemBase[T <: Data] = chisel3.core.MemBase[T]
+  type Mem[T <: Data] = chisel3.core.Mem[T]
+  val SeqMem = chisel3.core.SeqMem
+  type SeqMem[T <: Data] = chisel3.core.SeqMem[T]
+
+  val Module = chisel3.core.Module
+  type Module = chisel3.core.Module
+
+  val printf = chisel3.core.printf
+
+  val Reg = chisel3.core.Reg
+
+  val when = chisel3.core.when
+  type WhenContext = chisel3.core.WhenContext
+
+  /**
+  * These implicit classes allow one to convert scala.Int|scala.BigInt to
+  * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
+  * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
+  * mark a width for the new literal.
+  *
+  * Also provides .asBool to scala.Boolean and .asUInt to String
+  *
+  * Note that, for stylistic reasons, one hould avoid extracting immediately
+  * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
+  * confusion (the 1 is a bit length and the 0 is a bit extraction position).
+  * Prefer storing the result and then extracting from it.
+  */
+  implicit class addLiteraltoScalaInt(val target: Int) extends AnyVal {
+    def asUInt() = UInt.Lit(target)
+    def asSInt() = SInt.Lit(target)
+    def asUInt(width: Int) = UInt.Lit(target, width)
+    def asSInt(width: Int) = SInt.Lit(target, width)
+
+    // These were recently added to chisel2/3 but are not to be used internally
+    @deprecated("asUInt should be used over U", "gchisel")
+    def U() = UInt.Lit(target)
+    @deprecated("asSInt should be used over S", "gchisel")
+    def S() = SInt.Lit(target)
+    @deprecated("asUInt should be used over U", "gchisel")
+    def U(width: Int) = UInt.Lit(target, width)
+    @deprecated("asSInt should be used over S", "gchisel")
+    def S(width: Int) = SInt.Lit(target, width)
   }
   implicit class fromIntToLiteral(val x: Int) extends AnyVal {
     def U: UInt = UInt(BigInt(x), Width())
@@ -23,7 +99,7 @@ package object Chisel {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-  
+
     def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x
     def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
     def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index b8c1494a..f91536d5 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 
-package Chisel.testers
-import Chisel._
+package chisel3.testers
+import chisel3._
 
 import scala.language.experimental.macros
 
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index a56bb8b7..586fa780 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel.testers
-import Chisel._
+package chisel3.testers
+
+import chisel3._
 import scala.io.Source
 import scala.sys.process._
 import java.io._
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 16ae9be5..eb541977 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -3,7 +3,9 @@
 /** Arbiters in all shapes and sizes.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** An I/O bundle for the Arbiter */
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 96206f63..9eb5cf67 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -1,10 +1,11 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
 
 import scala.language.experimental.macros
 
-import Chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+import chisel3._
+import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
 object BitPat {
   /** Parses a bit pattern string into (bits, mask, width).
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 239a295e..ab1ff550 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -3,7 +3,10 @@
 /** Miscellaneous circuit generators operating on bits.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
+import chisel3.core.SeqUtils
 
 object FillInterleaved
 {
diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index dd706e62..469bf9ab 100644
--- a/src/main/scala/chisel3/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -1,6 +1,9 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
+
+import chisel3._
+import chisel3.core.SeqUtils
 
 object Cat {
   /** Combine data elements together
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 06cab903..1174c71c 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -3,7 +3,9 @@
 /** Circuit-land math operations.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** Compute Log2 with truncation of a UInt in hardware using a Mux Tree
   * An alternative interpretation is it computes the minimum number of bits needed to represent x
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 9cab25ef..6218feb0 100644
--- a/src/main/scala/chisel3/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -3,13 +3,15 @@
 /** Conditional blocks.
   */
 
-package Chisel
+package chisel3.util
 
 import scala.language.reflectiveCalls
 import scala.language.experimental.macros
 import scala.reflect.runtime.universe._
 import scala.reflect.macros.blackbox._
 
+import chisel3._
+
 /** This is identical to [[Chisel.when when]] with the condition inverted */
 object unless {  // scalastyle:ignore object.name
   def apply(c: Bool)(block: => Unit) {
@@ -59,7 +61,9 @@ object switch {  // scalastyle:ignore object.name
   def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
     val sc = c.universe.internal.reificationSupport.freshTermName("sc")
     def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match {
-      case q"Chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      // TODO: remove when Chisel compatibility package is removed
+      case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      case q"chisel3.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
       case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
     }
     val q"..$body" = x
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 872e830a..40615769 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** A counter module
   * @param n number of counts before the counter resets (or one more than the
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 8e045855..339fde7c 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -3,7 +3,9 @@
 /** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
 class DecoupledIO[+T <: Data](gen: T) extends Bundle
diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
index 20057197..4ecc243b 100644
--- a/src/main/scala/chisel3/util/Enum.scala
+++ b/src/main/scala/chisel3/util/Enum.scala
@@ -3,7 +3,9 @@
 /** Enum generators, allowing circuit constants to have more meaningful names.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 object Enum {
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 6a230022..4d816a19 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 object ImplicitConversions {
   implicit def intToUInt(x: Int): UInt = UInt(x)
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index 839b1d1f..a30c276f 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -3,7 +3,9 @@
 /** LFSRs in all shapes and sizes.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 // scalastyle:off magic.number
 /** linear feedback shift register
diff --git a/src/main/scala/chisel3/util/Lookup.scala b/src/main/scala/chisel3/util/Lookup.scala
index 54922fc4..9e909c0c 100644
--- a/src/main/scala/chisel3/util/Lookup.scala
+++ b/src/main/scala/chisel3/util/Lookup.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 object ListLookup {
   def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = {
diff --git a/src/main/scala/chisel3/util/Math.scala b/src/main/scala/chisel3/util/Math.scala
index 5f8212d8..73665f0f 100644
--- a/src/main/scala/chisel3/util/Math.scala
+++ b/src/main/scala/chisel3/util/Math.scala
@@ -3,7 +3,9 @@
 /** Scala-land math helper functions, like logs.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** Compute the log2 rounded up with min value of 1 */
 object log2Up {
diff --git a/src/main/scala/chisel3/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala
index 9d92321a..9956a7e3 100644
--- a/src/main/scala/chisel3/util/Mux.scala
+++ b/src/main/scala/chisel3/util/Mux.scala
@@ -3,7 +3,10 @@
 /** Mux circuit generators.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
+import chisel3.core.SeqUtils
 
 /** Builds a Mux tree out of the input signal vector using a one hot encoded
   select signal. Returns the output of the Mux tree.
@@ -37,7 +40,7 @@ object MuxLookup {
     * @param mapping a sequence to search of keys and values
     * @return the value found or the default if not
     */
-  def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = {
+  def apply[S <: UInt, T <: Data] (key: S, default: T, mapping: Seq[(S, T)]): T = {
     var res = default
     for ((k, v) <- mapping.reverse)
       res = Mux(k === key, v, res)
@@ -51,7 +54,7 @@ object MuxCase {
   /** @param default the default value if none are enabled
     * @param mapping a set of data values with associated enables
     * @return the first value in mapping that is enabled */
-  def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = {
+  def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
     var res = default
     for ((t, v) <- mapping.reverse){
       res = Mux(t, v, res)
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 73f27403..820c72d6 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -3,7 +3,9 @@
 /** Circuit generators for working with one-hot representations.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** Converts from One Hot Encoding to a UInt indicating which bit is active
   * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 6584a4bf..81de4754 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -3,7 +3,9 @@
 /** Variations and helpers for registers.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 object RegNext {
 
diff --git a/src/main/scala/chisel3/util/TransitName.scala b/src/main/scala/chisel3/util/TransitName.scala
index ec5a11cc..f36f926f 100644
--- a/src/main/scala/chisel3/util/TransitName.scala
+++ b/src/main/scala/chisel3/util/TransitName.scala
@@ -1,5 +1,6 @@
-package Chisel
+package chisel3.util
 
+import chisel3._
 import internal.HasId
 
 object TransitName {
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 9e2202bb..78187ff6 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -3,7 +3,9 @@
 /** Wrappers for valid interfaces and associated circuit generators using them.
   */
 
-package Chisel
+package chisel3.util
+
+import chisel3._
 
 /** An I/O Bundle containing data and a signal determining if it is valid */
 class ValidIO[+T <: Data](gen2: T) extends Bundle
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 24eb8b55..3fed2bd4 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -3,8 +3,9 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class FailingAssertTester() extends BasicTester {
   assert(Bool(false))
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 19aa956c..08999a1b 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index ca94087c..fdc5970e 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -4,8 +4,10 @@ package chiselTests
 
 import java.io.File
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class BlackBoxInverter extends BlackBox {
   val io = new Bundle() {
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index d2e42fa9..e5e9fb1a 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class Coord extends Bundle {
   val x = UInt(width = 32)
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index da68b0cb..d335bdf6 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -6,8 +6,8 @@ import java.io.File
 import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
-import Chisel._
-import Chisel.testers._
+import chisel3._
+import chisel3.testers._
 
 /** Common utility functions for Chisel unit tests. */
 trait ChiselRunners extends Assertions {
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index d79a2625..304fbcf5 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -1,11 +1,13 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
 import org.scalatest._
 import org.scalatest.prop._
 
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 07a76cdc..69d8a44a 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -1,10 +1,13 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index e5cdfd07..5586561b 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -1,11 +1,14 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
 import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 8f7937ab..09891647 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -2,8 +2,9 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /**
   * Created by chick on 2/8/16.
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index dd2f6572..8b84f844 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class DirectionHaver extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 6600df2a..7db20fc1 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class EnableShiftRegister extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index a1bfffda..60a70cc8 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -2,8 +2,8 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 
diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index bc838766..83f60391 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -1,13 +1,14 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel.testers.BasicTester
+
+import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 import java.io.File
 
 class HarnessSpec extends ChiselPropSpec
-  with Chisel.BackendCompilationUtilities {
+  with chisel3.BackendCompilationUtilities {
 
   def makeTrivialVerilog: (File => File) = makeHarness((prefix: String) => s"""
 module ${prefix};
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index ed76a296..a1699441 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -1,8 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class LFSR16 extends Module {
   val io = new Bundle {
@@ -34,7 +36,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) {
 }
 */
 
-//TODO: Use chisel.util version instead?
+//TODO: Use chisel3.util version instead?
 
 class LFSRSpec extends ChiselPropSpec {
 
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 55b704a0..679b894c 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -1,8 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
 
 class MemorySearch extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 88ba795b..23788b72 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
 
 class SimpleIO extends Bundle {
   val in  = UInt(INPUT,  32)
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 49ba13c7..831e323f 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 2f464123..d5e9b998 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -3,29 +3,31 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
 
   val test = Wire(UInt(width=4))
-  assert(test === UInt(7))  // allow read references before assign references
+  assert(test === UInt.Lit(7))  // allow read references before assign references
 
-  test := UInt(13)
-  assert(test === UInt(7))  // output value should be position-independent
+  test := UInt.Lit(13)
+  assert(test === UInt.Lit(7))  // output value should be position-independent
 
-  test := UInt(7)
-  assert(test === UInt(7))  // this obviously should work
+  test := UInt.Lit(7)
+  assert(test === UInt.Lit(7))  // this obviously should work
 
-  when(cnt.value === UInt(1)) {
+  when(cnt.value === UInt.Lit(1)) {
     stop()
   }
 }
 
 class ReassignmentTester() extends BasicTester {
-  val test = UInt(15)
-  test := UInt(7)
+  val test = UInt.Lit(15)
+  test := UInt.Lit(7)
 }
 
 class MultiAssignSpec extends ChiselFlatSpec {
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index c5a347e6..fa691b43 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class OptionBundle(hasIn: Boolean) extends Bundle {
   val in = if (hasIn) {
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 999b7d36..3fb0f955 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
 
 class Padder extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index 35e3ba78..4859759e 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class ParameterizedModule(invert: Boolean) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index eb8b4b25..c872fde4 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
   val x = UInt(254)
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index f2620d88..391dd7de 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -3,8 +3,9 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.core.DataMirror
+import chisel3.testers.BasicTester
 
 class RegSpec extends ChiselFlatSpec {
   "A Reg" should "throw an exception if not given any parameters" in {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 3daa5bd2..f5e61115 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -1,7 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
+import chisel3.util._
 
 class Risc extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 0835fb4d..6cd013f1 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -1,8 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
 
 class SIntOps extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ac799c8a..cbd9f3e3 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -1,8 +1,11 @@
 // See LICENSE for license details.
 
 package chiselTests
+
 import scala.collection.mutable.Stack
-import Chisel._
+
+import chisel3._
+import chisel3.util._
 
 class ChiselStack(val depth: Int) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala
index 878f090c..4afb077a 100644
--- a/src/test/scala/chiselTests/Stop.scala
+++ b/src/test/scala/chiselTests/Stop.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class StopTester() extends BasicTester {
   stop()
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index c79eb8a4..d84cd85e 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -2,10 +2,12 @@
 
 package chiselTests
 
-import Chisel._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 3c57daae..2f3e9368 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -2,8 +2,9 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /** Extend BasicTester with a simple circuit and finish method.  TesterDriver will call the
   * finish method after the FinishTester's constructor has completed, which will alter the
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index bb0b0f06..c5069fc4 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -1,9 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
 import org.scalatest._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class UIntOps extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 943d9e4b..7dd80a13 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -2,10 +2,12 @@
 
 package chiselTests
 
-import Chisel._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 99ec66a6..07779faa 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -2,8 +2,9 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /**
   * This test used to fail when assignment statements were
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 012fc493..f03cb881 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -1,7 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
+import chisel3.util._
 
 class VendingMachine extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index a6572706..5f3d3e61 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -3,8 +3,10 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)
-- 
cgit v1.2.3


From 3120eefc8a73b5ab3d8f909445a3e004b5e60cc6 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 19 Jul 2016 15:08:22 -0700
Subject: Incorporate connection logic. Compiles but fails tests.

---
 src/main/scala/chisel3/package.scala         | 45 +++++++++++++++-------------
 src/main/scala/chisel3/util/Decoupled.scala  | 14 ++++-----
 src/test/scala/chiselTests/Module.scala      |  2 +-
 src/test/scala/chiselTests/MultiAssign.scala | 19 ++++++------
 src/test/scala/chiselTests/Reg.scala         | 18 +++++------
 5 files changed, 51 insertions(+), 47 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 35bbd1c4..71ec0e92 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -3,15 +3,21 @@ package object chisel3 {
 
   import internal.firrtl.Width
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-  
-  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
-    def U: UInt = UInt(x, Width())
-    def S: SInt = SInt(x, Width())
 
   import util.BitPat
 
 
   type Direction = chisel3.core.Direction
+  object Input {
+    def apply[T<:Data](target: T): T = chisel3.core.Input(target)
+  }
+  object Output {
+    def apply[T<:Data](target: T): T = chisel3.core.Output(target)
+  }
+  object Flipped {
+    def apply[T<:Data](target: T): T = chisel3.core.Flipped(target)
+  }
+
   type Data = chisel3.core.Data
   val Wire = chisel3.core.Wire
   val Clock = chisel3.core.Clock
@@ -63,30 +69,24 @@ package object chisel3 {
   *
   * Also provides .asBool to scala.Boolean and .asUInt to String
   *
-  * Note that, for stylistic reasons, one hould avoid extracting immediately
+  * Note that, for stylistic reasons, one should avoid extracting immediately
   * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
   * confusion (the 1 is a bit length and the 0 is a bit extraction position).
   * Prefer storing the result and then extracting from it.
   */
-  implicit class addLiteraltoScalaInt(val target: Int) extends AnyVal {
-    def asUInt() = UInt.Lit(target)
-    def asSInt() = SInt.Lit(target)
-    def asUInt(width: Int) = UInt.Lit(target, width)
-    def asSInt(width: Int) = SInt.Lit(target, width)
-
-    // These were recently added to chisel2/3 but are not to be used internally
-    @deprecated("asUInt should be used over U", "gchisel")
-    def U() = UInt.Lit(target)
-    @deprecated("asSInt should be used over S", "gchisel")
-    def S() = SInt.Lit(target)
-    @deprecated("asUInt should be used over U", "gchisel")
-    def U(width: Int) = UInt.Lit(target, width)
-    @deprecated("asSInt should be used over S", "gchisel")
-    def S(width: Int) = SInt.Lit(target, width)
-  }
   implicit class fromIntToLiteral(val x: Int) extends AnyVal {
     def U: UInt = UInt(BigInt(x), Width())
     def S: SInt = SInt(BigInt(x), Width())
+
+    def asUInt() = UInt(x, Width())
+    def asSInt() = SInt(x, Width())
+    def asUInt(width: Int) = UInt(x, width)
+    def asSInt(width: Int) = SInt(x, width)
+  }
+  
+  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
+    def U: UInt = UInt(x, Width())
+    def S: SInt = SInt(x, Width())
   }
   implicit class fromStringToLiteral(val x: String) extends AnyVal {
     def U: UInt = UInt(x)
@@ -104,4 +104,7 @@ package object chisel3 {
     def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
     def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
   }
+
+  val INPUT = chisel3.core.Direction.Input
+  val OUTPUT = chisel3.core.Direction.Output
 }
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 73f58ed4..4a6b72e9 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -12,8 +12,8 @@ class DecoupledIO[+T <: Data](gen: T) extends Bundle
 {
   val ready = Input(Bool())
   val valid = Output(Bool())
-  val bits  = Output(gen.newType)
-  override protected def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
+  val bits  = Output(gen.cloneType)
+  override def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
 }
 
 object DecoupledIO {
@@ -30,7 +30,7 @@ object DecoupledIO {
       * @return    dat.
       */
     def enq(dat: T): T = {
-      target.valid := true.asBool
+      target.valid := Bool(true)
       target.bits := dat
       dat
     }
@@ -38,7 +38,7 @@ object DecoupledIO {
     /** Indicate no enqueue occurs.  Valid is set to false, and all bits are set to zero.
       */
     def noenq(): Unit = {
-      target.valid := false.asBool
+      target.valid := Bool(false)
       target.bits := target.bits.fromBits(0.asUInt)
     }
 
@@ -48,17 +48,17 @@ object DecoupledIO {
       * @return the data for this device,
       */
     def deq(): T = {
-      target.ready := true.asBool
+      target.ready := Bool(true)
       target.bits
     }
 
     /** Indicate no dequeue occurs. Ready is set to false
       */
     def nodeq(): Unit = {
-      target.ready := false.asBool
+      target.ready := Bool(false)
     }
   }
-  override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; }
+//  override def cloneType: this.type = { DeqIO(gen).asInstanceOf[this.type]; }
 }
 
 object EnqIO {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 7c0bc40e..f1608d5b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
 
 class ModuleWire extends Module {
   val io = IO(new SimpleIO)
-  val inc = Wire(Module(new PlusOne).io.newType)
+  val inc = Wire(Module(new PlusOne).io.cloneType)
   inc.in := io.in
   io.out := inc.out
 }
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index d5e9b998..fc6c5edc 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -12,29 +12,30 @@ class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
 
   val test = Wire(UInt(width=4))
-  assert(test === UInt.Lit(7))  // allow read references before assign references
+  assert(test === 7.U)  // allow read references before assign references
 
-  test := UInt.Lit(13)
-  assert(test === UInt.Lit(7))  // output value should be position-independent
+  test := 13.U
+  assert(test === 7.U)  // output value should be position-independent
 
-  test := UInt.Lit(7)
-  assert(test === UInt.Lit(7))  // this obviously should work
+  test := 7.U
+  assert(test === 7.U)  // this obviously should work
 
-  when(cnt.value === UInt.Lit(1)) {
+  when(cnt.value === 1.U) {
     stop()
   }
 }
 
 class ReassignmentTester() extends BasicTester {
-  val test = UInt.Lit(15)
-  test := UInt.Lit(7)
+  val test = 15.U
+  test := 7.U
 }
 
 class MultiAssignSpec extends ChiselFlatSpec {
   "The last assignment" should "be used when multiple assignments happen" in {
     assertTesterPasses{ new LastAssignTester }
   }
-  "Reassignments to non-wire types" should "be disallowed" in {
+  intercept[chisel3.internal.ChiselException] {
+//    "Reassignments to non-wire types" should "be disallowed" in {
     assertTesterFails{ new ReassignmentTester }
   }
 }
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 391dd7de..0caf6315 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,20 +16,20 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20))
-      reg.width.get should be (2)
+      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20))
+      reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
   }
 
   "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
     class RegUnknownWidthTester extends BasicTester {
-      val reg1 = Reg(next=UInt(width=3), init=UInt(20))
-      reg1.width.known should be (false)
-      val reg2 = Reg(init=UInt(20))
-      reg2.width.known should be (false)
-      val reg3 = Reg(next=UInt(width=3), init=UInt(width=5))
-      reg3.width.known should be (false)
+      val reg1 = Reg(next=Wire(UInt(width=3)), init=20.U)
+      DataMirror.widthOf(reg1).known should be (false)
+      val reg2 = Reg(init=20.U)
+      DataMirror.widthOf(reg2).known should be (false)
+      val reg3 = Reg(next=Wire(UInt(width=3)), init=5.U)
+      DataMirror.widthOf(reg3).known should be (false)
     }
     elaborate { new RegUnknownWidthTester }
   }
@@ -37,7 +37,7 @@ class RegSpec extends ChiselFlatSpec {
   "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
     class RegForcedWidthTester extends BasicTester {
       val reg2 = Reg(init=UInt(20, width=7))
-      reg2.width.get should be (7)
+      reg2.getWidth should be (7)
     }
     elaborate{ new RegForcedWidthTester }
   }
-- 
cgit v1.2.3


From 21a3c12b309df88cdb8114c01ef35b044282d647 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 19 Jul 2016 16:16:35 -0700
Subject: Fix LitBinding and MultiAssign tests.

---
 src/test/scala/chiselTests/MultiAssign.scala | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index fc6c5edc..2399267e 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -34,8 +34,12 @@ class MultiAssignSpec extends ChiselFlatSpec {
   "The last assignment" should "be used when multiple assignments happen" in {
     assertTesterPasses{ new LastAssignTester }
   }
-  intercept[chisel3.internal.ChiselException] {
-//    "Reassignments to non-wire types" should "be disallowed" in {
-    assertTesterFails{ new ReassignmentTester }
+}
+
+class IllegalAssignSpec extends ChiselFlatSpec {
+  "Reassignments to non-wire types" should "be disallowed" in {
+    intercept[chisel3.internal.ChiselException] {
+      assertTesterFails{ new ReassignmentTester }
+    }
   }
 }
-- 
cgit v1.2.3


From 28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 13:28:15 -0700
Subject: Compile ok. Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)

---
 src/main/scala/chisel3/package.scala        |  8 +++++++-
 src/main/scala/chisel3/util/BitPat.scala    |  4 ++--
 src/main/scala/chisel3/util/Decoupled.scala |  6 +++++-
 src/main/scala/chisel3/util/Valid.scala     |  6 +++++-
 src/test/scala/chiselTests/GCD.scala        | 14 +++++++-------
 src/test/scala/chiselTests/Module.scala     |  2 +-
 src/test/scala/chiselTests/Risc.scala       | 12 ++++++------
 7 files changed, 33 insertions(+), 19 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 71ec0e92..86fce6a2 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,9 +1,10 @@
+// See LICENSE for license details.
+
 package object chisel3 {
   import scala.language.experimental.macros
 
   import internal.firrtl.Width
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-
   import util.BitPat
 
 
@@ -87,6 +88,11 @@ package object chisel3 {
   implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
     def U: UInt = UInt(x, Width())
     def S: SInt = SInt(x, Width())
+
+    def asUInt() = UInt(x, Width())
+    def asSInt() = SInt(x, Width())
+    def asUInt(width: Int) = UInt(x, width)
+    def asSInt(width: Int) = SInt(x, width)
   }
   implicit class fromStringToLiteral(val x: String) extends AnyVal {
     def U: UInt = UInt(x)
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 9eb5cf67..3ae192a2 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -75,7 +75,7 @@ object BitPat {
 // TODO: Break out of Core? (this doesn't involve FIRRTL generation)
 /** Bit patterns are literals with masks, used to represent values with don't
   * cares. Equality comparisons will ignore don't care bits (for example,
-  * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)).
+  * BitPat(0b10?1) === 0b1001.asUInt and 0b1011.asUInt.
   */
 sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
   def getWidth: Int = width
@@ -83,7 +83,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) {
   def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
   def != (that: UInt): Bool = macro SourceInfoTransform.thatArg
 
-  def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask))
+  def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = value.asUInt === (that & mask.asUInt)
   def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that)
   def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that
 }
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 4a6b72e9..fb1ee6b9 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -58,7 +58,11 @@ object DecoupledIO {
       target.ready := Bool(false)
     }
   }
-//  override def cloneType: this.type = { DeqIO(gen).asInstanceOf[this.type]; }
+//  override def cloneType: this.type = {
+//    val clone = DeqIO(gen).asInstanceOf[this.type]
+//    clone.unBind()
+//    clone
+//  }
 }
 
 object EnqIO {
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 4078a76a..5641f0f2 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -13,7 +13,11 @@ class Valid[+T <: Data](gen: T) extends Bundle
   val valid = Output(Bool())
   val bits  = Output(gen.cloneType)
   def fire(dummy: Int = 0): Bool = valid
-  override def cloneType: this.type = Valid(gen).asInstanceOf[this.type]
+  override def cloneType: this.type = {
+    val clone = Valid(gen).asInstanceOf[this.type]
+    clone.unBind()
+    clone
+  }
 }
 
 /** Adds a valid protocol to any interface */
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index a8b907af..7c04ae00 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -21,18 +21,18 @@ class GCD extends Module {
   .otherwise     { y := y -% x }
   when (io.e) { x := io.a; y := io.b }
   io.z := x
-  io.v := y === UInt(0)
+  io.v := y === 0.U
 }
 
 class GCDTester(a: Int, b: Int, z: Int) extends BasicTester {
   val dut = Module(new GCD)
-  val first = Reg(init=Bool(true))
-  dut.io.a := UInt(a)
-  dut.io.b := UInt(b)
+  val first = Reg(init=true.B)
+  dut.io.a := a.U
+  dut.io.b := b.U
   dut.io.e := first
-  when(first) { first := Bool(false) }
-  when(dut.io.v) {
-    assert(dut.io.z === UInt(z))
+  when(first) { first := false.B }
+  when(!first && dut.io.v) {
+    assert(dut.io.z === z.U)
     stop()
   }
 }
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index f1608d5b..857aeda3 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -11,7 +11,7 @@ class SimpleIO extends Bundle {
 
 class PlusOne extends Module {
   val io = IO(new SimpleIO)
-  io.out := io.in + UInt(1)
+  io.out := io.in + 1.asUInt
 }
 
 class ModuleVec(val n: Int) extends Module {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index fafec95a..c110d37e 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -27,13 +27,13 @@ class Risc extends Module {
   val rai  = inst(15, 8)
   val rbi  = inst( 7, 0)
 
-  val ra = Mux(rai === Bits(0), Bits(0), file(rai))
-  val rb = Mux(rbi === Bits(0), Bits(0), file(rbi))
+  val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
+  val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
   val rc = Wire(Bits(width = 32))
 
   io.valid := Bool(false)
-  io.out   := Bits(0)
-  rc       := Bits(0)
+  io.out   := 0.asUInt()
+  rc       := 0.asUInt()
 
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
@@ -45,12 +45,12 @@ class Risc extends Module {
       is(imm_op) { rc := (rai << 8) | rbi }
     }
     io.out := rc
-    when (rci === UInt(255)) {
+    when (rci === 255.asUInt()) {
       io.valid := Bool(true)
     } .otherwise {
       file(rci) := rc
     }
-    pc := pc +% UInt(1)
+    pc := pc +% 1.asUInt()
   }
 }
 
-- 
cgit v1.2.3


From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 14:49:35 -0700
Subject: Distinguish between ?Int.Lit and ?Int.width

---
 src/main/scala/chisel3/package.scala               |  2 +-
 src/main/scala/chisel3/util/Arbiter.scala          | 12 ++++----
 src/main/scala/chisel3/util/CircuitMath.scala      |  4 +--
 src/main/scala/chisel3/util/Counter.scala          | 10 +++---
 src/main/scala/chisel3/util/Decoupled.scala        |  4 +--
 .../scala/chisel3/util/ImplicitConversions.scala   |  2 +-
 src/main/scala/chisel3/util/OneHot.scala           |  4 +--
 src/test/scala/chiselTests/Assert.scala            |  4 +--
 src/test/scala/chiselTests/BlackBox.scala          | 30 +++++++++---------
 src/test/scala/chiselTests/BundleWire.scala        |  8 ++---
 src/test/scala/chiselTests/ComplexAssign.scala     | 12 ++++----
 src/test/scala/chiselTests/Counter.scala           |  8 ++---
 src/test/scala/chiselTests/Decoder.scala           |  4 +--
 src/test/scala/chiselTests/Direction.scala         |  8 ++---
 .../scala/chiselTests/EnableShiftRegister.scala    |  4 +--
 src/test/scala/chiselTests/GCD.scala               |  6 ++--
 src/test/scala/chiselTests/LFSR16.scala            |  2 +-
 src/test/scala/chiselTests/MemorySearch.scala      | 10 +++---
 src/test/scala/chiselTests/Module.scala            |  8 ++---
 src/test/scala/chiselTests/MulLookup.scala         | 12 ++++----
 src/test/scala/chiselTests/Padding.scala           |  6 ++--
 src/test/scala/chiselTests/Printf.scala            |  6 ++--
 src/test/scala/chiselTests/Reg.scala               |  2 +-
 src/test/scala/chiselTests/Risc.scala              |  4 +--
 src/test/scala/chiselTests/SIntOps.scala           | 26 ++++++++--------
 src/test/scala/chiselTests/Stack.scala             | 16 +++++-----
 src/test/scala/chiselTests/Tbl.scala               | 10 +++---
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  6 ++--
 src/test/scala/chiselTests/UIntOps.scala           | 24 +++++++--------
 src/test/scala/chiselTests/Vec.scala               |  6 ++--
 src/test/scala/chiselTests/When.scala              | 36 +++++++++++-----------
 31 files changed, 148 insertions(+), 148 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 86fce6a2..e43434c0 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -95,7 +95,7 @@ package object chisel3 {
     def asSInt(width: Int) = SInt(x, width)
   }
   implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt(x)
+    def U: UInt = UInt.Lit(x)
   }
   implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
     def B: Bool = Bool(x)
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index a5397682..44cc88b6 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -36,7 +36,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
   if (count > 1) {
     val lockCount = Counter(count)
     val lockIdx = Reg(UInt())
-    val locked = lockCount.value =/= UInt(0)
+    val locked = lockCount.value =/= UInt.Lit(0)
     val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
 
     when (io.out.firing && wantsLock) {
@@ -46,7 +46,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 
     when (locked) { io.chosen := lockIdx }
     for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
-      in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
+      in.ready := Mux(locked, lockIdx === UInt.Lit(i), g) && io.out.ready
   } else {
     for ((in, g) <- io.in zip grant)
       in.ready := g && io.out.ready
@@ -66,9 +66,9 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
 
   override lazy val choice = Wire(init=UInt(n-1))
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
+    when (io.in(i).valid) { choice := UInt.Lit(i) }
   for (i <- n-1 to 1 by -1)
-    when (validMask(i)) { choice := UInt(i) }
+    when (validMask(i)) { choice := UInt.Lit(i) }
 }
 
 class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
@@ -77,7 +77,7 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T
 
   override lazy val choice = Wire(init=UInt(n-1))
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
+    when (io.in(i).valid) { choice := UInt.Lit(i) }
 }
 
 /** Hardware module that is used to sequence n producers into 1 consumer.
@@ -107,7 +107,7 @@ class Arbiter[T <: Data](gen: T, n: Int) extends Module {
   io.out.bits := io.in(n-1).bits
   for (i <- n-2 to 0 by -1) {
     when (io.in(i).valid) {
-      io.chosen := UInt(i)
+      io.chosen := UInt.Lit(i)
       io.out.bits := io.in(i).bits
     }
   }
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 1174c71c..5e93b009 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -11,12 +11,12 @@ import chisel3._
   * An alternative interpretation is it computes the minimum number of bits needed to represent x
   * @example
   * {{{ data_out := Log2(data_in) }}}
-  * @note Truncation is used so Log2(UInt(12412)) = 13*/
+  * @note Truncation is used so Log2(UInt.Lit(12412)) = 13*/
 object Log2 {
   /** Compute the Log2 on the least significant n bits of x */
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
-      UInt(0)
+      UInt.Lit(0)
     } else if (width == 2) {
       x(1)
     } else {
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 40615769..05d8fba8 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -10,17 +10,17 @@ import chisel3._
   */
 class Counter(val n: Int) {
   require(n >= 0)
-  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
+  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt.Lit(0)
   /** Increment the counter, returning whether the counter currently is at the
     * maximum and will wrap. The incremented value is registered and will be
     * visible on the next cycle.
     */
   def inc(): Bool = {
     if (n > 1) {
-      val wrap = value === UInt(n-1)
-      value := value + UInt(1)
+      val wrap = value === UInt.Lit(n-1)
+      value := value + UInt.Lit(1)
       if (!isPow2(n)) {
-        when (wrap) { value := UInt(0) }
+        when (wrap) { value := UInt.Lit(0) }
       }
       wrap
     } else {
@@ -33,7 +33,7 @@ class Counter(val n: Int) {
   * Example Usage:
   * {{{ val countOn = Bool(true) // increment counter every clock cycle
   * val myCounter = Counter(countOn, n)
-  * when ( myCounter.value === UInt(3) ) { ... } }}}*/
+  * when ( myCounter.value === UInt.Lit(3) ) { ... } }}}*/
 object Counter
 {
   def apply(n: Int): Counter = new Counter(n)
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index fb1ee6b9..5958c744 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -153,9 +153,9 @@ extends Module(override_reset=override_reset) {
   } else {
     io.count := Mux(ptr_match,
                     Mux(maybe_full,
-                      UInt(entries), UInt(0)),
+                      UInt.Lit(entries), UInt.Lit(0)),
                     Mux(deq_ptr.value > enq_ptr.value,
-                      UInt(entries) + ptr_diff, ptr_diff))
+                      UInt.Lit(entries) + ptr_diff, ptr_diff))
   }
 }
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 4d816a19..3a9089c5 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,6 @@ package chisel3.util
 import chisel3._
 
 object ImplicitConversions {
-  implicit def intToUInt(x: Int): UInt = UInt(x)
+  implicit def intToUInt(x: Int): UInt = UInt.Lit(x)
   implicit def booleanToBool(x: Boolean): Bool = Bool(x)
 }
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 820c72d6..8a5caf44 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -41,9 +41,9 @@ object UIntToOH
 {
   def apply(in: UInt, width: Int = -1): UInt =
     if (width == -1) {
-      UInt(1) << in
+      UInt.Lit(1) << in
     } else {
-      (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
+      (UInt.Lit(1) << in(log2Up(width)-1,0))(width-1,0)
     }
 }
 
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index efc2e1e7..bf3c8092 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester {
 
 class PipelinedResetModule extends Module {
   val io = IO(new Bundle { })
-  val a = Reg(init = UInt(0xbeef))
-  val b = Reg(init = UInt(0xbeef))
+  val a = Reg(init = UInt.Lit(0xbeef))
+  val b = Reg(init = UInt.Lit(0xbeef))
   assert(a === b)
 }
 
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index c1154883..9b43f0ef 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -35,11 +35,11 @@ class BlackBoxTester extends BasicTester {
   val blackBoxPos = Module(new BlackBoxInverter)
   val blackBoxNeg = Module(new BlackBoxInverter)
 
-  blackBoxPos.io.in := UInt(1)
-  blackBoxNeg.io.in := UInt(0)
+  blackBoxPos.io.in := UInt.Lit(1)
+  blackBoxNeg.io.in := UInt.Lit(0)
 
-  assert(blackBoxNeg.io.out === UInt(1))
-  assert(blackBoxPos.io.out === UInt(0))
+  assert(blackBoxNeg.io.out === UInt.Lit(1))
+  assert(blackBoxPos.io.out === UInt.Lit(0))
   stop()
 }
 
@@ -54,15 +54,15 @@ class MultiBlackBoxTester extends BasicTester {
   val blackBoxPassPos = Module(new BlackBoxPassthrough)
   val blackBoxPassNeg = Module(new BlackBoxPassthrough)
 
-  blackBoxInvPos.io.in := UInt(1)
-  blackBoxInvNeg.io.in := UInt(0)
-  blackBoxPassPos.io.in := UInt(1)
-  blackBoxPassNeg.io.in := UInt(0)
+  blackBoxInvPos.io.in := UInt.Lit(1)
+  blackBoxInvNeg.io.in := UInt.Lit(0)
+  blackBoxPassPos.io.in := UInt.Lit(1)
+  blackBoxPassNeg.io.in := UInt.Lit(0)
 
-  assert(blackBoxInvNeg.io.out === UInt(1))
-  assert(blackBoxInvPos.io.out === UInt(0))
-  assert(blackBoxPassNeg.io.out === UInt(0))
-  assert(blackBoxPassPos.io.out === UInt(1))
+  assert(blackBoxInvNeg.io.out === UInt.Lit(1))
+  assert(blackBoxInvPos.io.out === UInt.Lit(0))
+  assert(blackBoxPassNeg.io.out === UInt.Lit(0))
+  assert(blackBoxPassPos.io.out === UInt.Lit(1))
   stop()
 }
 
@@ -77,7 +77,7 @@ class BlackBoxWithClockTester extends BasicTester {
   blackBox.io.in := impetus
   model := impetus
 
-  when(cycles > UInt(0)) {
+  when(cycles > UInt.Lit(0)) {
     assert(blackBox.io.out === model)
   }
   when(end) { stop() }
@@ -98,8 +98,8 @@ class BlackBoxWithParamsTester extends BasicTester {
 
   val (cycles, end) = Counter(Bool(true), 4)
 
-  assert(blackBoxOne.io.out  === UInt(1))
-  assert(blackBoxFour.io.out === UInt(4))
+  assert(blackBoxOne.io.out  === UInt.Lit(1))
+  assert(blackBoxFour.io.out === UInt.Lit(4))
 
   when(end) { stop() }
 }
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 029407dd..2f6322b1 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -25,11 +25,11 @@ class BundleWire(n: Int) extends Module {
 
 class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new BundleWire(n))
-  dut.io.in.x := UInt(x)
-  dut.io.in.y := UInt(y)
+  dut.io.in.x := UInt.Lit(x)
+  dut.io.in.y := UInt.Lit(y)
   for (elt <- dut.io.outs) {
-    assert(elt.x === UInt(x))
-    assert(elt.y === UInt(y))
+    assert(elt.x === UInt.Lit(x))
+    assert(elt.y === UInt.Lit(y))
   }
   stop()
 }
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index e5d1fbea..638ef9b7 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -26,19 +26,19 @@ class ComplexAssign(w: Int) extends Module {
     io.out.re := tmp.re
     io.out.im := tmp.im
   } .otherwise {
-    io.out.re := UInt(0)
-    io.out.im := UInt(0)
+    io.out.re := UInt.Lit(0)
+    io.out.im := UInt.Lit(0)
   }
 }
 
 class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), enList.size)
   val dut = Module(new ComplexAssign(32))
-  dut.io.in.re := UInt(re)
-  dut.io.in.im := UInt(im)
+  dut.io.in.re := UInt.Lit(re)
+  dut.io.in.im := UInt.Lit(im)
   dut.io.e := Vec(enList.map(Bool(_)))(cnt)
-  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0))
-  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0))
+  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt.Lit(0))
+  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt.Lit(0))
   assert(re_correct && im_correct)
   when(wrap) {
     stop()
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 69d8a44a..af2fa550 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -12,20 +12,20 @@ import chisel3.util._
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
   when(Bool(true)) { cnt.inc() }
-  when(cnt.value === UInt(max-1)) {
+  when(cnt.value === UInt.Lit(max-1)) {
     stop()
   }
 }
 
 class EnableTester(seed: Int) extends BasicTester {
-  val ens = Reg(init = UInt(seed))
+  val ens = Reg(init = UInt.Lit(seed))
   ens := ens >> 1
 
   val (cntEnVal, _) = Counter(ens(0), 32)
   val (_, done) = Counter(Bool(true), 33)
 
   when(done) {
-    assert(cntEnVal === UInt(popCount(seed)))
+    assert(cntEnVal === UInt.Lit(popCount(seed)))
     stop()
   }
 }
@@ -33,7 +33,7 @@ class EnableTester(seed: Int) extends BasicTester {
 class WrapTester(max: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), max)
   when(wrap) {
-    assert(cnt === UInt(max - 1))
+    assert(cnt === UInt.Lit(max - 1))
     stop()
   }
 }
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 4a872245..ee892fc5 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = IO(new Bundle {
-    val inst  = Input(UInt(32))
+    val inst  = Input(UInt.width(32))
     val matched = Output(Bool())
   })
   io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
@@ -24,7 +24,7 @@ class DecoderTester(pairs: List[(String, String)]) extends BasicTester {
   val dut = Module(new Decoder(bitpats))
   dut.io.inst := Vec(insts.map(UInt(_)))(cnt)
   when(!dut.io.matched) {
-    assert(cnt === UInt(0))
+    assert(cnt === UInt.Lit(0))
     stop()
   }
   when(wrap) {
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 682103f7..e22e120b 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -9,17 +9,17 @@ import chisel3.testers.BasicTester
 
 class DirectionHaver extends Module {
   val io = IO(new Bundle {
-    val in = Input(UInt(32))
-    val out = Output(UInt(32))
+    val in = Input(UInt.width(32))
+    val out = Output(UInt.width(32))
   })
 }
 
 class GoodDirection extends DirectionHaver {
-  io.out := UInt(0)
+  io.out := UInt.Lit(0)
 }
 
 class BadDirection extends DirectionHaver {
-  io.in := UInt(0)
+  io.in := UInt.Lit(0)
 }
 
 class DirectionSpec extends ChiselPropSpec {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 26af944f..5f3e0dd1 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -6,9 +6,9 @@ import chisel3.testers.BasicTester
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
-    val in    = Input(UInt(4))
+    val in    = Input(UInt.width(4))
     val shift = Input(Bool())
-    val out   = Output(UInt(4))
+    val out   = Output(UInt.width(4))
   })
   val r0 = Reg(init = UInt(0, 4))
   val r1 = Reg(init = UInt(0, 4))
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index 7c04ae00..d0d945b7 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -9,10 +9,10 @@ import org.scalatest.prop._
 
 class GCD extends Module {
   val io = IO(new Bundle {
-    val a  = Input(UInt(32))
-    val b  = Input(UInt(32))
+    val a  = Input(UInt.width(32))
+    val b  = Input(UInt.width(32))
     val e  = Input(Bool())
-    val z  = Output(UInt(32))
+    val z  = Output(UInt.width(32))
     val v  = Output(Bool())
   })
   val x = Reg(UInt(width = 32))
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index 2d5e7f3e..b13b67e3 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -9,7 +9,7 @@ import chisel3.util._
 class LFSR16 extends Module {
   val io = IO(new Bundle {
     val inc = Input(Bool())
-    val out = Output(UInt(16))
+    val out = Output(UInt.width(16))
   })
   val res = Reg(init = UInt(1, 16))
   when (io.inc) {
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 770be326..e4063532 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -7,21 +7,21 @@ import chisel3.testers.BasicTester
 
 class MemorySearch extends Module {
   val io = IO(new Bundle {
-    val target  = Input(UInt(4))
+    val target  = Input(UInt.width(4))
     val en      = Input(Bool())
     val done    = Output(Bool())
-    val address = Output(UInt(3))
+    val address = Output(UInt.width(3))
   })
   val vals  = Array(0, 4, 15, 14, 2, 5, 13)
   val index = Reg(init = UInt(0, width = 3))
   val elts  = Vec(vals.map(UInt(_,4)))
   // val elts  = Mem(UInt(width = 32), 8) TODO ????
   val elt  = elts(index)
-  val end  = !io.en && ((elt === io.target) || (index === UInt(7)))
+  val end  = !io.en && ((elt === io.target) || (index === UInt.Lit(7)))
   when (io.en) {
-    index := UInt(0)
+    index := UInt.Lit(0)
   } .elsewhen (!end) {
-    index := index +% UInt(1)
+    index := index +% UInt.Lit(1)
   }
   io.done    := end
   io.address := index
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 857aeda3..59451a2b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -5,8 +5,8 @@ package chiselTests
 import chisel3._
 
 class SimpleIO extends Bundle {
-  val in  = Input(UInt(32))
-  val out = Output(UInt(32))
+  val in  = Input(UInt.width(32))
+  val out = Output(UInt.width(32))
 }
 
 class PlusOne extends Module {
@@ -16,8 +16,8 @@ class PlusOne extends Module {
 
 class ModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Input(Vec(n, UInt(32)))
-    val outs = Output(Vec(n, UInt(32)))
+    val ins  = Input(Vec(n, UInt.Lit(32)))
+    val outs = Output(Vec(n, UInt.Lit(32)))
   })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index b22b2820..16a29104 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -9,9 +9,9 @@ import chisel3.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
-    val x   = Input(UInt(w))
-    val y   = Input(UInt(w))
-    val z   = Output(UInt(2 * w))
+    val x   = Input(UInt.width(w))
+    val y   = Input(UInt.width(w))
+    val z   = Output(UInt.width(2 * w))
   })
   val tbl = Vec(
     for {
@@ -24,9 +24,9 @@ class MulLookup(val w: Int) extends Module {
 
 class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new MulLookup(w))
-  dut.io.x := UInt(x)
-  dut.io.y := UInt(y)
-  assert(dut.io.z === UInt(x * y))
+  dut.io.x := UInt.Lit(x)
+  dut.io.y := UInt.Lit(y)
+  assert(dut.io.z === UInt.Lit(x * y))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 6c92e87b..42df6802 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -6,9 +6,9 @@ import chisel3._
 
 class Padder extends Module {
   val io = IO(new Bundle {
-    val a   = Input(UInt(4))
-    val asp = Output(SInt(8))
-    val aup = Output(UInt(8))
+    val a   = Input(UInt.width(4))
+    val asp = Output(SInt.width(8))
+    val aup = Output(UInt.width(8))
   })
   io.asp := io.a.asSInt
   io.aup := io.a.asUInt
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index c872fde4..92b6fee1 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
-  val x = UInt(254)
+  val x = UInt.Lit(254)
   printf("x=%x", x)
   stop()
 }
@@ -18,8 +18,8 @@ class ASCIIPrintfTester() extends BasicTester {
 }
 
 class MultiPrintfTester() extends BasicTester {
-  val x = UInt(254)
-  val y = UInt(255)
+  val x = UInt.Lit(254)
+  val y = UInt.Lit(255)
   printf("x=%x y=%x", x, y)
   stop()
 }
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 0caf6315..5d4bd18d 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20))
+      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt.Lit(20))
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index c110d37e..156e5df2 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 class Risc extends Module {
   val io = IO(new Bundle {
     val isWr   = Input(Bool())
-    val wrAddr = Input(UInt(8))
+    val wrAddr = Input(UInt.width(8))
     val wrData = Input(Bits(32))
     val boot   = Input(Bool())
     val valid  = Output(Bool())
@@ -38,7 +38,7 @@ class Risc extends Module {
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
   } .elsewhen (io.boot) {
-    pc := UInt(0)
+    pc := UInt.Lit(0)
   } .otherwise {
     switch(op) {
       is(add_op) { rc := ra +% rb }
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index a98edf9b..d827c096 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -7,22 +7,22 @@ import chisel3.testers.BasicTester
 
 class SIntOps extends Module {
   val io = IO(new Bundle {
-    val a = Input(SInt(16))
-    val b = Input(SInt(16))
-    val addout = Output(SInt(16))
-    val subout = Output(SInt(16))
-    val timesout = Output(SInt(16))
-    val divout = Output(SInt(16))
-    val modout = Output(SInt(16))
-    val lshiftout = Output(SInt(16))
-    val rshiftout = Output(SInt(16))
+    val a = Input(SInt.width(16))
+    val b = Input(SInt.width(16))
+    val addout = Output(SInt.width(16))
+    val subout = Output(SInt.width(16))
+    val timesout = Output(SInt.width(16))
+    val divout = Output(SInt.width(16))
+    val modout = Output(SInt.width(16))
+    val lshiftout = Output(SInt.width(16))
+    val rshiftout = Output(SInt.width(16))
     val lessout = Output(Bool())
     val greatout = Output(Bool())
     val eqout = Output(Bool())
     val noteqout = Output(Bool())
     val lesseqout = Output(Bool())
     val greateqout = Output(Bool())
-    val negout = Output(SInt(16))
+    val negout = Output(SInt.width(16))
   })
 
   val a = io.a
@@ -32,9 +32,9 @@ class SIntOps extends Module {
   io.subout := a -% b
   // TODO:
   //io.timesout := (a * b)(15, 0)
-  //io.divout := a / Mux(b === SInt(0), SInt(1), b)
+  //io.divout := a / Mux(b === SInt.Lit(0), SInt.Lit(1), b)
   //io.divout := (a / b)(15, 0)
-  //io.modout := SInt(0)
+  //io.modout := SInt.Lit(0)
   //io.lshiftout := (a << 12)(15, 0) //  (a << ub(3, 0))(15, 0).toSInt
   io.rshiftout := (a >> 8) // (a >> ub).toSInt
   io.lessout := a < b
@@ -44,7 +44,7 @@ class SIntOps extends Module {
   io.lesseqout := a <= b
   io.greateqout := a >= b
   // io.negout := -a(15, 0).toSInt
-  io.negout := (SInt(0) -% a)
+  io.negout := (SInt.Lit(0) -% a)
 }
 
 /*
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 683c5224..440228c9 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -12,8 +12,8 @@ class ChiselStack(val depth: Int) extends Module {
     val push    = Input(Bool())
     val pop     = Input(Bool())
     val en      = Input(Bool())
-    val dataIn  = Input(UInt(32))
-    val dataOut = Output(UInt(32))
+    val dataIn  = Input(UInt.width(32))
+    val dataOut = Output(UInt.width(32))
   })
 
   val stack_mem = Mem(depth, UInt(width = 32))
@@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module {
   val out       = Reg(init = UInt(0, width = 32))
 
   when (io.en) {
-    when(io.push && (sp < UInt(depth))) {
+    when(io.push && (sp < UInt.Lit(depth))) {
       stack_mem(sp) := io.dataIn
-      sp := sp +% UInt(1)
-    } .elsewhen(io.pop && (sp > UInt(0))) {
-      sp := sp -% UInt(1)
+      sp := sp +% UInt.Lit(1)
+    } .elsewhen(io.pop && (sp > UInt.Lit(0))) {
+      sp := sp -% UInt.Lit(1)
     }
-    when (sp > UInt(0)) {
-      out := stack_mem(sp -% UInt(1))
+    when (sp > UInt.Lit(0)) {
+      out := stack_mem(sp -% UInt.Lit(1))
     }
   }
   io.dataOut := out
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 6ebe0875..75c4278f 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -14,8 +14,8 @@ class Tbl(w: Int, n: Int) extends Module {
     val wi  = Input(UInt(log2Up(n)))
     val ri  = Input(UInt(log2Up(n)))
     val we  = Input(Bool())
-    val  d  = Input(UInt(w))
-    val  o  = Output(UInt(w))
+    val  d  = Input(UInt.width(w))
+    val  o  = Output(UInt.width(w))
   })
   val m = Mem(n, UInt(width = w))
   io.o := m(io.ri)
@@ -32,13 +32,13 @@ class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends Basi
   val dut = Module(new Tbl(w, n))
   val vvalues = Vec(values.map(UInt(_)))
   val vidxs = Vec(idxs.map(UInt(_)))
-  val prev_idx = vidxs(cnt - UInt(1))
-  val prev_value = vvalues(cnt - UInt(1))
+  val prev_idx = vidxs(cnt - UInt.Lit(1))
+  val prev_value = vvalues(cnt - UInt.Lit(1))
   dut.io.wi := vidxs(cnt)
   dut.io.ri := prev_idx
   dut.io.we := Bool(true) //TODO enSequence
   dut.io.d := vvalues(cnt)
-  when (cnt > UInt(0)) {
+  when (cnt > UInt.Lit(0)) {
     when (prev_idx === vidxs(cnt)) {
       assert(dut.io.o === vvalues(cnt))
     } .otherwise {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 2f3e9368..4c1e41c8 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -20,17 +20,17 @@ class FinishTester extends BasicTester {
     stop()
   }
 
-  val test_wire = Wire(UInt(1, width = test_wire_width))
+  val test_wire = UInt(1, width = test_wire_width)
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
-  assert(test_wire === UInt(test_wire_override_value))
+  assert(test_wire === UInt.Lit(test_wire_override_value))
 
   /** In finish we use last connect semantics to alter the test_wire in the circuit
     * with a new value
     */
   override def finish(): Unit = {
-    test_wire := UInt(test_wire_override_value)
+    test_wire := UInt.Lit(test_wire_override_value)
   }
 }
 
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index ca83ee1d..812f822d 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -8,15 +8,15 @@ import chisel3.testers.BasicTester
 
 class UIntOps extends Module {
   val io = IO(new Bundle {
-    val a = Input(UInt(16))
-    val b = Input(UInt(16))
-    val addout = Output(UInt(16))
-    val subout = Output(UInt(16))
-    val timesout = Output(UInt(16))
-    val divout = Output(UInt(16))
-    val modout = Output(UInt(16))
-    val lshiftout = Output(UInt(16))
-    val rshiftout = Output(UInt(16))
+    val a = Input(UInt.width(16))
+    val b = Input(UInt.width(16))
+    val addout = Output(UInt.width(16))
+    val subout = Output(UInt.width(16))
+    val timesout = Output(UInt.width(16))
+    val divout = Output(UInt.width(16))
+    val modout = Output(UInt.width(16))
+    val lshiftout = Output(UInt.width(16))
+    val rshiftout = Output(UInt.width(16))
     val lessout = Output(Bool())
     val greatout = Output(Bool())
     val eqout = Output(Bool())
@@ -31,10 +31,10 @@ class UIntOps extends Module {
   io.addout := a +% b
   io.subout := a -% b
   io.timesout := (a * b)(15, 0)
-  io.divout := a / Mux(b === UInt(0), UInt(1), b)
+  io.divout := a / Mux(b === UInt.Lit(0), UInt.Lit(1), b)
   // io.modout := a % b
   // TODO:
-  io.modout := UInt(0)
+  io.modout := UInt.Lit(0)
   io.lshiftout := (a << b(3, 0))(15, 0)
   io.rshiftout := a >> b
   io.lessout := a < b
@@ -78,7 +78,7 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) {
 
 class GoodBoolConversion extends Module {
   val io = IO(new Bundle {
-    val u = Input(UInt(1))
+    val u = Input(UInt.width(1))
     val b = Output(Bool())
   })
   io.b := io.u.toBool
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index b90c1f09..cdb1ba8d 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
   for ((a,b) <- v.zip(values)) {
-    assert(a === UInt(b))
+    assert(a === UInt.Lit(b))
   }
   stop()
 }
@@ -34,8 +34,8 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
   val shifter = Reg(Vec(n, UInt(width = log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
-  when (cnt >= UInt(n)) {
-    val expected = cnt - UInt(n)
+  when (cnt >= UInt.Lit(n)) {
+    val expected = cnt - UInt.Lit(n)
     assert(shifter(0) === expected)
   }
   when (wrap) {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 5f3d3e61..58aa43e7 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -13,19 +13,19 @@ class WhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt(width=3))
-  when(cnt.value === UInt(0)) {
-    out := UInt(1)
-  } .elsewhen (cnt.value === UInt(1)) {
-    out := UInt(2)
-  } .elsewhen (cnt.value === UInt(2)) {
-    out := UInt(3)
+  when(cnt.value === UInt.Lit(0)) {
+    out := UInt.Lit(1)
+  } .elsewhen (cnt.value === UInt.Lit(1)) {
+    out := UInt.Lit(2)
+  } .elsewhen (cnt.value === UInt.Lit(2)) {
+    out := UInt.Lit(3)
   } .otherwise {
-    out := UInt(0)
+    out := UInt.Lit(0)
   }
 
-  assert(out === cnt.value + UInt(1))
+  assert(out === cnt.value + UInt.Lit(1))
 
-  when(cnt.value === UInt(3)) {
+  when(cnt.value === UInt.Lit(3)) {
     stop()
   }
 }
@@ -35,19 +35,19 @@ class OverlappedWhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt(width=3))
-  when(cnt.value <= UInt(0)) {
-    out := UInt(1)
-  } .elsewhen (cnt.value <= UInt(1)) {
-    out := UInt(2)
-  } .elsewhen (cnt.value <= UInt(2)) {
-    out := UInt(3)
+  when(cnt.value <= UInt.Lit(0)) {
+    out := UInt.Lit(1)
+  } .elsewhen (cnt.value <= UInt.Lit(1)) {
+    out := UInt.Lit(2)
+  } .elsewhen (cnt.value <= UInt.Lit(2)) {
+    out := UInt.Lit(3)
   } .otherwise {
-    out := UInt(0)
+    out := UInt.Lit(0)
   }
 
-  assert(out === cnt.value + UInt(1))
+  assert(out === cnt.value + UInt.Lit(1))
 
-  when(cnt.value === UInt(3)) {
+  when(cnt.value === UInt.Lit(3)) {
     stop()
   }
 }
-- 
cgit v1.2.3


From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 17:08:55 -0700
Subject: More literal/width rangling.

---
 src/main/scala/chisel3/util/Arbiter.scala       | 10 +++++-----
 src/main/scala/chisel3/util/Bitwise.scala       |  2 +-
 src/main/scala/chisel3/util/CircuitMath.scala   |  2 +-
 src/main/scala/chisel3/util/Decoupled.scala     |  2 +-
 src/main/scala/chisel3/util/OneHot.scala        |  2 +-
 src/test/scala/chiselTests/BitwiseOps.scala     |  8 ++++----
 src/test/scala/chiselTests/BundleWire.scala     |  4 ++--
 src/test/scala/chiselTests/ComplexAssign.scala  |  6 +++---
 src/test/scala/chiselTests/DeqIOSpec.scala      |  2 +-
 src/test/scala/chiselTests/GCD.scala            |  4 ++--
 src/test/scala/chiselTests/MultiAssign.scala    |  2 +-
 src/test/scala/chiselTests/Reg.scala            |  6 +++---
 src/test/scala/chiselTests/Risc.scala           | 12 ++++++------
 src/test/scala/chiselTests/Stack.scala          |  2 +-
 src/test/scala/chiselTests/Tbl.scala            | 10 +++++-----
 src/test/scala/chiselTests/UIntOps.scala        |  2 +-
 src/test/scala/chiselTests/Vec.scala            |  8 ++++----
 src/test/scala/chiselTests/VectorPacketIO.scala |  2 +-
 src/test/scala/chiselTests/When.scala           |  4 ++--
 19 files changed, 45 insertions(+), 45 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 44cc88b6..0ece3a0a 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -11,7 +11,7 @@ import chisel3._
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
   val in  = Flipped(Vec(n, DecoupledIO(gen)))
   val out = DecoupledIO(gen)
-  val chosen = Output(UInt(log2Up(n)))
+  val chosen = Output(UInt.width(log2Up(n)))
 }
 
 /** Arbiter Control determining which producer has access */
@@ -56,7 +56,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   lazy val lastGrant = RegEnable(io.chosen, io.out.firing)
-  lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
+  lazy val grantMask = (0 until n).map(UInt.Lit(_) > lastGrant)
   lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
 
   override def grant: Seq[Bool] = {
@@ -64,7 +64,7 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
     (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
   }
 
-  override lazy val choice = Wire(init=UInt(n-1))
+  override lazy val choice = Wire(init=UInt.Lit(n-1))
   for (i <- n-2 to 0 by -1)
     when (io.in(i).valid) { choice := UInt.Lit(i) }
   for (i <- n-1 to 1 by -1)
@@ -75,7 +75,7 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
 
-  override lazy val choice = Wire(init=UInt(n-1))
+  override lazy val choice = Wire(init=UInt.Lit(n-1))
   for (i <- n-2 to 0 by -1)
     when (io.in(i).valid) { choice := UInt.Lit(i) }
 }
@@ -103,7 +103,7 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
 class Arbiter[T <: Data](gen: T, n: Int) extends Module {
   val io = IO(new ArbiterIO(gen, n))
 
-  io.chosen := UInt(n-1)
+  io.chosen := UInt.Lit(n-1)
   io.out.bits := io.in(n-1).bits
   for (i <- n-2 to 0 by -1) {
     when (io.in(i).valid) {
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index ab1ff550..b2a9a28c 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -27,7 +27,7 @@ object Fill {
   /** Fan out x n times */
   def apply(n: Int, x: UInt): UInt = {
     n match {
-      case 0 => UInt(width=0)
+      case 0 => UInt.width(0)
       case 1 => x
       case y if n > 1 =>
         val p2 = Array.ofDim[UInt](log2Up(n + 1))
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 5e93b009..8f8bde4a 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -20,7 +20,7 @@ object Log2 {
     } else if (width == 2) {
       x(1)
     } else {
-      Mux(x(width-1), UInt(width-1), apply(x, width-1))
+      Mux(x(width-1), UInt.width(width-1), apply(x, width-1))
     }
   }
 
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 5958c744..037f9a22 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -82,7 +82,7 @@ class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
   val deq = DeqIO(gen)
   /** The current amount of data in the queue */
-  val count = Output(UInt(log2Up(entries + 1)))
+  val count = Output(UInt.width(log2Up(entries + 1)))
 }
 
 /** A hardware module implementing a Queue
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 8a5caf44..c1f94ba6 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -31,7 +31,7 @@ object OHToUInt {
   * @example {{{ data_out := PriorityEncoder(data_in) }}}
   */
 object PriorityEncoder {
-  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
+  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt.Lit(_)))
   def apply(in: Bits): UInt = apply(in.toBools)
 }
 
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 08999a1b..0aaa3c57 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -11,10 +11,10 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
   val a = UInt(_a, w)
   val b = UInt(_b, w)
-  assert(~a === UInt(mask & ~_a))
-  assert((a & b) === UInt(_a & _b))
-  assert((a | b) === UInt(_a | _b))
-  assert((a ^ b) === UInt(_a ^ _b))
+  assert(~a === UInt.Lit(mask & ~_a))
+  assert((a & b) === UInt.Lit(_a & _b))
+  assert((a | b) === UInt.Lit(_a | _b))
+  assert((a ^ b) === UInt.Lit(_a ^ _b))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 2f6322b1..3d3d58f3 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -7,8 +7,8 @@ import org.scalatest.prop._
 import chisel3.testers.BasicTester
 
 class Coord extends Bundle {
-  val x = UInt(width = 32)
-  val y = UInt(width = 32)
+  val x = UInt.width( 32)
+  val y = UInt.width( 32)
 }
 
 class BundleWire(n: Int) extends Module {
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 638ef9b7..c5aaa554 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -17,11 +17,11 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
 class ComplexAssign(w: Int) extends Module {
   val io = IO(new Bundle {
     val e   = Input(Bool())
-    val in  = Input(new Complex(UInt(width = w), UInt(width = w)))
-    val out = Output(new Complex(UInt(width = w), UInt(width = w)))
+    val in  = Input(new Complex(UInt.width(w), UInt.width(w)))
+    val out = Output(new Complex(UInt.width(w), UInt.width(w)))
   })
   when (io.e) {
-    val tmp = Wire(new Complex(UInt(width = w), UInt(width = w)))
+    val tmp = Wire(new Complex(UInt.width(w), UInt.width(w)))
     tmp := io.in
     io.out.re := tmp.re
     io.out.im := tmp.im
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 770d2e0e..cd8a5d63 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 class UsesDeqIOInfo extends Bundle {
   val test_width = 32
 
-  val info_data = UInt(width = test_width)
+  val info_data = UInt.width(test_width)
 }
 
 class UsesDeqIO extends Module {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index d0d945b7..5e4c897a 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -15,8 +15,8 @@ class GCD extends Module {
     val z  = Output(UInt.width(32))
     val v  = Output(Bool())
   })
-  val x = Reg(UInt(width = 32))
-  val y = Reg(UInt(width = 32))
+  val x = Reg(UInt.width( 32))
+  val y = Reg(UInt.width( 32))
   when (x > y)   { x := x -% y }
   .otherwise     { y := y -% x }
   when (io.e) { x := io.a; y := io.b }
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 2399267e..fa4c4898 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -11,7 +11,7 @@ import chisel3.util._
 class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
 
-  val test = Wire(UInt(width=4))
+  val test = Wire(UInt.width(4))
   assert(test === 7.U)  // allow read references before assign references
 
   test := 13.U
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 5d4bd18d..8b9016b1 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt.Lit(20))
+      val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20))
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
@@ -24,11 +24,11 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
     class RegUnknownWidthTester extends BasicTester {
-      val reg1 = Reg(next=Wire(UInt(width=3)), init=20.U)
+      val reg1 = Reg(next=Wire(UInt.width(3)), init=20.U)
       DataMirror.widthOf(reg1).known should be (false)
       val reg2 = Reg(init=20.U)
       DataMirror.widthOf(reg2).known should be (false)
-      val reg3 = Reg(next=Wire(UInt(width=3)), init=5.U)
+      val reg3 = Reg(next=Wire(UInt.width(3)), init=5.U)
       DataMirror.widthOf(reg3).known should be (false)
     }
     elaborate { new RegUnknownWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 156e5df2..665bb8e6 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -9,17 +9,17 @@ class Risc extends Module {
   val io = IO(new Bundle {
     val isWr   = Input(Bool())
     val wrAddr = Input(UInt.width(8))
-    val wrData = Input(Bits(32))
+    val wrData = Input(Bits.width(32))
     val boot   = Input(Bool())
     val valid  = Output(Bool())
-    val out    = Output(Bits(32))
+    val out    = Output(Bits.width(32))
   })
   val memSize = 256
-  val file = Mem(memSize, Bits(width = 32))
-  val code = Mem(memSize, Bits(width = 32))
+  val file = Mem(memSize, Bits.width(32))
+  val code = Mem(memSize, Bits.width(32))
   val pc   = Reg(init=UInt(0, 8))
 
-  val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2)
+  val add_op :: imm_op :: Nil = Enum(Bits.width(8), 2)
 
   val inst = code(pc)
   val op   = inst(31,24)
@@ -29,7 +29,7 @@ class Risc extends Module {
 
   val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
   val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
-  val rc = Wire(Bits(width = 32))
+  val rc = Wire(Bits.width(32))
 
   io.valid := Bool(false)
   io.out   := 0.asUInt()
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 440228c9..0c84e62a 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -16,7 +16,7 @@ class ChiselStack(val depth: Int) extends Module {
     val dataOut = Output(UInt.width(32))
   })
 
-  val stack_mem = Mem(depth, UInt(width = 32))
+  val stack_mem = Mem(depth, UInt.width(32))
   val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
   val out       = Reg(init = UInt(0, width = 32))
 
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 75c4278f..40730264 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -11,13 +11,13 @@ import chisel3.util._
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = IO(new Bundle {
-    val wi  = Input(UInt(log2Up(n)))
-    val ri  = Input(UInt(log2Up(n)))
+    val wi  = Input(UInt.width(log2Up(n)))
+    val ri  = Input(UInt.width(log2Up(n)))
     val we  = Input(Bool())
     val  d  = Input(UInt.width(w))
     val  o  = Output(UInt.width(w))
   })
-  val m = Mem(n, UInt(width = w))
+  val m = Mem(n, UInt.width(w))
   io.o := m(io.ri)
   when (io.we) {
     m(io.wi) := io.d
@@ -30,8 +30,8 @@ class Tbl(w: Int, n: Int) extends Module {
 class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), idxs.size)
   val dut = Module(new Tbl(w, n))
-  val vvalues = Vec(values.map(UInt(_)))
-  val vidxs = Vec(idxs.map(UInt(_)))
+  val vvalues = Vec(values.map(UInt.Lit(_)))
+  val vidxs = Vec(idxs.map(UInt.Lit(_)))
   val prev_idx = vidxs(cnt - UInt.Lit(1))
   val prev_value = vvalues(cnt - UInt.Lit(1))
   dut.io.wi := vidxs(cnt)
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 812f822d..69633461 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -86,7 +86,7 @@ class GoodBoolConversion extends Module {
 
 class BadBoolConversion extends Module {
   val io = IO(new Bundle {
-    val u = Input(UInt(width = 5))
+    val u = Input(UInt.width( 5))
     val b = Output(Bool())
   })
   io.b := io.u.toBool
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index cdb1ba8d..22b518a2 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -18,9 +18,9 @@ class ValueTester(w: Int, values: List[Int]) extends BasicTester {
 }
 
 class TabulateTester(n: Int) extends BasicTester {
-  val v = Vec(Range(0, n).map(i => UInt(i * 2)))
-  val x = Vec(Array.tabulate(n){ i => UInt(i * 2) })
-  val u = Vec.tabulate(n)(i => UInt(i*2))
+  val v = Vec(Range(0, n).map(i => UInt.Lit(i * 2)))
+  val x = Vec(Array.tabulate(n){ i => UInt.Lit(i * 2) })
+  val u = Vec.tabulate(n)(i => UInt.Lit(i*2))
 
   assert(v.toBits === x.toBits)
   assert(v.toBits === u.toBits)
@@ -31,7 +31,7 @@ class TabulateTester(n: Int) extends BasicTester {
 
 class ShiftRegisterTester(n: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), n*2)
-  val shifter = Reg(Vec(n, UInt(width = log2Up(n))))
+  val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
   when (cnt >= UInt.Lit(n)) {
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 081990ad..6e1d267d 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -19,7 +19,7 @@ import chisel3.util._
   * IMPORTANT:  The canonical way to initialize a decoupled inteface is still being debated.
   */
 class Packet extends Bundle {
-  val header = UInt(width = 1)
+  val header = UInt.width(1)
 }
 
 /**
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 58aa43e7..2f5c49e4 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -12,7 +12,7 @@ class WhenTester() extends BasicTester {
   val cnt = Counter(4)
   when(Bool(true)) { cnt.inc() }
 
-  val out = Wire(UInt(width=3))
+  val out = Wire(UInt.width(3))
   when(cnt.value === UInt.Lit(0)) {
     out := UInt.Lit(1)
   } .elsewhen (cnt.value === UInt.Lit(1)) {
@@ -34,7 +34,7 @@ class OverlappedWhenTester() extends BasicTester {
   val cnt = Counter(4)
   when(Bool(true)) { cnt.inc() }
 
-  val out = Wire(UInt(width=3))
+  val out = Wire(UInt.width(3))
   when(cnt.value <= UInt.Lit(0)) {
     out := UInt.Lit(1)
   } .elsewhen (cnt.value <= UInt.Lit(1)) {
-- 
cgit v1.2.3


From d269818bdd4f2b71abebfaba9d7f8c9b4d488688 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 21 Jul 2016 09:24:55 -0700
Subject: Ensure test_wire is sinkable.

---
 src/test/scala/chiselTests/TesterDriverSpec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 4c1e41c8..b0f3a981 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -20,7 +20,7 @@ class FinishTester extends BasicTester {
     stop()
   }
 
-  val test_wire = UInt(1, width = test_wire_width)
+  val test_wire = Wire(init=UInt(1, test_wire_width))
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
-- 
cgit v1.2.3


From 7c9043859994b32bb07d2fce4ae61a7a3362a1b3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 21 Jul 2016 17:12:06 -0700
Subject: Introduce chiselCloneType to distinguish from cloneType. Still fails
 one test - DirectionSpec in Direction.scala

---
 src/main/scala/chisel3/util/Decoupled.scala    | 8 +++-----
 src/main/scala/chisel3/util/Reg.scala          | 4 ++--
 src/main/scala/chisel3/util/Valid.scala        | 8 ++------
 src/test/scala/chiselTests/ComplexAssign.scala | 2 +-
 src/test/scala/chiselTests/Module.scala        | 2 +-
 5 files changed, 9 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 037f9a22..76bf4842 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -12,7 +12,7 @@ class DecoupledIO[+T <: Data](gen: T) extends Bundle
 {
   val ready = Input(Bool())
   val valid = Output(Bool())
-  val bits  = Output(gen.cloneType)
+  val bits  = Output(gen.chiselCloneType)
   override def cloneType: this.type = DecoupledIO(gen).asInstanceOf[this.type]
 }
 
@@ -59,9 +59,7 @@ object DecoupledIO {
     }
   }
 //  override def cloneType: this.type = {
-//    val clone = DeqIO(gen).asInstanceOf[this.type]
-//    clone.unBind()
-//    clone
+//    DeqIO(gen).asInstanceOf[this.type]
 //  }
 }
 
@@ -171,7 +169,7 @@ extends Module(override_reset=override_reset) {
 object Queue
 {
   def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T]  = {
-    val q = Module(new Queue(enq.bits.cloneType, entries, pipe))
+    val q = Module(new Queue(enq.bits.chiselCloneType, entries, pipe))
     q.io.enq.valid := enq.valid // not using <> so that override is allowed
     q.io.enq.bits := enq.bits
     enq.ready := q.io.enq.ready
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 81de4754..f77a9667 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -26,12 +26,12 @@ object RegEnable
 {
   def apply[T <: Data](updateData: T, enable: Bool): T = {
     val r = Reg(updateData)
-    when (enable) { r := updateData }
+    when (enable) { r := updateData.chiselCloneType }
     r
   }
   def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
     val r = RegInit(resetData)
-    when (enable) { r := updateData }
+    when (enable) { r := updateData.chiselCloneType }
     r
   }
 }
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 5641f0f2..743038f3 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -11,13 +11,9 @@ import chisel3._
 class Valid[+T <: Data](gen: T) extends Bundle
 {
   val valid = Output(Bool())
-  val bits  = Output(gen.cloneType)
+  val bits  = Output(gen.chiselCloneType)
   def fire(dummy: Int = 0): Bool = valid
-  override def cloneType: this.type = {
-    val clone = Valid(gen).asInstanceOf[this.type]
-    clone.unBind()
-    clone
-  }
+  override def cloneType: this.type = Valid(gen).asInstanceOf[this.type]
 }
 
 /** Adds a valid protocol to any interface */
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index c5aaa554..fce2c602 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -11,7 +11,7 @@ import chisel3.util._
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
-    new Complex(re.cloneType, im.cloneType).asInstanceOf[this.type]
+    new Complex(re.chiselCloneType, im.chiselCloneType).asInstanceOf[this.type]
 }
 
 class ComplexAssign(w: Int) extends Module {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 59451a2b..26953f5f 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
 
 class ModuleWire extends Module {
   val io = IO(new SimpleIO)
-  val inc = Wire(Module(new PlusOne).io.cloneType)
+  val inc = Wire(Module(new PlusOne).io.chiselCloneType)
   inc.in := io.in
   io.out := inc.out
 }
-- 
cgit v1.2.3


From 922d43c085585b9eb0276ff2e8e680ca93ec1c2e Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 08:48:41 -0700
Subject: catch Bad connection exception

---
 src/test/scala/chiselTests/Direction.scala | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index e22e120b..bb01f0eb 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -31,7 +31,15 @@ class DirectionSpec extends ChiselPropSpec {
   }
 
   property("Inputs should not be assignable") {
-    elaborate(new BadDirection)
+    var excepts: Boolean = false
+    try elaborate(new BadDirection)
+    catch {
+      case e: Exception => {
+        excepts = true
+      }
+      // Should except so this is okay
+      // Ideally, would throw and catch more precise exception
+    }
+    assert(excepts, "Bad connection should have thrown exception!")
   }
-
 }
-- 
cgit v1.2.3


From 2d4cb434f214c31b5e3e4247775b27f1eb8d7734 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 09:18:23 -0700
Subject: Add missing compatibility.scala.

---
 src/main/scala/chisel3/compatibility.scala | 156 +++++++++++++++++++++++++++++
 1 file changed, 156 insertions(+)
 create mode 100644 src/main/scala/chisel3/compatibility.scala

(limited to 'src')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
new file mode 100644
index 00000000..9360acbc
--- /dev/null
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -0,0 +1,156 @@
+// See LICENSE for license details.
+
+// Allows legacy users to continue using Chisel (capital C) package name while
+// moving to the more standard package naming convention chisel3 (lowercase c).
+
+package object Chisel {
+  type Direction = chisel3.core.Direction
+  val INPUT = chisel3.core.Direction.Input
+  val OUTPUT = chisel3.core.Direction.Output
+  object Flipped {
+    def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target)
+  }
+  type ChiselException = chisel3.internal.ChiselException
+
+  type Data = chisel3.core.Data
+  val Wire = chisel3.core.Wire
+  val Clock = chisel3.core.Clock
+  type Clock = chisel3.core.Clock
+
+  type Aggregate = chisel3.core.Aggregate
+  val Vec = chisel3.core.Vec
+  type Vec[T <: Data] = chisel3.core.Vec[T]
+  type VecLike[T <: Data] = chisel3.core.VecLike[T]
+  type Bundle = chisel3.core.Bundle
+
+  val assert = chisel3.core.assert
+  val stop = chisel3.core.stop
+
+  type Element = chisel3.core.Element
+  type Bits = chisel3.core.Bits
+  val Bits = chisel3.core.Bits
+  type Num[T <: Data] = chisel3.core.Num[T]
+  type UInt = chisel3.core.UInt
+  val UInt = chisel3.core.UInt
+  type SInt = chisel3.core.SInt
+  val SInt = chisel3.core.SInt
+  type Bool = chisel3.core.Bool
+  val Bool = chisel3.core.Bool
+  val Mux = chisel3.core.Mux
+
+  type BlackBox = chisel3.core.BlackBox
+
+  val Mem = chisel3.core.Mem
+  type MemBase[T <: Data] = chisel3.core.MemBase[T]
+  type Mem[T <: Data] = chisel3.core.Mem[T]
+  val SeqMem = chisel3.core.SeqMem
+  type SeqMem[T <: Data] = chisel3.core.SeqMem[T]
+
+  val Module = chisel3.core.Module
+  type Module = chisel3.core.Module
+
+  val printf = chisel3.core.printf
+
+  val Reg = chisel3.core.Reg
+
+  val when = chisel3.core.when
+  type WhenContext = chisel3.core.WhenContext
+
+
+  type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
+  val Driver = chisel3.Driver
+  type FileSystemUtilities = chisel3.compatibility.FileSystemUtilities
+  val ImplicitConversions = chisel3.util.ImplicitConversions
+  val chiselMain = chisel3.compatibility.chiselMain
+  val throwException = chisel3.compatibility.throwException
+  val debug = chisel3.core.debug
+
+  object testers {
+    type BasicTester = chisel3.testers.BasicTester
+    val TesterDriver = chisel3.testers.TesterDriver
+  }
+
+
+  val log2Up = chisel3.util.log2Up
+  val log2Ceil = chisel3.util.log2Ceil
+  val log2Down = chisel3.util.log2Down
+  val log2Floor = chisel3.util.log2Floor
+  val isPow2 = chisel3.util.isPow2
+
+  val BitPat = chisel3.util.BitPat
+  type BitPat = chisel3.util.BitPat
+
+  type ArbiterIO[T <: Data] = chisel3.util.ArbiterIO[T]
+  type LockingArbiterLike[T <: Data] = chisel3.util.LockingArbiterLike[T]
+  type LockingRRArbiter[T <: Data] = chisel3.util.LockingRRArbiter[T]
+  type LockingArbiter[T <: Data] = chisel3.util.LockingArbiter[T]
+  type RRArbiter[T <: Data] = chisel3.util.RRArbiter[T]
+  type Arbiter[T <: Data] = chisel3.util.Arbiter[T]
+
+  val FillInterleaved = chisel3.util.FillInterleaved
+  val PopCount = chisel3.util.PopCount
+  val Fill = chisel3.util.Fill
+  val Reverse = chisel3.util.Reverse
+
+  val Cat = chisel3.util.Cat
+
+  val Log2 = chisel3.util.Log2
+
+  val unless = chisel3.util.unless
+  type SwitchContext[T <: Bits] = chisel3.util.SwitchContext[T]
+  val is = chisel3.util.is
+  val switch = chisel3.util.switch
+
+  type Counter = chisel3.util.Counter
+  val Counter = chisel3.util.Counter
+
+  type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
+  val DecoupledIO = chisel3.util.DecoupledIO
+  object EnqIO {
+    def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
+  }
+  object DeqIO {
+    def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
+  }
+  type QueueIO[T <: Data] = chisel3.util.QueueIO[T]
+  type Queue[T <: Data] = chisel3.util.Queue[T]
+  val Queue = chisel3.util.Queue
+
+  val Enum = chisel3.util.Enum
+
+  val LFSR16 = chisel3.util.LFSR16
+
+  val ListLookup = chisel3.util.ListLookup
+  val Lookup = chisel3.util.Lookup
+
+  val Mux1H = chisel3.util.Mux1H
+  val PriorityMux = chisel3.util.PriorityMux
+  val MuxLookup = chisel3.util.MuxLookup
+  val MuxCase = chisel3.util.MuxCase
+
+  val OHToUInt = chisel3.util.OHToUInt
+  val PriorityEncoder = chisel3.util.PriorityEncoder
+  val UIntToOH = chisel3.util.UIntToOH
+  val PriorityEncoderOH = chisel3.util.PriorityEncoderOH
+
+  val RegNext = chisel3.util.RegNext
+  val RegInit = chisel3.util.RegInit
+  val RegEnable = chisel3.util.RegEnable
+  val ShiftRegister = chisel3.util.ShiftRegister
+
+  type ValidIO[+T <: Data] = chisel3.util.Valid[T]
+  val Valid = chisel3.util.Valid
+  val Pipe = chisel3.util.Pipe
+  type Pipe[T <: Data] = chisel3.util.Pipe[T]
+
+
+  import chisel3.internal.firrtl.Width
+  implicit def fromBigIntToLiteral(x: BigInt): chisel3.fromBigIntToLiteral =
+    new chisel3.fromBigIntToLiteral(x)
+  implicit def fromIntToLiteral(x: Int): chisel3.fromIntToLiteral=
+    new chisel3.fromIntToLiteral(x)
+  implicit def fromStringToLiteral(x: String): chisel3.fromStringToLiteral=
+    new chisel3.fromStringToLiteral(x)
+  implicit def fromBooleanToLiteral(x: Boolean): chisel3.fromBooleanToLiteral=
+    new chisel3.fromBooleanToLiteral(x)
+}
-- 
cgit v1.2.3


From 50518f43cbd9c783633714a26ecdb0f2f18a1142 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 09:19:14 -0700
Subject: Use more idiomatic ScalaTest exception expecting code.

---
 src/main/scala/chisel3/package.scala       |  1 +
 src/test/scala/chiselTests/Direction.scala | 13 +++----------
 2 files changed, 4 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index e43434c0..d47ed890 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -113,4 +113,5 @@ package object chisel3 {
 
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
+  type ChiselException = chisel3.internal.ChiselException
 }
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index bb01f0eb..2fe31475 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -22,7 +22,7 @@ class BadDirection extends DirectionHaver {
   io.in := UInt.Lit(0)
 }
 
-class DirectionSpec extends ChiselPropSpec {
+class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
 
   //TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests?
 
@@ -31,15 +31,8 @@ class DirectionSpec extends ChiselPropSpec {
   }
 
   property("Inputs should not be assignable") {
-    var excepts: Boolean = false
-    try elaborate(new BadDirection)
-    catch {
-      case e: Exception => {
-        excepts = true
-      }
-      // Should except so this is okay
-      // Ideally, would throw and catch more precise exception
+    a[ChiselException] should be thrownBy {
+     elaborate(new BadDirection)
     }
-    assert(excepts, "Bad connection should have thrown exception!")
   }
 }
-- 
cgit v1.2.3


From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 14:06:51 -0700
Subject: Minimize differences with master. Remove .Lit(x) usage. Undo
 "private" scope change. Change "firing" back to "fire". Add package level
 NODIR definition.

---
 src/main/scala/chisel3/compatibility.scala         |  1 +
 src/main/scala/chisel3/package.scala               |  3 +-
 src/main/scala/chisel3/util/Arbiter.scala          | 24 +++++++--------
 src/main/scala/chisel3/util/CircuitMath.scala      |  4 +--
 src/main/scala/chisel3/util/Counter.scala          | 10 +++---
 src/main/scala/chisel3/util/Decoupled.scala        | 10 +++---
 .../scala/chisel3/util/ImplicitConversions.scala   |  2 +-
 src/main/scala/chisel3/util/OneHot.scala           |  6 ++--
 src/test/scala/chiselTests/Assert.scala            |  4 +--
 src/test/scala/chiselTests/BitwiseOps.scala        |  8 ++---
 src/test/scala/chiselTests/BlackBox.scala          | 30 +++++++++---------
 src/test/scala/chiselTests/BundleWire.scala        |  8 ++---
 src/test/scala/chiselTests/ComplexAssign.scala     | 12 ++++----
 src/test/scala/chiselTests/Counter.scala           |  8 ++---
 src/test/scala/chiselTests/Decoder.scala           |  2 +-
 src/test/scala/chiselTests/Direction.scala         |  4 +--
 src/test/scala/chiselTests/MemorySearch.scala      |  6 ++--
 src/test/scala/chiselTests/Module.scala            |  4 +--
 src/test/scala/chiselTests/MulLookup.scala         |  6 ++--
 src/test/scala/chiselTests/Printf.scala            |  6 ++--
 src/test/scala/chiselTests/Reg.scala               |  2 +-
 src/test/scala/chiselTests/Risc.scala              |  2 +-
 src/test/scala/chiselTests/SIntOps.scala           |  6 ++--
 src/test/scala/chiselTests/Stack.scala             | 12 ++++----
 src/test/scala/chiselTests/Tbl.scala               | 10 +++---
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  4 +--
 src/test/scala/chiselTests/UIntOps.scala           |  4 +--
 src/test/scala/chiselTests/Vec.scala               | 12 ++++----
 src/test/scala/chiselTests/When.scala              | 36 +++++++++++-----------
 29 files changed, 124 insertions(+), 122 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index b7020b5e..041553e0 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -7,6 +7,7 @@ package object Chisel {
   type Direction = chisel3.core.Direction
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
+  val NODIR = chisel3.core.Direction.Unspecified
   object Flipped {
     def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target)
   }
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 9a79b109..774455c4 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -95,7 +95,7 @@ package object chisel3 {
     def asSInt(width: Int) = SInt(x, width)
   }
   implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt.Lit(x)
+    def U: UInt = UInt(x)
   }
   implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
     def B: Bool = Bool(x)
@@ -113,5 +113,6 @@ package object chisel3 {
 
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
+  val NODIR = chisel3.core.Direction.Unspecified
   type ChiselException = chisel3.internal.ChiselException
 }
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 0ece3a0a..5875b3f2 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -36,17 +36,17 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
   if (count > 1) {
     val lockCount = Counter(count)
     val lockIdx = Reg(UInt())
-    val locked = lockCount.value =/= UInt.Lit(0)
+    val locked = lockCount.value =/= UInt(0)
     val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
 
-    when (io.out.firing && wantsLock) {
+    when (io.out.fire() && wantsLock) {
       lockIdx := io.chosen
       lockCount.inc()
     }
 
     when (locked) { io.chosen := lockIdx }
     for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
-      in.ready := Mux(locked, lockIdx === UInt.Lit(i), g) && io.out.ready
+      in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
   } else {
     for ((in, g) <- io.in zip grant)
       in.ready := g && io.out.ready
@@ -55,8 +55,8 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
-  lazy val lastGrant = RegEnable(io.chosen, io.out.firing)
-  lazy val grantMask = (0 until n).map(UInt.Lit(_) > lastGrant)
+  lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
+  lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
   lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
 
   override def grant: Seq[Bool] = {
@@ -64,20 +64,20 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
     (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
   }
 
-  override lazy val choice = Wire(init=UInt.Lit(n-1))
+  override lazy val choice = Wire(init=UInt(n-1))
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt.Lit(i) }
+    when (io.in(i).valid) { choice := UInt(i) }
   for (i <- n-1 to 1 by -1)
-    when (validMask(i)) { choice := UInt.Lit(i) }
+    when (validMask(i)) { choice := UInt(i) }
 }
 
 class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
 
-  override lazy val choice = Wire(init=UInt.Lit(n-1))
+  override lazy val choice = Wire(init=UInt(n-1))
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt.Lit(i) }
+    when (io.in(i).valid) { choice := UInt(i) }
 }
 
 /** Hardware module that is used to sequence n producers into 1 consumer.
@@ -103,11 +103,11 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
 class Arbiter[T <: Data](gen: T, n: Int) extends Module {
   val io = IO(new ArbiterIO(gen, n))
 
-  io.chosen := UInt.Lit(n-1)
+  io.chosen := UInt(n-1)
   io.out.bits := io.in(n-1).bits
   for (i <- n-2 to 0 by -1) {
     when (io.in(i).valid) {
-      io.chosen := UInt.Lit(i)
+      io.chosen := UInt(i)
       io.out.bits := io.in(i).bits
     }
   }
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 27bd7bfb..c809e14b 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -16,11 +16,11 @@ object Log2 {
   /** Compute the Log2 on the least significant n bits of x */
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
-      UInt.Lit(0)
+      UInt(0)
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt.Lit(width-1), apply(x, width-1))
+      Mux(x(width-1), UInt(width-1), apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 05d8fba8..40615769 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -10,17 +10,17 @@ import chisel3._
   */
 class Counter(val n: Int) {
   require(n >= 0)
-  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt.Lit(0)
+  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
   /** Increment the counter, returning whether the counter currently is at the
     * maximum and will wrap. The incremented value is registered and will be
     * visible on the next cycle.
     */
   def inc(): Bool = {
     if (n > 1) {
-      val wrap = value === UInt.Lit(n-1)
-      value := value + UInt.Lit(1)
+      val wrap = value === UInt(n-1)
+      value := value + UInt(1)
       if (!isPow2(n)) {
-        when (wrap) { value := UInt.Lit(0) }
+        when (wrap) { value := UInt(0) }
       }
       wrap
     } else {
@@ -33,7 +33,7 @@ class Counter(val n: Int) {
   * Example Usage:
   * {{{ val countOn = Bool(true) // increment counter every clock cycle
   * val myCounter = Counter(countOn, n)
-  * when ( myCounter.value === UInt.Lit(3) ) { ... } }}}*/
+  * when ( myCounter.value === UInt(3) ) { ... } }}}*/
 object Counter
 {
   def apply(n: Int): Counter = new Counter(n)
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 76bf4842..68c3ae88 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -23,7 +23,7 @@ object DecoupledIO {
   def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
 
   implicit class AddMethodsToDecoupled[T<:Data](val target: DecoupledIO[T]) extends AnyVal {
-    def firing: Bool = target.ready && target.valid
+    def fire(): Bool = target.ready && target.valid
 
     /** push dat onto the output bits of this interface to let the consumer know it has happened.
       * @param dat the values to assign to bits.
@@ -114,8 +114,8 @@ extends Module(override_reset=override_reset) {
   val ptr_match = enq_ptr.value === deq_ptr.value
   val empty = ptr_match && !maybe_full
   val full = ptr_match && maybe_full
-  val do_enq = Wire(init=io.enq.firing)
-  val do_deq = Wire(init=io.deq.firing)
+  val do_enq = Wire(init=io.enq.fire())
+  val do_deq = Wire(init=io.deq.fire())
 
   when (do_enq) {
     ram(enq_ptr.value) := io.enq.bits
@@ -151,9 +151,9 @@ extends Module(override_reset=override_reset) {
   } else {
     io.count := Mux(ptr_match,
                     Mux(maybe_full,
-                      UInt.Lit(entries), UInt.Lit(0)),
+                      UInt(entries), UInt(0)),
                     Mux(deq_ptr.value > enq_ptr.value,
-                      UInt.Lit(entries) + ptr_diff, ptr_diff))
+                      UInt(entries) + ptr_diff, ptr_diff))
   }
 }
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 3a9089c5..4d816a19 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,6 @@ package chisel3.util
 import chisel3._
 
 object ImplicitConversions {
-  implicit def intToUInt(x: Int): UInt = UInt.Lit(x)
+  implicit def intToUInt(x: Int): UInt = UInt(x)
   implicit def booleanToBool(x: Boolean): Bool = Bool(x)
 }
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 49661115..abede61e 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -31,7 +31,7 @@ object OHToUInt {
   * @example {{{ data_out := PriorityEncoder(data_in) }}}
   */
 object PriorityEncoder {
-  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt.Lit(_)))
+  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
   def apply(in: Bits): UInt = apply(in.toBools)
 }
 
@@ -41,9 +41,9 @@ object UIntToOH
 {
   def apply(in: UInt, width: Int = -1): UInt =
     if (width == -1) {
-      UInt.Lit(1) << in
+      UInt(1) << in
     } else {
-      (UInt.Lit(1) << in(log2Up(width)-1,0))(width-1,0)
+      (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
     }
 }
 
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index bf3c8092..efc2e1e7 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester {
 
 class PipelinedResetModule extends Module {
   val io = IO(new Bundle { })
-  val a = Reg(init = UInt.Lit(0xbeef))
-  val b = Reg(init = UInt.Lit(0xbeef))
+  val a = Reg(init = UInt(0xbeef))
+  val b = Reg(init = UInt(0xbeef))
   assert(a === b)
 }
 
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 0aaa3c57..08999a1b 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -11,10 +11,10 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
   val a = UInt(_a, w)
   val b = UInt(_b, w)
-  assert(~a === UInt.Lit(mask & ~_a))
-  assert((a & b) === UInt.Lit(_a & _b))
-  assert((a | b) === UInt.Lit(_a | _b))
-  assert((a ^ b) === UInt.Lit(_a ^ _b))
+  assert(~a === UInt(mask & ~_a))
+  assert((a & b) === UInt(_a & _b))
+  assert((a | b) === UInt(_a | _b))
+  assert((a ^ b) === UInt(_a ^ _b))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 9b43f0ef..c1154883 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -35,11 +35,11 @@ class BlackBoxTester extends BasicTester {
   val blackBoxPos = Module(new BlackBoxInverter)
   val blackBoxNeg = Module(new BlackBoxInverter)
 
-  blackBoxPos.io.in := UInt.Lit(1)
-  blackBoxNeg.io.in := UInt.Lit(0)
+  blackBoxPos.io.in := UInt(1)
+  blackBoxNeg.io.in := UInt(0)
 
-  assert(blackBoxNeg.io.out === UInt.Lit(1))
-  assert(blackBoxPos.io.out === UInt.Lit(0))
+  assert(blackBoxNeg.io.out === UInt(1))
+  assert(blackBoxPos.io.out === UInt(0))
   stop()
 }
 
@@ -54,15 +54,15 @@ class MultiBlackBoxTester extends BasicTester {
   val blackBoxPassPos = Module(new BlackBoxPassthrough)
   val blackBoxPassNeg = Module(new BlackBoxPassthrough)
 
-  blackBoxInvPos.io.in := UInt.Lit(1)
-  blackBoxInvNeg.io.in := UInt.Lit(0)
-  blackBoxPassPos.io.in := UInt.Lit(1)
-  blackBoxPassNeg.io.in := UInt.Lit(0)
+  blackBoxInvPos.io.in := UInt(1)
+  blackBoxInvNeg.io.in := UInt(0)
+  blackBoxPassPos.io.in := UInt(1)
+  blackBoxPassNeg.io.in := UInt(0)
 
-  assert(blackBoxInvNeg.io.out === UInt.Lit(1))
-  assert(blackBoxInvPos.io.out === UInt.Lit(0))
-  assert(blackBoxPassNeg.io.out === UInt.Lit(0))
-  assert(blackBoxPassPos.io.out === UInt.Lit(1))
+  assert(blackBoxInvNeg.io.out === UInt(1))
+  assert(blackBoxInvPos.io.out === UInt(0))
+  assert(blackBoxPassNeg.io.out === UInt(0))
+  assert(blackBoxPassPos.io.out === UInt(1))
   stop()
 }
 
@@ -77,7 +77,7 @@ class BlackBoxWithClockTester extends BasicTester {
   blackBox.io.in := impetus
   model := impetus
 
-  when(cycles > UInt.Lit(0)) {
+  when(cycles > UInt(0)) {
     assert(blackBox.io.out === model)
   }
   when(end) { stop() }
@@ -98,8 +98,8 @@ class BlackBoxWithParamsTester extends BasicTester {
 
   val (cycles, end) = Counter(Bool(true), 4)
 
-  assert(blackBoxOne.io.out  === UInt.Lit(1))
-  assert(blackBoxFour.io.out === UInt.Lit(4))
+  assert(blackBoxOne.io.out  === UInt(1))
+  assert(blackBoxFour.io.out === UInt(4))
 
   when(end) { stop() }
 }
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 3d3d58f3..0071041c 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -25,11 +25,11 @@ class BundleWire(n: Int) extends Module {
 
 class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new BundleWire(n))
-  dut.io.in.x := UInt.Lit(x)
-  dut.io.in.y := UInt.Lit(y)
+  dut.io.in.x := UInt(x)
+  dut.io.in.y := UInt(y)
   for (elt <- dut.io.outs) {
-    assert(elt.x === UInt.Lit(x))
-    assert(elt.y === UInt.Lit(y))
+    assert(elt.x === UInt(x))
+    assert(elt.y === UInt(y))
   }
   stop()
 }
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index fce2c602..0a1f31cc 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -26,19 +26,19 @@ class ComplexAssign(w: Int) extends Module {
     io.out.re := tmp.re
     io.out.im := tmp.im
   } .otherwise {
-    io.out.re := UInt.Lit(0)
-    io.out.im := UInt.Lit(0)
+    io.out.re := UInt(0)
+    io.out.im := UInt(0)
   }
 }
 
 class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), enList.size)
   val dut = Module(new ComplexAssign(32))
-  dut.io.in.re := UInt.Lit(re)
-  dut.io.in.im := UInt.Lit(im)
+  dut.io.in.re := UInt(re)
+  dut.io.in.im := UInt(im)
   dut.io.e := Vec(enList.map(Bool(_)))(cnt)
-  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt.Lit(0))
-  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt.Lit(0))
+  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0))
+  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0))
   assert(re_correct && im_correct)
   when(wrap) {
     stop()
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index af2fa550..69d8a44a 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -12,20 +12,20 @@ import chisel3.util._
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
   when(Bool(true)) { cnt.inc() }
-  when(cnt.value === UInt.Lit(max-1)) {
+  when(cnt.value === UInt(max-1)) {
     stop()
   }
 }
 
 class EnableTester(seed: Int) extends BasicTester {
-  val ens = Reg(init = UInt.Lit(seed))
+  val ens = Reg(init = UInt(seed))
   ens := ens >> 1
 
   val (cntEnVal, _) = Counter(ens(0), 32)
   val (_, done) = Counter(Bool(true), 33)
 
   when(done) {
-    assert(cntEnVal === UInt.Lit(popCount(seed)))
+    assert(cntEnVal === UInt(popCount(seed)))
     stop()
   }
 }
@@ -33,7 +33,7 @@ class EnableTester(seed: Int) extends BasicTester {
 class WrapTester(max: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), max)
   when(wrap) {
-    assert(cnt === UInt.Lit(max - 1))
+    assert(cnt === UInt(max - 1))
     stop()
   }
 }
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index ee892fc5..b50a80c0 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -24,7 +24,7 @@ class DecoderTester(pairs: List[(String, String)]) extends BasicTester {
   val dut = Module(new Decoder(bitpats))
   dut.io.inst := Vec(insts.map(UInt(_)))(cnt)
   when(!dut.io.matched) {
-    assert(cnt === UInt.Lit(0))
+    assert(cnt === UInt(0))
     stop()
   }
   when(wrap) {
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 2fe31475..83484a64 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -15,11 +15,11 @@ class DirectionHaver extends Module {
 }
 
 class GoodDirection extends DirectionHaver {
-  io.out := UInt.Lit(0)
+  io.out := UInt(0)
 }
 
 class BadDirection extends DirectionHaver {
-  io.in := UInt.Lit(0)
+  io.in := UInt(0)
 }
 
 class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index e4063532..1d09f3c5 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -17,11 +17,11 @@ class MemorySearch extends Module {
   val elts  = Vec(vals.map(UInt(_,4)))
   // val elts  = Mem(UInt(width = 32), 8) TODO ????
   val elt  = elts(index)
-  val end  = !io.en && ((elt === io.target) || (index === UInt.Lit(7)))
+  val end  = !io.en && ((elt === io.target) || (index === UInt(7)))
   when (io.en) {
-    index := UInt.Lit(0)
+    index := UInt(0)
   } .elsewhen (!end) {
-    index := index +% UInt.Lit(1)
+    index := index +% UInt(1)
   }
   io.done    := end
   io.address := index
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 26953f5f..7a4050db 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -16,8 +16,8 @@ class PlusOne extends Module {
 
 class ModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Input(Vec(n, UInt.Lit(32)))
-    val outs = Output(Vec(n, UInt.Lit(32)))
+    val ins  = Input(Vec(n, UInt(32)))
+    val outs = Output(Vec(n, UInt(32)))
   })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 16a29104..26ee4e03 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -24,9 +24,9 @@ class MulLookup(val w: Int) extends Module {
 
 class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new MulLookup(w))
-  dut.io.x := UInt.Lit(x)
-  dut.io.y := UInt.Lit(y)
-  assert(dut.io.z === UInt.Lit(x * y))
+  dut.io.x := UInt(x)
+  dut.io.y := UInt(y)
+  assert(dut.io.z === UInt(x * y))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index 92b6fee1..c872fde4 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
-  val x = UInt.Lit(254)
+  val x = UInt(254)
   printf("x=%x", x)
   stop()
 }
@@ -18,8 +18,8 @@ class ASCIIPrintfTester() extends BasicTester {
 }
 
 class MultiPrintfTester() extends BasicTester {
-  val x = UInt.Lit(254)
-  val y = UInt.Lit(255)
+  val x = UInt(254)
+  val y = UInt(255)
   printf("x=%x y=%x", x, y)
   stop()
 }
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 8b9016b1..b66d7cb4 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20))
+      val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt(20))
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 665bb8e6..6d5a0a76 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -38,7 +38,7 @@ class Risc extends Module {
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
   } .elsewhen (io.boot) {
-    pc := UInt.Lit(0)
+    pc := UInt(0)
   } .otherwise {
     switch(op) {
       is(add_op) { rc := ra +% rb }
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index d827c096..392c4803 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -32,9 +32,9 @@ class SIntOps extends Module {
   io.subout := a -% b
   // TODO:
   //io.timesout := (a * b)(15, 0)
-  //io.divout := a / Mux(b === SInt.Lit(0), SInt.Lit(1), b)
+  //io.divout := a / Mux(b === SInt(0), SInt(1), b)
   //io.divout := (a / b)(15, 0)
-  //io.modout := SInt.Lit(0)
+  //io.modout := SInt(0)
   //io.lshiftout := (a << 12)(15, 0) //  (a << ub(3, 0))(15, 0).toSInt
   io.rshiftout := (a >> 8) // (a >> ub).toSInt
   io.lessout := a < b
@@ -44,7 +44,7 @@ class SIntOps extends Module {
   io.lesseqout := a <= b
   io.greateqout := a >= b
   // io.negout := -a(15, 0).toSInt
-  io.negout := (SInt.Lit(0) -% a)
+  io.negout := (SInt(0) -% a)
 }
 
 /*
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 0c84e62a..a72af928 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module {
   val out       = Reg(init = UInt(0, width = 32))
 
   when (io.en) {
-    when(io.push && (sp < UInt.Lit(depth))) {
+    when(io.push && (sp < UInt(depth))) {
       stack_mem(sp) := io.dataIn
-      sp := sp +% UInt.Lit(1)
-    } .elsewhen(io.pop && (sp > UInt.Lit(0))) {
-      sp := sp -% UInt.Lit(1)
+      sp := sp +% UInt(1)
+    } .elsewhen(io.pop && (sp > UInt(0))) {
+      sp := sp -% UInt(1)
     }
-    when (sp > UInt.Lit(0)) {
-      out := stack_mem(sp -% UInt.Lit(1))
+    when (sp > UInt(0)) {
+      out := stack_mem(sp -% UInt(1))
     }
   }
   io.dataOut := out
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 40730264..66a06435 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -30,15 +30,15 @@ class Tbl(w: Int, n: Int) extends Module {
 class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), idxs.size)
   val dut = Module(new Tbl(w, n))
-  val vvalues = Vec(values.map(UInt.Lit(_)))
-  val vidxs = Vec(idxs.map(UInt.Lit(_)))
-  val prev_idx = vidxs(cnt - UInt.Lit(1))
-  val prev_value = vvalues(cnt - UInt.Lit(1))
+  val vvalues = Vec(values.map(UInt(_)))
+  val vidxs = Vec(idxs.map(UInt(_)))
+  val prev_idx = vidxs(cnt - UInt(1))
+  val prev_value = vvalues(cnt - UInt(1))
   dut.io.wi := vidxs(cnt)
   dut.io.ri := prev_idx
   dut.io.we := Bool(true) //TODO enSequence
   dut.io.d := vvalues(cnt)
-  when (cnt > UInt.Lit(0)) {
+  when (cnt > UInt(0)) {
     when (prev_idx === vidxs(cnt)) {
       assert(dut.io.o === vvalues(cnt))
     } .otherwise {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index b0f3a981..23eed15f 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -24,13 +24,13 @@ class FinishTester extends BasicTester {
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
-  assert(test_wire === UInt.Lit(test_wire_override_value))
+  assert(test_wire === UInt(test_wire_override_value))
 
   /** In finish we use last connect semantics to alter the test_wire in the circuit
     * with a new value
     */
   override def finish(): Unit = {
-    test_wire := UInt.Lit(test_wire_override_value)
+    test_wire := UInt(test_wire_override_value)
   }
 }
 
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 69633461..ad5aecd8 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -31,10 +31,10 @@ class UIntOps extends Module {
   io.addout := a +% b
   io.subout := a -% b
   io.timesout := (a * b)(15, 0)
-  io.divout := a / Mux(b === UInt.Lit(0), UInt.Lit(1), b)
+  io.divout := a / Mux(b === UInt(0), UInt(1), b)
   // io.modout := a % b
   // TODO:
-  io.modout := UInt.Lit(0)
+  io.modout := UInt(0)
   io.lshiftout := (a << b(3, 0))(15, 0)
   io.rshiftout := a >> b
   io.lessout := a < b
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 22b518a2..e8bd66bd 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -12,15 +12,15 @@ import chisel3.util._
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
   for ((a,b) <- v.zip(values)) {
-    assert(a === UInt.Lit(b))
+    assert(a === UInt(b))
   }
   stop()
 }
 
 class TabulateTester(n: Int) extends BasicTester {
-  val v = Vec(Range(0, n).map(i => UInt.Lit(i * 2)))
-  val x = Vec(Array.tabulate(n){ i => UInt.Lit(i * 2) })
-  val u = Vec.tabulate(n)(i => UInt.Lit(i*2))
+  val v = Vec(Range(0, n).map(i => UInt(i * 2)))
+  val x = Vec(Array.tabulate(n){ i => UInt(i * 2) })
+  val u = Vec.tabulate(n)(i => UInt(i*2))
 
   assert(v.toBits === x.toBits)
   assert(v.toBits === u.toBits)
@@ -34,8 +34,8 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
   val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
-  when (cnt >= UInt.Lit(n)) {
-    val expected = cnt - UInt.Lit(n)
+  when (cnt >= UInt(n)) {
+    val expected = cnt - UInt(n)
     assert(shifter(0) === expected)
   }
   when (wrap) {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 2f5c49e4..07ab3444 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -13,19 +13,19 @@ class WhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt.width(3))
-  when(cnt.value === UInt.Lit(0)) {
-    out := UInt.Lit(1)
-  } .elsewhen (cnt.value === UInt.Lit(1)) {
-    out := UInt.Lit(2)
-  } .elsewhen (cnt.value === UInt.Lit(2)) {
-    out := UInt.Lit(3)
+  when(cnt.value === UInt(0)) {
+    out := UInt(1)
+  } .elsewhen (cnt.value === UInt(1)) {
+    out := UInt(2)
+  } .elsewhen (cnt.value === UInt(2)) {
+    out := UInt(3)
   } .otherwise {
-    out := UInt.Lit(0)
+    out := UInt(0)
   }
 
-  assert(out === cnt.value + UInt.Lit(1))
+  assert(out === cnt.value + UInt(1))
 
-  when(cnt.value === UInt.Lit(3)) {
+  when(cnt.value === UInt(3)) {
     stop()
   }
 }
@@ -35,19 +35,19 @@ class OverlappedWhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt.width(3))
-  when(cnt.value <= UInt.Lit(0)) {
-    out := UInt.Lit(1)
-  } .elsewhen (cnt.value <= UInt.Lit(1)) {
-    out := UInt.Lit(2)
-  } .elsewhen (cnt.value <= UInt.Lit(2)) {
-    out := UInt.Lit(3)
+  when(cnt.value <= UInt(0)) {
+    out := UInt(1)
+  } .elsewhen (cnt.value <= UInt(1)) {
+    out := UInt(2)
+  } .elsewhen (cnt.value <= UInt(2)) {
+    out := UInt(3)
   } .otherwise {
-    out := UInt.Lit(0)
+    out := UInt(0)
   }
 
-  assert(out === cnt.value + UInt.Lit(1))
+  assert(out === cnt.value + UInt(1))
 
-  when(cnt.value === UInt.Lit(3)) {
+  when(cnt.value === UInt(3)) {
     stop()
   }
 }
-- 
cgit v1.2.3


From e09a09e3f4e5d6d8650b1db4add96c0a5b09e8ca Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 16:36:06 -0700
Subject: Enable current (chisel2-style) compatibility mode.

---
 src/test/scala/chiselTests/IOCompatibility.scala | 45 ++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 src/test/scala/chiselTests/IOCompatibility.scala

(limited to 'src')

diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
new file mode 100644
index 00000000..b904d77e
--- /dev/null
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -0,0 +1,45 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+
+class IOCSimpleIO extends Bundle {
+  val in  = UInt(INPUT,  32)
+  val out = UInt(OUTPUT, 32)
+}
+
+class IOCPlusOne extends Module {
+  val io = new IOCSimpleIO
+  io.out := io.in + UInt(1)
+}
+
+class IOCModuleVec(val n: Int) extends Module {
+  val io = new Bundle {
+    val ins  = Vec(n, UInt(INPUT,  32))
+    val outs = Vec(n, UInt(OUTPUT, 32))
+  }
+  val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
+  for (i <- 0 until n) {
+    pluses(i).in := io.ins(i)
+    io.outs(i)   := pluses(i).out
+  }
+}
+
+class IOCModuleWire extends Module {
+  val io = new IOCSimpleIO
+  val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType)
+  inc.in := io.in
+  io.out := inc.out
+}
+
+class IOCompatibilitySpec extends ChiselPropSpec {
+
+  property("IOCModuleVec should elaborate") {
+    elaborate { new IOCModuleVec(2) }
+  }
+
+  property("IOCModuleWire should elaborate") {
+    elaborate { new IOCModuleWire }
+  }
+}
-- 
cgit v1.2.3


From 11f119d0aba5ca578f2178cf83ba5096cc26cb22 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 26 Jul 2016 08:24:45 -0700
Subject: Add ValidIO definition for old code.

---
 src/main/scala/chisel3/package.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 774455c4..926ca00d 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -111,8 +111,10 @@ package object chisel3 {
     def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
   }
 
+  // Compatibility with existing code.
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
   val NODIR = chisel3.core.Direction.Unspecified
   type ChiselException = chisel3.internal.ChiselException
+  type ValidIO[+T <: Data] = chisel3.util.Valid[T]
 }
-- 
cgit v1.2.3


From bdbc554c0ccf490dd75d57c57b171452ac3de14b Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 08:59:11 -0700
Subject: Correct EnqIO/DeqIO Flipped-ness.

---
 src/main/scala/chisel3/util/Decoupled.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 68c3ae88..3ee363a2 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -64,10 +64,10 @@ object DecoupledIO {
 }
 
 object EnqIO {
-  def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
+  def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
 }
 object DeqIO {
-  def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
+  def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
 }
 
 /** An I/O Bundle for Queues
-- 
cgit v1.2.3


From ddeff65c1c50f0a7c3604cdc254538fbf1263d4f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 09:13:15 -0700
Subject: Correct EnqIO/DeqIO Flipped-ness.

---
 src/main/scala/chisel3/compatibility.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 041553e0..3b613a5e 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -108,10 +108,10 @@ package object Chisel {
   type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
   val DecoupledIO = chisel3.util.DecoupledIO
   object EnqIO {
-    def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
+    def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
   }
   object DeqIO {
-    def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
+    def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
   }
   type QueueIO[T <: Data] = chisel3.util.QueueIO[T]
   type Queue[T <: Data] = chisel3.util.Queue[T]
-- 
cgit v1.2.3


From e065416d59871d790cca9d75dc9a40fcc7b52015 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 09:13:45 -0700
Subject: Additional compatibility code.

---
 src/main/scala/chisel3/package.scala            | 30 +++++++++++++++++++++++++
 src/test/scala/chiselTests/DeqIOSpec.scala      |  4 ++--
 src/test/scala/chiselTests/VectorPacketIO.scala |  4 ++--
 3 files changed, 34 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 926ca00d..5fcf5e67 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -7,6 +7,9 @@ package object chisel3 {
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
   import util.BitPat
 
+  import chisel3.core.{Binding, Bits, Element, FlippedBinder}
+  import chisel3.util._
+  import chisel3.internal.firrtl.Port
 
   type Direction = chisel3.core.Direction
   object Input {
@@ -117,4 +120,31 @@ package object chisel3 {
   val NODIR = chisel3.core.Direction.Unspecified
   type ChiselException = chisel3.internal.ChiselException
   type ValidIO[+T <: Data] = chisel3.util.Valid[T]
+  val Decoupled = chisel3.util.DecoupledIO
+
+  class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+    def init(): Unit = {
+      this.noenq()
+    }
+    override def cloneType: this.type = EnqIO(gen).asInstanceOf[this.type]
+  }
+  class DeqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+    Binding.bind(this, FlippedBinder, "Error: Cannot flip ")
+    def init(): Unit = {
+      this.nodeq()
+    }
+    override def cloneType: this.type = DeqIO(gen).asInstanceOf[this.type]
+  }
+  object EnqIO {
+    def apply[T<:Data](gen: T): EnqIO[T] = new EnqIO(gen)
+  }
+  object DeqIO {
+    def apply[T<:Data](gen: T): DeqIO[T] = new DeqIO(gen)
+  }
+
+  // Debugger/Tester access to internal Chisel data structures and methods.
+  def getDataElements(a: Aggregate): Seq[Element] = {
+    a.allElements
+  }
+  def getModulePorts(m: Module): Seq[Port] = m.getPorts
 }
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index cd8a5d63..d41c50e5 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -17,8 +17,8 @@ class UsesDeqIOInfo extends Bundle {
 
 class UsesDeqIO extends Module {
   val io = IO(new Bundle {
-    val in = DeqIO(new UsesDeqIOInfo)
-    val out = EnqIO(new UsesDeqIOInfo)
+    val in = chisel3.util.DeqIO(new UsesDeqIOInfo)
+    val out = chisel3.util.EnqIO(new UsesDeqIOInfo)
   })
 }
 
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 6e1d267d..86c0d66f 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -28,8 +28,8 @@ class Packet extends Bundle {
   * The problem does not occur if the Vec is taken out
   */
 class VectorPacketIO(n: Int) extends Bundle {
-  val ins  = Vec(n, DeqIO(new Packet()))
-  val outs = Vec(n, EnqIO(new Packet()))
+  val ins  = Vec(n, chisel3.util.DeqIO(new Packet()))
+  val outs = Vec(n, chisel3.util.EnqIO(new Packet()))
 }
 
 /**
-- 
cgit v1.2.3


From 87d69afd1c8f28d91c78e7a539f6bf7a908e2a1f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 09:35:02 -0700
Subject: Correct EnqIO/DeqIO Flipped-ness.

---
 src/main/scala/chisel3/util/Decoupled.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 3ee363a2..0d000f49 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -76,9 +76,9 @@ object DeqIO {
 class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
 {
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */
-  val enq = EnqIO(gen)
+  val enq = DeqIO(gen)
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
-  val deq = DeqIO(gen)
+  val deq = EnqIO(gen)
   /** The current amount of data in the queue */
   val count = Output(UInt.width(log2Up(entries + 1)))
 }
-- 
cgit v1.2.3


From 089987c3e0b2bc390935a4d9d44db38a18c47901 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 10:29:13 -0700
Subject: Correct EnqIO/DeqIO Flipped-ness.

---
 src/test/scala/chiselTests/VectorPacketIO.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 86c0d66f..b8e3a154 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -41,8 +41,8 @@ class BrokenVectorPacketModule extends Module {
   val io = IO(new VectorPacketIO(n))
 
   /* the following method of initializing the circuit may change in the future */
-  io.ins.foreach(_.noenq())
-  io.outs.foreach(_.nodeq())
+  io.ins.foreach(_.nodeq())
+  io.outs.foreach(_.noenq())
 }
 
 class VectorPacketIOUnitTester extends BasicTester {
-- 
cgit v1.2.3


From 138329479914ac37b49a5a44841dc1de2929dca5 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 10:36:55 -0700
Subject: More compatibility fixes

---
 src/main/scala/chisel3/compatibility.scala       | 13 +++++++++++++
 src/main/scala/chisel3/package.scala             |  3 ++-
 src/test/scala/chiselTests/Direction.scala       |  2 +-
 src/test/scala/chiselTests/IOCompatibility.scala |  2 +-
 4 files changed, 17 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 3b613a5e..a7968bd5 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -107,6 +107,19 @@ package object Chisel {
 
   type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
   val DecoupledIO = chisel3.util.DecoupledIO
+  class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+    def init(): Unit = {
+      this.noenq()
+    }
+    override def cloneType: this.type = EnqIO(gen).asInstanceOf[this.type]
+  }
+  class DeqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+    chisel3.core.Binding.bind(this, chisel3.core.FlippedBinder, "Error: Cannot flip ")
+    def init(): Unit = {
+      this.nodeq()
+    }
+    override def cloneType: this.type = DeqIO(gen).asInstanceOf[this.type]
+  }
   object EnqIO {
     def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
   }
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 5fcf5e67..a0264df4 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -7,7 +7,7 @@ package object chisel3 {
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
   import util.BitPat
 
-  import chisel3.core.{Binding, Bits, Element, FlippedBinder}
+  import chisel3.core.{Binding, FlippedBinder}
   import chisel3.util._
   import chisel3.internal.firrtl.Port
 
@@ -120,6 +120,7 @@ package object chisel3 {
   val NODIR = chisel3.core.Direction.Unspecified
   type ChiselException = chisel3.internal.ChiselException
   type ValidIO[+T <: Data] = chisel3.util.Valid[T]
+  val ValidIO = chisel3.util.Valid
   val Decoupled = chisel3.util.DecoupledIO
 
   class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 83484a64..949b92ed 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -31,7 +31,7 @@ class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
   }
 
   property("Inputs should not be assignable") {
-    a[ChiselException] should be thrownBy {
+    a[Exception] should be thrownBy {
      elaborate(new BadDirection)
     }
   }
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index b904d77e..edbd3d09 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -2,7 +2,7 @@
 
 package chiselTests
 
-import chisel3._
+import Chisel._
 
 class IOCSimpleIO extends Bundle {
   val in  = UInt(INPUT,  32)
-- 
cgit v1.2.3


From 81d60a4076eab24553f67ae6b85031d2075a5fac Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 28 Jul 2016 17:20:33 -0700
Subject: Add missing Decoupled object pointer.

---
 src/main/scala/chisel3/compatibility.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index a7968bd5..939e005a 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -107,6 +107,7 @@ package object Chisel {
 
   type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
   val DecoupledIO = chisel3.util.DecoupledIO
+  val Decoupled = chisel3.util.DecoupledIO
   class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
     def init(): Unit = {
       this.noenq()
-- 
cgit v1.2.3


From c661d9c8def3a14e9e8a42d96005ead78e11e34d Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 3 Aug 2016 13:57:03 -0700
Subject: Merge "package" code into "compatibility".

---
 src/main/scala/chisel3/compatibility.scala | 50 ++++++++++++++++++++++++------
 1 file changed, 40 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 939e005a..d4ad7b9f 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -57,6 +57,46 @@ package object Chisel {
   val when = chisel3.core.when
   type WhenContext = chisel3.core.WhenContext
 
+  import chisel3.internal.firrtl.Width
+  /**
+  * These implicit classes allow one to convert scala.Int|scala.BigInt to
+  * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
+  * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
+  * mark a width for the new literal.
+  *
+  * Also provides .asBool to scala.Boolean and .asUInt to String
+  *
+  * Note that, for stylistic reasons, one should avoid extracting immediately
+  * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
+  * confusion (the 1 is a bit length and the 0 is a bit extraction position).
+  * Prefer storing the result and then extracting from it.
+  */
+  implicit class fromIntToLiteral(val x: Int) extends AnyVal {
+    def U: UInt = UInt(BigInt(x), Width())
+    def S: SInt = SInt(BigInt(x), Width())
+
+    def asUInt() = UInt(x, Width())
+    def asSInt() = SInt(x, Width())
+    def asUInt(width: Int) = UInt(x, width)
+    def asSInt(width: Int) = SInt(x, width)
+  }
+  
+  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
+    def U: UInt = UInt(x, Width())
+    def S: SInt = SInt(x, Width())
+
+    def asUInt() = UInt(x, Width())
+    def asSInt() = SInt(x, Width())
+    def asUInt(width: Int) = UInt(x, width)
+    def asSInt(width: Int) = SInt(x, width)
+  }
+  implicit class fromStringToLiteral(val x: String) extends AnyVal {
+    def U: UInt = UInt(x)
+  }
+  implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
+    def B: Bool = Bool(x)
+  }
+
 
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
@@ -158,14 +198,4 @@ package object Chisel {
   val Pipe = chisel3.util.Pipe
   type Pipe[T <: Data] = chisel3.util.Pipe[T]
 
-
-  import chisel3.internal.firrtl.Width
-  implicit def fromBigIntToLiteral(x: BigInt): chisel3.fromBigIntToLiteral =
-    new chisel3.fromBigIntToLiteral(x)
-  implicit def fromIntToLiteral(x: Int): chisel3.fromIntToLiteral=
-    new chisel3.fromIntToLiteral(x)
-  implicit def fromStringToLiteral(x: String): chisel3.fromStringToLiteral=
-    new chisel3.fromStringToLiteral(x)
-  implicit def fromBooleanToLiteral(x: Boolean): chisel3.fromBooleanToLiteral=
-    new chisel3.fromBooleanToLiteral(x)
 }
-- 
cgit v1.2.3


From f41f2533c55e506f7d5bf2ee0198de4d9a3dbea3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 16 Aug 2016 11:59:20 -0700
Subject: Reduce rocket-chip elaboration errors.

---
 src/main/scala/chisel3/util/Reg.scala | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index f77a9667..37c28b14 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -25,13 +25,14 @@ object RegInit {
 object RegEnable
 {
   def apply[T <: Data](updateData: T, enable: Bool): T = {
-    val r = Reg(updateData)
-    when (enable) { r := updateData.chiselCloneType }
+    val clonedUpdateData = updateData.chiselCloneType
+    val r = Reg(clonedUpdateData)
+    when (enable) { r := updateData }
     r
   }
   def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
     val r = RegInit(resetData)
-    when (enable) { r := updateData.chiselCloneType }
+    when (enable) { r := updateData }
     r
   }
 }
-- 
cgit v1.2.3