From c9beeeb1408f760309524f44a2dbd1c4f6d116b6 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 7 Feb 2017 17:18:53 -0800
Subject: Add generateFirrtl() method to ChiselSpec.scala (#423)

---
 src/test/scala/chiselTests/ChiselSpec.scala | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 4588abe1..55d58d77 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -27,6 +27,14 @@ trait ChiselRunners extends Assertions {
     assert(!runTester(t, additionalVResources))
   }
   def elaborate(t: => Module): Unit = Driver.elaborate(() => t)
+
+  /** Given a generator, return the Firrtl that it generates.
+    *
+    * @param t Module generator
+    * @return Firrtl representation as a String
+    */
+  def generateFirrtl(t: => Module): String = Driver.emit(() => t)
+
   /** Compiles a Chisel Module to Verilog */
   def compile(t: => Module): String = {
     val manager = new ExecutionOptionsManager("compile") with HasFirrtlOptions
-- 
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