From bb3ef96d8911dbba4e22926ad4ce71eb8ab0d869 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Wed, 31 Aug 2022 01:41:09 +0000 Subject: Wires should have source location information in firrtl (#2714) (#2716) - Remove line defeating having wire locators `implicit val noSourceInfo = UnlocatableSourceInfo` from `WireDefault#apply` - Add test to show locators (cherry picked from commit f701a9f8151891e3bf9019cd3229cb3f2cd1833b) Co-authored-by: Chick Markley --- src/test/scala/chiselTests/WireSpec.scala | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src') diff --git a/src/test/scala/chiselTests/WireSpec.scala b/src/test/scala/chiselTests/WireSpec.scala index 11a1f1a1..058a7f08 100644 --- a/src/test/scala/chiselTests/WireSpec.scala +++ b/src/test/scala/chiselTests/WireSpec.scala @@ -3,6 +3,7 @@ package chiselTests import chisel3._ +import chisel3.stage.ChiselStage class WireSpec extends ChiselFlatSpec { "WireDefault.apply" should "work" in { @@ -17,4 +18,19 @@ class WireSpec extends ChiselFlatSpec { it should "not allow init argument to affect type inference" in { assertDoesNotCompile("val x: UInt = WireDefault(UInt(4.W), 2.S)") } + it should "have source locator information on wires" in { + class Dummy extends chisel3.Module { + val in = IO(Input(Bool())) + val out = IO(Output(Bool())) + + val wire = WireInit(Bool(), true.B) + val wire2 = Wire(Bool()) + wire2 := in + out := in & wire & wire2 + } + + val chirrtl = ChiselStage.emitChirrtl(new Dummy) + chirrtl should include("wire wire : UInt<1> @[WireSpec.scala") + chirrtl should include("wire wire2 : UInt<1> @[WireSpec.scala") + } } -- cgit v1.2.3