From b18e98ba2d058c7dd24f96f005486b70c856aeca Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 21 Sep 2016 16:16:25 -0700
Subject: Expose FIRRTL asClock construct

Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.---
 src/test/scala/chiselTests/Clock.scala | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 src/test/scala/chiselTests/Clock.scala

(limited to 'src')

diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala
new file mode 100644
index 00000000..79dd2de4
--- /dev/null
+++ b/src/test/scala/chiselTests/Clock.scala
@@ -0,0 +1,22 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import org.scalatest._
+import org.scalatest.prop._
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
+
+class ClockAsUIntTester extends BasicTester {
+  assert(Bool(true).asClock.asUInt === UInt(1))
+  stop()
+}
+
+
+class ClockSpec extends ChiselPropSpec {
+  property("Bool.asClock.asUInt should pass a signal through unaltered") {
+    assertTesterPasses { new ClockAsUIntTester }
+  }
+}
-- 
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