From b187a0ce5269e735e7bd75620b4fd33f7ed27af5 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Fri, 15 Apr 2022 19:45:25 +0000 Subject: Enable Clock Invalidation (#2485) (#2487) Loosen restrictions on clocks to enable them to be connected to DontCare, i.e., be invalidated. Co-authored-by: Jack Koenig Signed-off-by: Schuyler Eldridge Co-authored-by: Jack Koenig (cherry picked from commit 5d8a0c8e406376f7ceda91273fb0fa7a646865aa) Co-authored-by: Schuyler Eldridge --- src/test/scala/chiselTests/InvalidateAPISpec.scala | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index 2c51e5d2..dbd353a0 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -228,4 +228,12 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare) firrtlOutput should include("is invalid") } + + property("a clock should be able to be connected to a DontCare") { + class ClockConnectedToDontCare extends Module { + val foo = IO(Output(Clock())) + foo := DontCare + } + myGenerateFirrtl(new ClockConnectedToDontCare) should include("foo is invalid") + } } -- cgit v1.2.3