From b0cc0c93a80aec5bed54cfb11923636c09b7e180 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 11:21:59 -0800
Subject: SInt conversion finished, everything builds again

---
 src/main/scala/chisel3/compatibility.scala         |  1 +
 src/main/scala/chisel3/package.scala               |  2 +-
 src/test/scala/chiselTests/AnnotatingExample.scala | 22 +++++++++++-----------
 src/test/scala/chiselTests/DriverSpec.scala        |  4 ++--
 4 files changed, 15 insertions(+), 14 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 69d02f9c..a9365ac3 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -147,6 +147,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
   implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
   implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
+  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 1161a1ca..1a100480 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -180,7 +180,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
   implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
   implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
-
+  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
diff --git a/src/test/scala/chiselTests/AnnotatingExample.scala b/src/test/scala/chiselTests/AnnotatingExample.scala
index 04228d6b..0be3ba59 100644
--- a/src/test/scala/chiselTests/AnnotatingExample.scala
+++ b/src/test/scala/chiselTests/AnnotatingExample.scala
@@ -24,8 +24,8 @@ import scala.util.DynamicVariable
 
 class SomeSubMod(param1: Int, param2: Int) extends Module {
   val io = new Bundle {
-    val in = UInt(INPUT, 16)
-    val out = SInt(OUTPUT, 32)
+    val in = Input(UInt(16.W))
+    val out = Output(SInt(32.W))
   }
   val annotate = MyBuilder.myDynamicContext.annotationMap
 
@@ -36,18 +36,18 @@ class SomeSubMod(param1: Int, param2: Int) extends Module {
 
 class AnnotatingExample extends Module {
   val io = new Bundle {
-    val a  = UInt(INPUT, 32)
-    val b  = UInt(INPUT, 32)
-    val e  = Bool(INPUT)
-    val z  = UInt(OUTPUT, 32)
-    val v  = Bool(OUTPUT)
+    val a  = Input(UInt(32.W))
+    val b  = Input(UInt(32.W))
+    val e  = Input(Bool())
+    val z  = Output(UInt(32.W))
+    val v  = Output(Bool())
     val bun = new Bundle {
-      val nested_1 = UInt(INPUT, 12)
-      val nested_2 = Bool(OUTPUT)
+      val nested_1 = Input(UInt(12.W))
+      val nested_2 = Output(Bool())
     }
   }
-  val x = Reg(UInt(width = 32))
-  val y = Reg(UInt(width = 32))
+  val x = Reg(UInt(32.W))
+  val y = Reg(UInt(32.W))
 
   val subModule1 = Module(new SomeSubMod(1, 2))
   val subModule2 = Module(new SomeSubMod(3, 4))
diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala
index 4f9619e3..d77dbaf1 100644
--- a/src/test/scala/chiselTests/DriverSpec.scala
+++ b/src/test/scala/chiselTests/DriverSpec.scala
@@ -8,8 +8,8 @@ import org.scalatest.{Matchers, FreeSpec}
 
 class DummyModule extends Module {
   val io = IO(new Bundle {
-    val in = UInt(INPUT, 1)
-    val out = UInt(OUTPUT, 1)
+    val in = Input(UInt(1.W))
+    val out = Output(UInt(1.W))
   })
   io.out := io.in
 }
-- 
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