From b08d9a2946cc27a360dabab3089095ea46786524 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Fri, 31 Jul 2015 16:46:40 -0700
Subject: Disallow dynamic bit range extraction

It wasn't correctly implemented, anyway.
---
 src/main/scala/Chisel/Core.scala | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 2e8feabc..f4a53d41 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -615,8 +615,6 @@ sealed abstract class Bits(dirArg: Direction, width: Int, lit: Option[LitArg]) e
   }
   final def apply(x: Int, y: Int): UInt =
     apply(BigInt(x), BigInt(y))
-  final def apply(x: UInt, y: UInt): UInt =
-    apply(x.litValue(), y.litValue())
 
   protected[Chisel] def unop(op: PrimOp, width: Int): this.type = {
     val d = cloneTypeWidth(width)
-- 
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