From a97fbfca90ba1a2604c89d3595a49d5260bd5f91 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Wed, 6 Sep 2017 13:24:20 -0700
Subject: Added API to get Verilog from Chisel (#676)

* Added API to get Verilog from Chisel

* Removed second emitVerilog implementation, added scaladoc
---
 src/main/scala/chisel3/Driver.scala | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index f3ba6534..d138bf1f 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -95,6 +95,18 @@ object Driver extends BackendCompilationUtilities {
 
   def emit[T <: RawModule](ir: Circuit): String = Emitter.emit(ir)
 
+  /** Elaborates the Module specified in the gen function into Verilog
+    *
+    *  @param gen a function that creates a Module hierarchy
+    *  @return the resulting String containing the design in Verilog
+    */
+  def emitVerilog[T <: RawModule](gen: => T): String = {
+    execute(Array[String](), { () => gen }) match {
+      case ChiselExecutionSuccess(_, _, Some(firrtl.FirrtlExecutionSuccess(_, verilog))) => verilog
+      case _ => sys.error("Cannot get Verilog!")
+    }
+  }
+
   def dumpFirrtl(ir: Circuit, optName: Option[File]): File = {
     val f = optName.getOrElse(new File(ir.name + ".fir"))
     val w = new FileWriter(f)
-- 
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