From 3fb693ea5209c402ca944086713684fa53e8c34c Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 5 Jan 2016 14:18:50 -0800
Subject: Scalastyle fixes - whitespace or comments only.

---
 src/main/scala/Chisel/Driver.scala                   |  2 +-
 src/test/scala/chiselTests/EnableShiftRegister.scala |  4 ++--
 src/test/scala/chiselTests/LFSR16.scala              |  6 +++---
 src/test/scala/chiselTests/MemorySearch.scala        |  4 ++--
 src/test/scala/chiselTests/Module.scala              | 18 +++++++++---------
 src/test/scala/chiselTests/Padding.scala             |  2 +-
 src/test/scala/chiselTests/Risc.scala                | 10 +++++-----
 src/test/scala/chiselTests/SIntOps.scala             |  4 ++--
 src/test/scala/chiselTests/Stack.scala               |  4 ++--
 src/test/scala/chiselTests/UIntOps.scala             |  8 ++++----
 10 files changed, 31 insertions(+), 31 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index cd88c302..900d53ce 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -84,7 +84,7 @@ trait BackendCompilationUtilities {
     val e = Process(s"./V${prefix}", dir) !
       ProcessLogger(line => {
         triggered = triggered || line.contains(assertionMsg)
-        System.out.println(line)
+        System.out.println(line)  // scalastyle:ignore regex
       })
     triggered
   }
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index b19fe3d9..6600df2a 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -29,7 +29,7 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
   for (t <- 0 until 16) {
     val in    = rnd.nextInt(16)
     val shift = rnd.nextInt(2)
-    println("SHIFT " + shift + " IN " + in)
+    println("SHIFT " + shift + " IN " + in)   // scalastyle:ignore regex
     poke(c.io.in,    in)
     poke(c.io.shift, shift)
     step(1)
@@ -44,7 +44,7 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
 */
 
 class EnableShiftRegisterSpec extends ChiselPropSpec {
-  
+
   property("EnableShiftRegister should elaborate") {
     elaborate { new EnableShiftRegister }
   }
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index dcc3a403..ed76a296 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -10,8 +10,8 @@ class LFSR16 extends Module {
     val out = UInt(OUTPUT, 16)
   }
   val res = Reg(init = UInt(1, 16))
-  when (io.inc) { 
-    val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) 
+  when (io.inc) {
+    val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
     res := nxt_res
   }
   io.out := res
@@ -37,7 +37,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) {
 //TODO: Use chisel.util version instead?
 
 class LFSRSpec extends ChiselPropSpec {
-  
+
   property("LFSR16 should elaborate") {
     elaborate { new LFSR16 }
   }
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index ec48c666..55b704a0 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -41,14 +41,14 @@ class MemorySearchTester(c: MemorySearch) extends Tester(c) {
       step(1)
     } while (peek(c.io.done) == 0 && t < maxT)
     val addr = peek(c.io.address).toInt
-    expect(addr == list.length || list(addr) == target, 
+    expect(addr == list.length || list(addr) == target,
            "LOOKING FOR " + target + " FOUND " + addr)
   }
 }
 */
 
 class MemorySearchSpec extends ChiselPropSpec {
-  
+
   property("MemorySearch should elaborate") {
     elaborate { new EnableShiftRegister }
   }
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 4191eea7..27fd5125 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -21,7 +21,7 @@ class ModuleVec(val n: Int) extends Module {
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
     pluses(i).in := io.ins(i)
-    io.outs(i)   := pluses(i).out 
+    io.outs(i)   := pluses(i).out
   }
 }
 
@@ -29,10 +29,10 @@ class ModuleVec(val n: Int) extends Module {
 class ModuleVecTester(c: ModuleVec) extends Tester(c) {
   for (t <- 0 until 16) {
     val test_ins = Array.fill(c.n){ rnd.nextInt(256) }
-    for (i <- 0 until c.n) 
+    for (i <- 0 until c.n)
       poke(c.io.ins(i), test_ins(i))
     step(1)
-    for (i <- 0 until c.n) 
+    for (i <- 0 until c.n)
       expect(c.io.outs(i), test_ins(i) + 1)
   }
 }
@@ -42,7 +42,7 @@ class ModuleWire extends Module {
   val io = new SimpleIO
   val inc = Wire(Module(new PlusOne).io)
   inc.in := io.in
-  io.out := inc.out 
+  io.out := inc.out
 }
 
 /*
@@ -61,27 +61,27 @@ class ModuleWhen extends Module {
     val s = new SimpleIO
     val en = Bool()
   }
-  when(io.en) { 
+  when(io.en) {
     val inc = Module(new PlusOne).io
     inc.in := io.s.in
-    io.s.out := inc.out 
+    io.s.out := inc.out
   } otherwise { io.s.out := io.s.in }
 }
 
 class ModuleSpec extends ChiselPropSpec {
-  
+
   property("ModuleVec should elaborate") {
     elaborate { new ModuleVec(2) }
   }
 
   ignore("ModuleVecTester should return the correct result") { }
-  
+
   property("ModuleWire should elaborate") {
     elaborate { new ModuleWire }
   }
 
   ignore("ModuleWireTester should return the correct result") { }
-  
+
   property("ModuleWhen should elaborate") {
     elaborate { new ModuleWhen }
   }
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 35a4c4a6..93a2c39f 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -32,7 +32,7 @@ class PadsTester(c: Pads) extends Tester(c) {
 */
 
 class PadderSpec extends ChiselPropSpec {
-  
+
   property("Padder should elaborate") {
     elaborate { new Padder }
   }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index b33b896b..ad5cf762 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -15,7 +15,7 @@ class Risc extends Module {
   val file = Mem(Bits(width = 32), 256)
   val code = Mem(Bits(width = 32), 256)
   val pc   = Reg(init=UInt(0, 8))
-  
+
   val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2)
 
   val inst = code(pc)
@@ -72,7 +72,7 @@ class RiscTester(c: Risc) extends Tester(c) {
   def I (op: UInt, rc: Int, ra: Int, rb: Int) = {
     // val cr = Cat(op, UInt(rc, 8), UInt(ra, 8), UInt(rb, 8)).litValue()
     val cr = op.litValue() << 24 | rc << 16 | ra << 8 | rb
-    println("I = " + cr)
+    println("I = " + cr)    // scalastyle:ignore regex
     cr
   }
 
@@ -81,10 +81,10 @@ class RiscTester(c: Risc) extends Tester(c) {
                    I(c.add_op,   1, 1, 1), // r1 <- r1 + r1
                    I(c.add_op, 255, 1, 0)) // rh <- r1
   wr(0, 0) // skip reset
-  for (addr <- 0 until app.length) 
+  for (addr <- 0 until app.length)
     wr(addr, app(addr))
   def dump(k: Int) {
-    println("K = " + k)
+    println("K = " + k)  // scalastyle:ignore regex
     peek(c.ra)
     peek(c.rb)
     peek(c.rc)
@@ -110,7 +110,7 @@ class RiscTester(c: Risc) extends Tester(c) {
 */
 
 class RiscSpec extends ChiselPropSpec {
-  
+
   property("Risc should elaborate") {
     elaborate { new Risc }
   }
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 4a87a2d2..0835fb4d 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -29,7 +29,7 @@ class SIntOps extends Module {
 
   io.addout := a +% b
   io.subout := a -% b
-  // TODO: 
+  // TODO:
   //io.timesout := (a * b)(15, 0)
   //io.divout := a / Mux(b === SInt(0), SInt(1), b)
   //io.divout := (a / b)(15, 0)
@@ -83,7 +83,7 @@ class SIntOpsTester(c: SIntOps) extends Tester(c) {
 */
 
 class SIntOpsSpec extends ChiselPropSpec {
-  
+
   property("SIntOps should elaborate") {
     elaborate { new SIntOps }
   }
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 0110550d..600934aa 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -14,7 +14,7 @@ class ChiselStack(val depth: Int) extends Module {
   }
 
   val stack_mem = Mem(UInt(width = 32), depth)
-  val sp        = Reg(init = UInt(0, width = log2Up(depth+1)))
+  val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
   val out       = Reg(init = UInt(0, width = 32))
 
   when (io.en) {
@@ -66,7 +66,7 @@ class StackTester(c: Stack) extends Tester(c) {
 */
 
 class StackSpec extends ChiselPropSpec {
-  
+
   property("Stack should elaborate") {
     elaborate { new ChiselStack(2) }
   }
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 9affb511..24cb8fc9 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -32,7 +32,7 @@ class UIntOps extends Module {
   io.timesout := (a * b)(15, 0)
   io.divout := a / Mux(b === UInt(0), UInt(1), b)
   // io.modout := a % b
-  // TODO: 
+  // TODO:
   io.modout := UInt(0)
   io.lshiftout := (a << b(3, 0))(15, 0)
   io.rshiftout := a >> b
@@ -48,13 +48,13 @@ class UIntOps extends Module {
 class UIntOpsTester(c: UIntOps) extends Tester(c) {
   def uintExpect(d: Bits, x: BigInt) {
     val mask = (1 << 16) - 1
-    println(" E = " + x + " X&M = " + (x & mask))
+    println(" E = " + x + " X&M = " + (x & mask))  // scalastyle:ignore regex
     expect(d, x & mask)
   }
   for (t <- 0 until 16) {
     val test_a = rnd.nextInt(1 << 16)
     val test_b = rnd.nextInt(1 << 16)
-    println("A = " + test_a + " B = " + test_b)
+    println("A = " + test_a + " B = " + test_b)  // scalastyle:ignore regex
     poke(c.io.a, test_a)
     poke(c.io.b, test_b)
     step(1)
@@ -99,7 +99,7 @@ class UIntOpsSpec extends ChiselPropSpec with Matchers {
   property("Bools cannot be created from >1 bit UInts") {
     a [Exception] should be thrownBy { elaborate(new BadBoolConversion) }
   }
-  
+
   property("UIntOps should elaborate") {
     elaborate { new UIntOps }
   }
-- 
cgit v1.2.3


From 6d37cc8b9d731fa4c844f097b11057c46771961b Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jan 2016 08:25:41 -0800
Subject: Don't silence legitimate warnings - these println()s should be
 controlled by a diagnostic/debugging infrastructure.

---
 src/main/scala/Chisel/Driver.scala       | 2 +-
 src/test/scala/chiselTests/UIntOps.scala | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index 900d53ce..cd88c302 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -84,7 +84,7 @@ trait BackendCompilationUtilities {
     val e = Process(s"./V${prefix}", dir) !
       ProcessLogger(line => {
         triggered = triggered || line.contains(assertionMsg)
-        System.out.println(line)  // scalastyle:ignore regex
+        System.out.println(line)
       })
     triggered
   }
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 24cb8fc9..bb0b0f06 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -48,13 +48,13 @@ class UIntOps extends Module {
 class UIntOpsTester(c: UIntOps) extends Tester(c) {
   def uintExpect(d: Bits, x: BigInt) {
     val mask = (1 << 16) - 1
-    println(" E = " + x + " X&M = " + (x & mask))  // scalastyle:ignore regex
+    println(" E = " + x + " X&M = " + (x & mask))
     expect(d, x & mask)
   }
   for (t <- 0 until 16) {
     val test_a = rnd.nextInt(1 << 16)
     val test_b = rnd.nextInt(1 << 16)
-    println("A = " + test_a + " B = " + test_b)  // scalastyle:ignore regex
+    println("A = " + test_a + " B = " + test_b)
     poke(c.io.a, test_a)
     poke(c.io.b, test_b)
     step(1)
-- 
cgit v1.2.3


From 2a3b5fc59c732d85aafda78f2fb21368dc4a5660 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:18:49 -0800
Subject: New FIRRTL syntax for reg

---
 src/main/scala/Chisel/Reg.scala                     | 10 ++++++----
 src/main/scala/Chisel/internal/firrtl/Emitter.scala |  3 ++-
 src/main/scala/Chisel/internal/firrtl/IR.scala      |  3 ++-
 3 files changed, 10 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Reg.scala b/src/main/scala/Chisel/Reg.scala
index f166c84b..e69061c5 100644
--- a/src/main/scala/Chisel/Reg.scala
+++ b/src/main/scala/Chisel/Reg.scala
@@ -45,10 +45,12 @@ object Reg {
     // to resolve all use cases. If the type inferencer / implicit resolution
     // system improves, this may be changed.
     val x = makeType(t, next, init)
-    val (resetEn, resetVal) =
-      if (init != null) (Node(x._parent.get.reset), init)
-      else (ULit(0, Width(1)), x)
-    pushCommand(DefRegister(x, Node(x._parent.get.clock), resetEn, resetVal.ref)) // TODO multi-clock
+    val clock = Node(x._parent.get.clock) // TODO multi-clock
+    if (init == null) {
+      pushCommand(DefReg(x, clock))
+    } else {
+      pushCommand(DefRegInit(x, clock, Node(x._parent.get.reset), init.ref))
+    }
     if (next != null) {
       x := next
     }
diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/Chisel/internal/firrtl/Emitter.scala
index 8597454a..2765efa8 100644
--- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ b/src/main/scala/Chisel/internal/firrtl/Emitter.scala
@@ -12,7 +12,8 @@ private class Emitter(circuit: Circuit) {
     case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_ + ", " + _)})"
     case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
     case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}"
-    case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}"
+    case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}"
+    case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
     case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]"
     case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]"
     case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index 5612f1af..ec9b9e36 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -149,7 +149,8 @@ abstract class Definition extends Command {
 }
 case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefWire(id: Data) extends Definition
-case class DefRegister(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
+case class DefReg(id: Data, clock: Arg) extends Definition
+case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
 case class DefMemory(id: HasId, t: Data, size: Int) extends Definition
 case class DefSeqMemory(id: HasId, t: Data, size: Int) extends Definition
 case class DefMemPort[T <: Data](id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
-- 
cgit v1.2.3


From 71f45a6df99cb86ada1ad9d091a38e01b698a863 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:19:23 -0800
Subject: In FIRRTL, bitwise operators return UInt

---
 src/main/scala/Chisel/Bits.scala | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index fbc1586f..3974d05d 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -92,9 +92,6 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   private[Chisel] def redop(op: PrimOp): Bool =
     pushOp(DefPrim(Bool(), op, this.ref))
 
-  /** Returns this wire bitwise-inverted. */
-  def unary_~ : this.type = unop(cloneTypeWidth(width), BitNotOp)
-
   /** Returns this wire zero padded up to the specified width.
     *
     * @note for SInts only, this does sign extension
@@ -292,6 +289,9 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
   def | (other: UInt): UInt = binop(UInt(this.width max other.width), BitOrOp, other)
   def ^ (other: UInt): UInt = binop(UInt(this.width max other.width), BitXorOp, other)
 
+  /** Returns this wire bitwise-inverted. */
+  def unary_~ : UInt = unop(UInt(width = width), BitNotOp)
+
   // REVIEW TODO: Can this be defined on Bits?
   def orR: Bool = this != UInt(0)
   def andR: Bool = ~this === UInt(0)
@@ -422,9 +422,12 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
   def / (other: SInt): SInt = binop(SInt(this.width), DivideOp, other)
   def % (other: SInt): SInt = binop(SInt(this.width), ModOp, other)
 
-  def & (other: SInt): SInt = binop(SInt(this.width max other.width), BitAndOp, other)
-  def | (other: SInt): SInt = binop(SInt(this.width max other.width), BitOrOp, other)
-  def ^ (other: SInt): SInt = binop(SInt(this.width max other.width), BitXorOp, other)
+  def & (other: SInt): SInt = binop(UInt(this.width max other.width), BitAndOp, other).asSInt
+  def | (other: SInt): SInt = binop(UInt(this.width max other.width), BitOrOp, other).asSInt
+  def ^ (other: SInt): SInt = binop(UInt(this.width max other.width), BitXorOp, other).asSInt
+
+  /** Returns this wire bitwise-inverted. */
+  def unary_~ : SInt = unop(UInt(width = width), BitNotOp).asSInt
 
   def < (other: SInt): Bool = compop(LessOp, other)
   def > (other: SInt): Bool = compop(GreaterOp, other)
@@ -490,6 +493,9 @@ sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Wi
   def | (other: Bool): Bool = binop(Bool(), BitOrOp, other)
   def ^ (other: Bool): Bool = binop(Bool(), BitXorOp, other)
 
+  /** Returns this wire bitwise-inverted. */
+  override def unary_~ : Bool = unop(Bool(), BitNotOp)
+
   /** Outputs the logical OR of two Bools.
    */
   def || (that: Bool): Bool = this | that
-- 
cgit v1.2.3


From 22d302ad066d8a073e44289ba4876a165ea56b05 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:20:00 -0800
Subject: Remove unsupported FIRRTL node bit(); use bits()

---
 src/main/scala/Chisel/Bits.scala               | 2 +-
 src/main/scala/Chisel/internal/firrtl/IR.scala | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 3974d05d..6062f2de 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -39,7 +39,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     if (isLit()) {
       Bool(((litValue() >> x.toInt) & 1) == 1)
     } else {
-      pushOp(DefPrim(Bool(), BitSelectOp, this.ref, ILit(x)))
+      pushOp(DefPrim(Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
     }
   }
 
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index ec9b9e36..1bc3ad89 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -25,7 +25,6 @@ object PrimOp {
   val BitXorOp = PrimOp("xor")
   val BitNotOp = PrimOp("not")
   val ConcatOp = PrimOp("cat")
-  val BitSelectOp = PrimOp("bit")
   val BitsExtractOp = PrimOp("bits")
   val LessOp = PrimOp("lt")
   val LessEqOp = PrimOp("leq")
-- 
cgit v1.2.3


From c9dd94dd6968cba5ecd44fee6df3071cb7a25a9c Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:20:44 -0800
Subject: Use FIRRTL node rem, not mod, for %

---
 src/main/scala/Chisel/Bits.scala               | 4 ++--
 src/main/scala/Chisel/internal/firrtl/IR.scala | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 6062f2de..4a9a6074 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -283,7 +283,7 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
   def * (other: UInt): UInt = binop(UInt(this.width + other.width), TimesOp, other)
   def * (other: SInt): SInt = other * this
   def / (other: UInt): UInt = binop(UInt(this.width), DivideOp, other)
-  def % (other: UInt): UInt = binop(UInt(this.width), ModOp, other)
+  def % (other: UInt): UInt = binop(UInt(this.width), RemOp, other)
 
   def & (other: UInt): UInt = binop(UInt(this.width max other.width), BitAndOp, other)
   def | (other: UInt): UInt = binop(UInt(this.width max other.width), BitOrOp, other)
@@ -420,7 +420,7 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
   def * (other: SInt): SInt = binop(SInt(this.width + other.width), TimesOp, other)
   def * (other: UInt): SInt = binop(SInt(this.width + other.width), TimesOp, other)
   def / (other: SInt): SInt = binop(SInt(this.width), DivideOp, other)
-  def % (other: SInt): SInt = binop(SInt(this.width), ModOp, other)
+  def % (other: SInt): SInt = binop(SInt(this.width), RemOp, other)
 
   def & (other: SInt): SInt = binop(UInt(this.width max other.width), BitAndOp, other).asSInt
   def | (other: SInt): SInt = binop(UInt(this.width max other.width), BitOrOp, other).asSInt
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index 1bc3ad89..cc80e3aa 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -15,7 +15,7 @@ object PrimOp {
   val SubModOp = PrimOp("subw")
   val TimesOp = PrimOp("mul")
   val DivideOp = PrimOp("div")
-  val ModOp = PrimOp("mod")
+  val RemOp = PrimOp("rem")
   val ShiftLeftOp = PrimOp("shl")
   val ShiftRightOp = PrimOp("shr")
   val DynamicShiftLeftOp = PrimOp("dshl")
-- 
cgit v1.2.3


From bce4a96934fe8575b71769f2e52a2b75a068d34d Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 27 Jan 2016 15:20:58 -0800
Subject: Use FIRRTL nodes add+tail instead of addw

---
 src/main/scala/Chisel/Bits.scala               | 26 ++++++++++++++++++++++----
 src/main/scala/Chisel/internal/firrtl/IR.scala |  4 ++--
 2 files changed, 24 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 4a9a6074..b800644d 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -29,6 +29,24 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
 
   override def <> (that: Data): Unit = this := that
 
+  def tail(n: Int): UInt = {
+    val w = width match {
+      case KnownWidth(x) =>
+        require(x >= n, s"Can't tail($n) for width $x < $n")
+        Width(x - n)
+      case UnknownWidth() => Width()
+    }
+    binop(UInt(width = w), TailOp, n)
+  }
+
+  def head(n: Int): UInt = {
+    width match {
+      case KnownWidth(x) => require(x >= n, s"Can't head($n) for width $x < $n")
+      case UnknownWidth() =>
+    }
+    binop(UInt(width = n), HeadOp, n)
+  }
+
   /** Returns the specified bit on this wire as a [[Bool]], statically
     * addressed.
     */
@@ -276,10 +294,10 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
   def unary_-% : UInt = UInt(0) -% this
   def +& (other: UInt): UInt = binop(UInt((this.width max other.width) + 1), AddOp, other)
   def + (other: UInt): UInt = this +% other
-  def +% (other: UInt): UInt = binop(UInt(this.width max other.width), AddModOp, other)
+  def +% (other: UInt): UInt = (this +& other) tail 1
   def -& (other: UInt): UInt = binop(UInt((this.width max other.width) + 1), SubOp, other)
   def - (other: UInt): UInt = this -% other
-  def -% (other: UInt): UInt = binop(UInt(this.width max other.width), SubModOp, other)
+  def -% (other: UInt): UInt = (this -& other) tail 1
   def * (other: UInt): UInt = binop(UInt(this.width + other.width), TimesOp, other)
   def * (other: SInt): SInt = other * this
   def / (other: UInt): UInt = binop(UInt(this.width), DivideOp, other)
@@ -410,13 +428,13 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
   /** add (default - no growth) operator */
   def + (other: SInt): SInt = this +% other
   /** add (no growth) operator */
-  def +% (other: SInt): SInt = binop(SInt(this.width max other.width), AddModOp, other)
+  def +% (other: SInt): SInt = (this +& other).tail(1).asSInt
   /** subtract (width +1) operator */
   def -& (other: SInt): SInt = binop(SInt((this.width max other.width) + 1), SubOp, other)
   /** subtract (default - no growth) operator */
   def - (other: SInt): SInt = this -% other
   /** subtract (no growth) operator */
-  def -% (other: SInt): SInt = binop(SInt(this.width max other.width), SubModOp, other)
+  def -% (other: SInt): SInt = (this -& other).tail(1).asSInt
   def * (other: SInt): SInt = binop(SInt(this.width + other.width), TimesOp, other)
   def * (other: UInt): SInt = binop(SInt(this.width + other.width), TimesOp, other)
   def / (other: SInt): SInt = binop(SInt(this.width), DivideOp, other)
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index cc80e3aa..3e923366 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -10,9 +10,9 @@ case class PrimOp(val name: String) {
 
 object PrimOp {
   val AddOp = PrimOp("add")
-  val AddModOp = PrimOp("addw")
   val SubOp = PrimOp("sub")
-  val SubModOp = PrimOp("subw")
+  val TailOp = PrimOp("tail")
+  val HeadOp = PrimOp("head")
   val TimesOp = PrimOp("mul")
   val DivideOp = PrimOp("div")
   val RemOp = PrimOp("rem")
-- 
cgit v1.2.3


From 41674d5e130f64d7489fdb8583b8f4ad88b64aeb Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 28 Jan 2016 12:05:03 -0800
Subject: Use FIRRTL is invalid construct

---
 src/main/scala/Chisel/Data.scala                    | 10 +---------
 src/main/scala/Chisel/Mem.scala                     |  7 +++++--
 src/main/scala/Chisel/Module.scala                  |  8 ++------
 src/main/scala/Chisel/internal/firrtl/Emitter.scala |  2 +-
 src/main/scala/Chisel/internal/firrtl/IR.scala      |  2 +-
 5 files changed, 10 insertions(+), 19 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Data.scala b/src/main/scala/Chisel/Data.scala
index 1011fe47..0ac3ee32 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/src/main/scala/Chisel/Data.scala
@@ -119,7 +119,7 @@ object Wire {
     if (init != null) {
       x := init
     } else {
-      x.flatten.foreach(e => e := e.fromInt(0))
+      pushCommand(DefInvalid(x.ref))
     }
     x
   }
@@ -141,11 +141,3 @@ sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
     case _ => this badConnect that
   }
 }
-
-// TODO: check with FIRRTL specs, how much official implementation flexibility
-// is there?
-/** A source of garbage data, used to initialize Wires to a don't-care value. */
-private object Poison extends Command {
-  def apply[T <: Data](t: T): T =
-    pushCommand(DefPoison(t.cloneType)).id
-}
diff --git a/src/main/scala/Chisel/Mem.scala b/src/main/scala/Chisel/Mem.scala
index 3bbb1151..21284607 100644
--- a/src/main/scala/Chisel/Mem.scala
+++ b/src/main/scala/Chisel/Mem.scala
@@ -113,6 +113,9 @@ object SeqMem {
   * result is undefined (unlike Vec, where the last assignment wins)
   */
 sealed class SeqMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
-  def read(addr: UInt, enable: Bool): T =
-    read(Mux(enable, addr, Poison(addr)))
+  def read(addr: UInt, enable: Bool): T = {
+    val a = Wire(UInt())
+    when (enable) { a := addr }
+    read(a)
+  }
 }
diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala
index 2a0f29db..463c2f81 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/src/main/scala/Chisel/Module.scala
@@ -20,16 +20,12 @@ object Module {
   def apply[T <: Module](bc: => T): T = {
     val parent = dynamicContext.currentModule
     val m = bc.setRefs()
-    // init module outputs
-    m._commands prependAll (for (p <- m.io.flatten; if p.dir == OUTPUT)
-      yield Connect(p.lref, p.fromInt(0).ref))
+    m._commands.prepend(DefInvalid(m.io.ref)) // init module outputs
     dynamicContext.currentModule = parent
     val ports = m.computePorts
     Builder.components += Component(m, m.name, ports, m._commands)
     pushCommand(DefInstance(m, ports))
-    // init instance inputs
-    for (p <- m.io.flatten; if p.dir == INPUT)
-      p := p.fromInt(0)
+    pushCommand(DefInvalid(m.io.ref)) // init instance inputs
     m.connectImplicitIOs()
   }
 }
diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/Chisel/internal/firrtl/Emitter.scala
index 2765efa8..13d9fa8f 100644
--- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ b/src/main/scala/Chisel/internal/firrtl/Emitter.scala
@@ -11,7 +11,6 @@ private class Emitter(circuit: Circuit) {
   private def emit(e: Command, ctx: Component): String = e match {
     case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_ + ", " + _)})"
     case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
-    case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}"
     case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}"
     case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
     case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]"
@@ -21,6 +20,7 @@ private class Emitter(circuit: Circuit) {
     case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
     case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})"
     case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})"""
+    case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
     case e: DefInstance => {
       val modName = moduleMap.getOrElse(e.id.name, e.id.name)
       s"inst ${e.name} of $modName"
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index 3e923366..7bb273c0 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -147,6 +147,7 @@ abstract class Definition extends Command {
   def name: String = id.getRef.name
 }
 case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
+case class DefInvalid(arg: Arg) extends Command
 case class DefWire(id: Data) extends Definition
 case class DefReg(id: Data, clock: Arg) extends Definition
 case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
@@ -154,7 +155,6 @@ case class DefMemory(id: HasId, t: Data, size: Int) extends Definition
 case class DefSeqMemory(id: HasId, t: Data, size: Int) extends Definition
 case class DefMemPort[T <: Data](id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
 case class DefInstance(id: Module, ports: Seq[Port]) extends Definition
-case class DefPoison[T <: Data](id: T) extends Definition
 case class WhenBegin(pred: Arg) extends Command
 case class WhenEnd() extends Command
 case class Connect(loc: Node, exp: Arg) extends Command
-- 
cgit v1.2.3