From a689c7c0dd336fe0b9db6171786993b190a700f8 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Wed, 8 Jun 2022 20:09:45 +0000 Subject: Added migration for inferModuleReset (#2571) (#2573) Co-authored-by: Jack Koenig (cherry picked from commit 3c6c044b6bdee850ad9ba375324abaf3813c557d) Co-authored-by: Adam Izraelevitz --- .../chiselTests/MigrateCompileOptionsSpec.scala | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 src/test/scala/chiselTests/MigrateCompileOptionsSpec.scala (limited to 'src') diff --git a/src/test/scala/chiselTests/MigrateCompileOptionsSpec.scala b/src/test/scala/chiselTests/MigrateCompileOptionsSpec.scala new file mode 100644 index 00000000..3757c360 --- /dev/null +++ b/src/test/scala/chiselTests/MigrateCompileOptionsSpec.scala @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chiselTests + +import chisel3.stage.ChiselStage + +import org.scalatestplus.scalacheck.ScalaCheckDrivenPropertyChecks + +class MigrateCompileOptionsSpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyChecks with Utils { + import Chisel.{defaultCompileOptions => _, _} + import chisel3.RequireSyncReset + + behavior.of("Migrating infer resets") + + val migrateIR = new chisel3.CompileOptions { + val connectFieldsMustMatch = false + val declaredTypeMustBeUnbound = false + val dontTryConnectionsSwapped = false + val dontAssumeDirectionality = false + val checkSynthesizable = false + val explicitInvalidate = false + val inferModuleReset = false + + override val migrateInferModuleReset = true + } + + it should "error if migrating, but not extended RequireSyncReset" in { + implicit val options = migrateIR + class Foo extends Module { + val io = new Bundle {} + } + intercept[Exception] { + ChiselStage.elaborate(new Foo) + } + } + it should "not error if migrating, and you mix with RequireSyncReset" in { + implicit val options = migrateIR + class Foo extends Module with RequireSyncReset { + val io = new Bundle {} + } + ChiselStage.elaborate(new Foo) + } +} -- cgit v1.2.3