From 9e6b8862c87139a44cb4766abe86ee4a5fd93b02 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 18 Sep 2015 13:53:01 -0700 Subject: Improve IR class hierarchy - Rename Alias to Node to match FIRRTL notion - Remove poorly-named Immediate and replace root of hierarchy with Arg --- src/main/scala/Chisel/Builder.scala | 12 ++++++------ src/main/scala/Chisel/Core.scala | 12 ++++++------ src/main/scala/Chisel/IR.scala | 27 +++++++++++---------------- 3 files changed, 23 insertions(+), 28 deletions(-) (limited to 'src') diff --git a/src/main/scala/Chisel/Builder.scala b/src/main/scala/Chisel/Builder.scala index 3cce042f..6b055c68 100644 --- a/src/main/scala/Chisel/Builder.scala +++ b/src/main/scala/Chisel/Builder.scala @@ -41,7 +41,7 @@ private[Chisel] trait HasId { private[Chisel] val _refMap = Builder.globalRefMap private[Chisel] val _id = Builder.idGen.next - private[Chisel] def setRef(imm: Immediate) = _refMap.setRef(this, imm) + private[Chisel] def setRef(imm: Arg) = _refMap.setRef(this, imm) private[Chisel] def setRef(name: String) = _refMap.setRef(this, name) private[Chisel] def setRef(parent: HasId, name: String) = _refMap.setField(parent, this, name) private[Chisel] def setRef(parent: HasId, index: Int) = _refMap.setIndex(parent, this, index) @@ -49,21 +49,21 @@ private[Chisel] trait HasId { } class RefMap { - private val _refmap = new HashMap[Long,Immediate]() + private val _refmap = new HashMap[Long,Arg]() - private[Chisel] def setRef(id: HasId, ref: Immediate): Unit = + private[Chisel] def setRef(id: HasId, ref: Arg): Unit = _refmap(id._id) = ref private[Chisel] def setRef(id: HasId, name: String): Unit = if (!_refmap.contains(id._id)) setRef(id, Ref(name)) private[Chisel] def setField(parentid: HasId, id: HasId, name: String): Unit = - _refmap(id._id) = Slot(Alias(parentid), name) + _refmap(id._id) = Slot(Node(parentid), name) private[Chisel] def setIndex(parentid: HasId, id: HasId, index: Int): Unit = - _refmap(id._id) = Index(Alias(parentid), index) + _refmap(id._id) = Index(Node(parentid), index) - def apply(id: HasId): Immediate = _refmap(id._id) + def apply(id: HasId): Arg = _refmap(id._id) } private class DynamicContext { diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index 2284ff16..e0e2dd6a 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -68,7 +68,7 @@ abstract class Data(dirArg: Direction) extends HasId { pushCommand(Connect(this.lref, that.ref)) private[Chisel] def bulkConnect(that: Data): Unit = pushCommand(BulkConnect(this.lref, that.lref)) - private[Chisel] def lref: Alias = Alias(this) + private[Chisel] def lref: Node = Node(this) private[Chisel] def ref: Arg = if (isLit) litArg.get else lref private[Chisel] def cloneTypeWidth(width: Width): this.type private[Chisel] def toType: String @@ -122,7 +122,7 @@ object Reg { def apply[T <: Data](t: T = null, next: T = null, init: T = null): T = { val x = makeType(t, next, init) - pushCommand(DefRegister(x, Alias(x._parent.get.clock), Alias(x._parent.get.reset))) // TODO multi-clock + pushCommand(DefRegister(x, Node(x._parent.get.clock), Node(x._parent.get.reset))) // TODO multi-clock if (init != null) pushCommand(ConnectInit(x.lref, init.ref)) if (next != null) @@ -136,7 +136,7 @@ object Mem { def apply[T <: Data](t: T, size: Int): Mem[T] = { val mt = t.cloneType val mem = new Mem(mt, size) - pushCommand(DefMemory(mem, mt, size, Alias(mt._parent.get.clock))) // TODO multi-clock + pushCommand(DefMemory(mem, mt, size, Node(mt._parent.get.clock))) // TODO multi-clock mem } } @@ -144,7 +144,7 @@ object Mem { sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId with VecLike[T] { def apply(idx: Int): T = apply(UInt(idx)) def apply(idx: UInt): T = - pushCommand(DefAccessor(t.cloneType, Alias(this), NO_DIR, idx.ref)).id + pushCommand(DefAccessor(t.cloneType, Node(this), NO_DIR, idx.ref)).id def read(idx: UInt): T = apply(idx) def write(idx: UInt, data: T): Unit = apply(idx) := data @@ -161,7 +161,7 @@ object SeqMem { def apply[T <: Data](t: T, size: Int): SeqMem[T] = { val mt = t.cloneType val mem = new SeqMem(mt, size) - pushCommand(DefSeqMemory(mem, mt, size, Alias(mt._parent.get.clock))) // TODO multi-clock + pushCommand(DefSeqMemory(mem, mt, size, Node(mt._parent.get.clock))) // TODO multi-clock mem } } @@ -237,7 +237,7 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) def apply(idx: UInt): T = { val x = gen - pushCommand(DefAccessor(x, Alias(this), NO_DIR, idx.ref)) + pushCommand(DefAccessor(x, Node(this), NO_DIR, idx.ref)) x } diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala index 8b642902..d76683ec 100644 --- a/src/main/scala/Chisel/IR.scala +++ b/src/main/scala/Chisel/IR.scala @@ -38,19 +38,14 @@ object PrimOp { val AsSIntOp = PrimOp("asSInt") } -abstract class Immediate { +abstract class Arg { def fullName(ctx: Component): String = name def name: String } -abstract class Arg extends Immediate { - def name: String -} - -case class Alias(id: HasId) extends Arg { +case class Node(id: HasId) extends Arg { override def fullName(ctx: Component) = id.getRef.fullName(ctx) def name = id.getRef.name - def emit: String = s"Alias($id)" } abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { @@ -81,17 +76,17 @@ case class SLit(n: BigInt, w: Width) extends LitArg(n, w) { def minWidth = 1 + n.bitLength } -case class Ref(name: String) extends Immediate -case class ModuleIO(mod: Module, name: String) extends Immediate { +case class Ref(name: String) extends Arg +case class ModuleIO(mod: Module, name: String) extends Arg { override def fullName(ctx: Component) = if (mod eq ctx.id) name else s"${mod.getRef.name}.$name" } -case class Slot(imm: Alias, name: String) extends Immediate { +case class Slot(imm: Node, name: String) extends Arg { override def fullName(ctx: Component) = if (imm.fullName(ctx).isEmpty) name else s"${imm.fullName(ctx)}.${name}" } -case class Index(imm: Immediate, value: Int) extends Immediate { +case class Index(imm: Arg, value: Int) extends Arg { def name = s"[$value]" override def fullName(ctx: Component) = s"${imm.fullName(ctx)}[$value]" } @@ -143,16 +138,16 @@ case class DefWire(id: Data) extends Definition case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition case class DefSeqMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition -case class DefAccessor[T <: Data](id: T, source: Alias, direction: Direction, index: Arg) extends Definition +case class DefAccessor[T <: Data](id: T, source: Node, direction: Direction, index: Arg) extends Definition case class DefInstance(id: Module, ports: Seq[Port]) extends Definition case class DefPoison[T <: Data](id: T) extends Definition case class WhenBegin(pred: Arg) extends Command case class WhenElse() extends Command case class WhenEnd() extends Command -case class Connect(loc: Alias, exp: Arg) extends Command -case class BulkConnect(loc1: Alias, loc2: Alias) extends Command -case class ConnectInit(loc: Alias, exp: Arg) extends Command -case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Immediate +case class Connect(loc: Node, exp: Arg) extends Command +case class BulkConnect(loc1: Node, loc2: Node) extends Command +case class ConnectInit(loc: Node, exp: Arg) extends Command +case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg case class Port(id: Data, dir: Direction) case class Circuit(name: String, components: Seq[Component], refMap: RefMap, parameterDump: ParameterDump) { -- cgit v1.2.3