From 834dd38ea1bc6c6ac5453d8e73893910a5dcc968 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 20 Aug 2015 23:26:04 -0700
Subject: Simplify I/O zero-initialization

---
 src/main/scala/Chisel/Core.scala    |  6 ++++++
 src/main/scala/Chisel/Emitter.scala | 14 +-------------
 2 files changed, 7 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 60b22830..8495a5d4 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -781,10 +781,16 @@ object Module {
     paramsScope(currParams) {
       val parent = dynamicContext.currentModule
       val m = bc.setRefs()
+      // init module outputs
+      m._commands prependAll (for (p <- m.io.flatten; if p.dir == OUTPUT)
+        yield Connect(p.lref, p.fromInt(0).ref))
       dynamicContext.currentModule = parent
       val ports = m.computePorts
       Builder.components += Component(m, m.name, ports, m._commands)
       pushCommand(DefInstance(m, ports))
+      // init instance inputs
+      for (p <- m.io.flatten; if p.dir == INPUT)
+        p := p.fromInt(0)
       m
     }.connectImplicitIOs()
   }
diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala
index d384a536..fd271aa4 100644
--- a/src/main/scala/Chisel/Emitter.scala
+++ b/src/main/scala/Chisel/Emitter.scala
@@ -19,11 +19,7 @@ private class Emitter(circuit: Circuit) {
     case e: ConnectInit => s"onreset ${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
     case e: DefInstance => {
       val modName = moduleMap.getOrElse(e.id.name, e.id.name)
-      val res = new StringBuilder(s"inst ${e.name} of $modName")
-      res ++= newline
-      for (p <- e.ports; x <- initPort(p, INPUT, ctx))
-        res ++= newline + x
-      res.toString
+     s"inst ${e.name} of $modName"
     }
 
     case w: WhenBegin =>
@@ -36,20 +32,12 @@ private class Emitter(circuit: Circuit) {
       unindent()
       "skip"
   }
-  private def initPort(p: Data, dir: Direction, ctx: Component) = {
-    for (x <- p.flatten; if x.dir == dir)
-      yield s"${x.getRef.fullName(ctx)} := ${x.makeLit(0).name}"
-  }
-
   private def emitBody(m: Component) = {
     val me = new StringBuilder
     withIndent {
       for (p <- m.ports)
         me ++= newline + emitPort(p)
       me ++= newline
-      for (p <- m.ports; x <- initPort(p, OUTPUT, m))
-        me ++= newline + x
-      me ++= newline
       for (cmd <- m.commands)
         me ++= newline + emit(cmd, m)
       me ++= newline
-- 
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