From 81845909248aaceef427e73924211931e0dc60dc Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Thu, 26 Mar 2020 16:27:24 -0400
Subject: Set StageError cause in ChiselStage (#1382)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>---
 src/main/scala/chisel3/stage/ChiselStage.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index ea40e92b..0068d86f 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -46,7 +46,7 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
         .augmentString(stackTrace)
         .lines
         .foreach(line => println(s"${ErrorLog.errTag} $line")) // scalastyle:ignore regex
-      throw new StageError()
+      throw new StageError(cause=ce)
   }
 
   /** Convert a Chisel module to a CHIRRTL string
-- 
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