From 802cfc4405c28ae212a955a92c7a6ad2d2b6f0c2 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 17 Aug 2017 11:26:29 -0700 Subject: Make Reset a trait (#672) Bool implements Reset. Compatibility package includes an implicit conversion from Reset to Bool.--- src/main/scala/chisel3/compatibility.scala | 3 + src/main/scala/chisel3/testers/BasicTester.scala | 2 +- src/test/scala/chiselTests/AsTypeOfTester.scala | 76 ++++++++++++++++++++++ src/test/scala/chiselTests/Assert.scala | 6 +- src/test/scala/chiselTests/CompatibilitySpec.scala | 12 ++++ src/test/scala/chiselTests/FromBitsTester.scala | 67 ------------------- src/test/scala/chiselTests/MultiClockSpec.scala | 2 +- 7 files changed, 96 insertions(+), 72 deletions(-) create mode 100644 src/test/scala/chiselTests/AsTypeOfTester.scala delete mode 100644 src/test/scala/chiselTests/FromBitsTester.scala (limited to 'src') diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index e169fb8f..4d2d9311 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -195,6 +195,9 @@ package object Chisel { // scalastyle:ignore package.object.name type Bool = chisel3.core.Bool object Bool extends BoolFactory val Mux = chisel3.core.Mux + type Reset = chisel3.core.Reset + + implicit def resetToBool(reset: Reset): Bool = reset.toBool import chisel3.core.Param abstract class BlackBox(params: Map[String, Param] = Map.empty[String, Param]) extends chisel3.core.BlackBox(params) { diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala index bd7d4027..6d1a4913 100644 --- a/src/main/scala/chisel3/testers/BasicTester.scala +++ b/src/main/scala/chisel3/testers/BasicTester.scala @@ -25,7 +25,7 @@ class BasicTester extends Module() { */ def stop()(implicit sourceInfo: SourceInfo) { // TODO: rewrite this using library-style SourceInfo passing. - when (!reset) { + when (!reset.toBool) { pushCommand(Stop(sourceInfo, Node(clock), 0)) } } diff --git a/src/test/scala/chiselTests/AsTypeOfTester.scala b/src/test/scala/chiselTests/AsTypeOfTester.scala new file mode 100644 index 00000000..75a2dc8a --- /dev/null +++ b/src/test/scala/chiselTests/AsTypeOfTester.scala @@ -0,0 +1,76 @@ +// See LICENSE for license details. + +package chiselTests + +import org.scalatest._ + +import chisel3._ +import chisel3.experimental.{DataMirror, FixedPoint} +import chisel3.testers.BasicTester +import chisel3.util._ + +class AsTypeOfBundleTester extends BasicTester { + class MultiTypeBundle extends Bundle { + val u = UInt(4.W) + val s = SInt(4.W) + val fp = FixedPoint(4.W, 3.BP) + } + + val bun = new MultiTypeBundle + + val bunAsTypeOf = ((4 << 8) + (15 << 4) + (12 << 0)).U.asTypeOf(bun) + + assert(bunAsTypeOf.u === 4.U) + assert(bunAsTypeOf.s === -1.S) + assert(bunAsTypeOf.fp === FixedPoint.fromDouble(-0.5, 4.W, 3.BP)) + + stop() +} + +class AsTypeOfVecTester extends BasicTester { + val vec = ((15 << 12) + (0 << 8) + (1 << 4) + (2 << 0)).U.asTypeOf(Vec(4, SInt(4.W))) + + assert(vec(0) === 2.S) + assert(vec(1) === 1.S) + assert(vec(2) === 0.S) + assert(vec(3) === -1.S) + + stop() +} + +class AsTypeOfTruncationTester extends BasicTester { + val truncate = (64 + 3).U.asTypeOf(UInt(3.W)) + val expand = 1.U.asTypeOf(UInt(3.W)) + + assert( DataMirror.widthOf(truncate).get == 3 ) + assert( truncate === 3.U ) + assert( DataMirror.widthOf(expand).get == 3 ) + assert( expand === 1.U ) + + stop() +} + +class ResetAsTypeOfBoolTester extends BasicTester { + assert(reset.asTypeOf(Bool()) === reset.toBool) + stop() +} + +class AsTypeOfSpec extends ChiselFlatSpec { + behavior of "asTypeOf" + + it should "work with Bundles containing Bits Types" in { + assertTesterPasses{ new AsTypeOfBundleTester } + } + + it should "work with Vecs containing Bits Types" in { + assertTesterPasses{ new AsTypeOfVecTester } + } + + it should "expand and truncate UInts of different width" in { + assertTesterPasses{ new AsTypeOfTruncationTester } + } + + it should "work for casting implicit Reset to Bool" in { + assertTesterPasses{ new ResetAsTypeOfBoolTester } + } +} diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index 92559123..994a16fd 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -10,7 +10,7 @@ import chisel3.util._ class FailingAssertTester() extends BasicTester { assert(false.B) // Wait to come out of reset - val (_, done) = Counter(!reset, 4) + val (_, done) = Counter(!reset.toBool, 4) when (done) { stop() } @@ -19,7 +19,7 @@ class FailingAssertTester() extends BasicTester { class SucceedingAssertTester() extends BasicTester { assert(true.B) // Wait to come out of reset - val (_, done) = Counter(!reset, 4) + val (_, done) = Counter(!reset.toBool, 4) when (done) { stop() } @@ -38,7 +38,7 @@ class PipelinedResetTester extends BasicTester { module.reset := RegNext(RegNext(RegNext(reset))) - val (_, done) = Counter(!reset, 4) + val (_, done) = Counter(!reset.toBool, 4) when (done) { stop() } diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index 52a93aed..7feee96f 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -270,6 +270,17 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks }) } + "Reset" should "still walk, talk, and quack like a Bool" in { + import Chisel._ + elaborate(new Module { + val io = new Bundle { + val in = Bool(INPUT) + val out = Bool(OUTPUT) + } + io.out := io.in && reset + }) + } + "Data.dir" should "give the correct direction for io" in { import Chisel._ elaborate(new Module { @@ -292,4 +303,5 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks }) } } + } diff --git a/src/test/scala/chiselTests/FromBitsTester.scala b/src/test/scala/chiselTests/FromBitsTester.scala deleted file mode 100644 index e916272f..00000000 --- a/src/test/scala/chiselTests/FromBitsTester.scala +++ /dev/null @@ -1,67 +0,0 @@ -// See LICENSE for license details. - -package chiselTests - -import org.scalatest._ - -import chisel3._ -import chisel3.experimental.{DataMirror, FixedPoint} -import chisel3.testers.BasicTester -import chisel3.util._ - -class FromBitsBundleTester extends BasicTester { - class MultiTypeBundle extends Bundle { - val u = UInt(4.W) - val s = SInt(4.W) - val fp = FixedPoint(4.W, 3.BP) - } - - val bun = new MultiTypeBundle - - val bunFromBits = ((4 << 8) + (15 << 4) + (12 << 0)).U.asTypeOf(bun) - - assert(bunFromBits.u === 4.U) - assert(bunFromBits.s === -1.S) - assert(bunFromBits.fp === FixedPoint.fromDouble(-0.5, 4.W, 3.BP)) - - stop() -} - -class FromBitsVecTester extends BasicTester { - val vec = ((15 << 12) + (0 << 8) + (1 << 4) + (2 << 0)).U.asTypeOf(Vec(4, SInt(4.W))) - - assert(vec(0) === 2.S) - assert(vec(1) === 1.S) - assert(vec(2) === 0.S) - assert(vec(3) === -1.S) - - stop() -} - -class FromBitsTruncationTester extends BasicTester { - val truncate = (64 + 3).U.asTypeOf(UInt(3.W)) - val expand = 1.U.asTypeOf(UInt(3.W)) - - assert( DataMirror.widthOf(truncate).get == 3 ) - assert( truncate === 3.U ) - assert( DataMirror.widthOf(expand).get == 3 ) - assert( expand === 1.U ) - - stop() -} - -class FromBitsSpec extends ChiselFlatSpec { - behavior of "fromBits" - - it should "work with Bundles containing Bits Types" in { - assertTesterPasses{ new FromBitsBundleTester } - } - - it should "work with Vecs containing Bits Types" in { - assertTesterPasses{ new FromBitsVecTester } - } - - it should "expand and truncate UInts of different width" in { - assertTesterPasses{ new FromBitsTruncationTester } - } -} diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index ada0b9b0..3f9ad895 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -55,7 +55,7 @@ class MultiClockSubModuleTest extends BasicTester { /** Test withReset changing the reset of a Reg */ class WithResetTest extends BasicTester { val reset2 = Wire(init = false.B) - val reg = withReset(reset2 || reset) { RegInit(0.U(8.W)) } + val reg = withReset(reset2 || reset.toBool) { RegInit(0.U(8.W)) } reg := reg + 1.U val (cycle, done) = Counter(true.B, 10) -- cgit v1.2.3