From 7e9f424fb7dcd11c894ceb9f6f049fd9eda80632 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Mon, 20 Jul 2020 12:11:44 -0700
Subject: Delete outdated scalastyle configuration comments from source

---
 src/main/scala/chisel3/Driver.scala                |  2 +-
 src/main/scala/chisel3/compatibility.scala         | 24 ++++++++++------------
 .../scala/chisel3/internal/firrtl/Emitter.scala    |  9 ++++----
 src/main/scala/chisel3/stage/ChiselStage.scala     |  2 +-
 src/main/scala/chisel3/testers/TesterDriver.scala  |  2 --
 src/main/scala/chisel3/util/BitPat.scala           | 12 +++++------
 src/main/scala/chisel3/util/Bitwise.scala          |  2 +-
 src/main/scala/chisel3/util/Conditional.scala      |  6 +++---
 src/main/scala/chisel3/util/Decoupled.scala        |  4 ++--
 .../util/experimental/LoadMemoryTransform.scala    |  1 -
 src/main/scala/chisel3/util/random/LFSR.scala      |  4 ++--
 .../scala/chiselTests/AnnotatingDiamondSpec.scala  |  2 +-
 src/test/scala/chiselTests/AnnotationNoDedup.scala |  2 --
 src/test/scala/chiselTests/BlackBoxImpl.scala      |  2 --
 src/test/scala/chiselTests/CompatibilitySpec.scala |  4 +---
 .../scala/chiselTests/CompileOptionsTest.scala     |  2 --
 .../scala/chiselTests/EnableShiftRegister.scala    |  4 +---
 src/test/scala/chiselTests/FixedPointSpec.scala    |  1 -
 src/test/scala/chiselTests/IntegerMathSpec.scala   |  1 -
 src/test/scala/chiselTests/IntervalRangeSpec.scala |  1 -
 src/test/scala/chiselTests/IntervalSpec.scala      |  2 --
 src/test/scala/chiselTests/InvalidateAPISpec.scala |  2 --
 .../scala/chiselTests/LiteralExtractorSpec.scala   |  2 +-
 src/test/scala/chiselTests/Module.scala            |  2 +-
 .../scala/chiselTests/NamingAnnotationTest.scala   | 16 +++++++--------
 src/test/scala/chiselTests/OneHotMuxSpec.scala     |  1 -
 src/test/scala/chiselTests/PrintableSpec.scala     |  2 +-
 src/test/scala/chiselTests/Risc.scala              |  6 ++----
 src/test/scala/chiselTests/StrongEnum.scala        |  4 +---
 .../scala/chiselTests/util/random/LFSRSpec.scala   |  1 -
 src/test/scala/cookbook/FSM.scala                  |  2 +-
 31 files changed, 49 insertions(+), 78 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 6ac0a5c1..7393fd22 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -211,7 +211,7 @@ object Driver extends BackendCompilationUtilities {
     * @return                       An execution result with useful stuff, or failure with message
     */
   @deprecated("Use chisel3.stage.ChiselStage.execute. This will be removed in 3.4.", "3.2.2")
-  def execute( // scalastyle:ignore method.length
+  def execute(
       optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions,
       dut: () => RawModule): ChiselExecutionResult = {
 
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 89aefef2..d63a8343 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -8,7 +8,7 @@ import chisel3.experimental.chiselName
 import chisel3.util.random.FibonacciLFSR
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage, phases}
 
-package object Chisel {     // scalastyle:ignore package.object.name number.of.types number.of.methods
+package object Chisel {
   import chisel3.internal.firrtl.Width
 
   import scala.language.experimental.macros
@@ -207,8 +207,8 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     /** Create an SInt literal with specified width. */
     def apply(value: BigInt, width: Width): SInt = value.asSInt(width)
 
-    def Lit(value: BigInt): SInt = value.asSInt // scalastyle:ignore method.name
-    def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W) // scalastyle:ignore method.name
+    def Lit(value: BigInt): SInt = value.asSInt
+    def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W)
 
     /** Create a SInt with a specified width - compatibility with Chisel2. */
     def apply(dir: Option[Direction] = None, width: Int): SInt = apply(width.W)
@@ -263,7 +263,7 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
   abstract class BlackBox(params: Map[String, Param] = Map.empty[String, Param]) extends chisel3.BlackBox(params) {
     // This class auto-wraps the BlackBox with IO(...), allowing legacy code (where IO(...) wasn't
     // required) to build.
-    override def _compatAutoWrapPorts(): Unit = { // scalastyle:ignore method.name
+    override def _compatAutoWrapPorts(): Unit = {
       if (!_compatIoPortBound()) {
         _bindIoInPlace(io)
       }
@@ -322,7 +322,7 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) =
       this(Option(_clock), Option(_reset))(moduleCompileOptions)
 
-    override def _compatAutoWrapPorts(): Unit = { // scalastyle:ignore method.name
+    override def _compatAutoWrapPorts(): Unit = {
       if (!_compatIoPortBound() && io != null) {
         _bindIoInPlace(io)
       }
@@ -426,7 +426,7 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
   }
 
   @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
-  object debug {  // scalastyle:ignore object.name
+  object debug {
     def apply (arg: Data): Data = arg
   }
 
@@ -439,7 +439,7 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     }
   }
 
-  object testers {    // scalastyle:ignore object.name
+  object testers {
     type BasicTester = chisel3.testers.BasicTester
     val TesterDriver = chisel3.testers.TesterDriver
   }
@@ -593,7 +593,6 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     *
     * }}}
     */
-  // scalastyle:off magic.number
   object LFSR16 {
     /** Generates a 16-bit linear feedback shift register, returning the register contents.
       * @param increment optional control to gate when the LFSR updates.
@@ -607,7 +606,6 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
         .asUInt
 
   }
-  // scalastyle:on magic.number
 
   val ListLookup = chisel3.util.ListLookup
   val Lookup = chisel3.util.Lookup
@@ -636,12 +634,12 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
     * Because its contents won't necessarily have the same level of stability and support as
     * non-experimental, you must explicitly import this package to use its contents.
     */
-  object experimental {  // scalastyle:ignore object.name
+  object experimental {
     import scala.annotation.compileTimeOnly
 
-    class dump extends chisel3.internal.naming.dump  // scalastyle:ignore class.name
-    class treedump extends chisel3.internal.naming.treedump  // scalastyle:ignore class.name
-    class chiselName extends chisel3.internal.naming.chiselName  // scalastyle:ignore class.name
+    class dump extends chisel3.internal.naming.dump
+    class treedump extends chisel3.internal.naming.treedump
+    class chiselName extends chisel3.internal.naming.chiselName
   }
 
   implicit class DataCompatibility(a: Data) {
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 2124fa25..be8d8f2f 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -25,7 +25,7 @@ private class Emitter(circuit: Circuit) {
     s"$dirString ${e.id.getRef.name} : ${emitType(e.id, clearDir)}"
   }
 
-  private def emitType(d: Data, clearDir: Boolean = false): String = d match { // scalastyle:ignore cyclomatic.complexity line.size.limit
+  private def emitType(d: Data, clearDir: Boolean = false): String = d match {
     case d: Clock => "Clock"
     case _: AsyncReset => "AsyncReset"
     case _: ResetType => "Reset"
@@ -62,15 +62,15 @@ private class Emitter(circuit: Circuit) {
     case d => d.specifiedDirection
   }
 
-  private def emit(e: Command, ctx: Component): String = { // scalastyle:ignore cyclomatic.complexity
+  private def emit(e: Command, ctx: Component): String = {
     val firrtlLine = e match {
       case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})"
       case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}"
       case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}"
-      case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" // scalastyle:ignore line.size.limit
+      case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))"
       case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]"
       case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}], ${e.readUnderWrite}"
-      case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" // scalastyle:ignore line.size.limit
+      case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
       case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
       case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
       case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")")
@@ -101,7 +101,6 @@ private class Emitter(circuit: Circuit) {
         s"skip"
     }
     firrtlLine + e.sourceInfo.makeMessage(" " + _)
-    // scalastyle:on line.size.limit
   }
 
   private def emitParam(name: String, p: Param): String = {
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala
index 2dbb5b9d..938f0250 100644
--- a/src/main/scala/chisel3/stage/ChiselStage.scala
+++ b/src/main/scala/chisel3/stage/ChiselStage.scala
@@ -45,7 +45,7 @@ class ChiselStage extends Stage with PreservesAll[Phase] {
       Predef
         .augmentString(stackTrace)
         .lines
-        .foreach(line => println(s"${ErrorLog.errTag} $line")) // scalastyle:ignore regex
+        .foreach(line => println(s"${ErrorLog.errTag} $line"))
       throw new StageError(cause=ce)
   }
 
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index 6231f81a..6e414ff4 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -16,7 +16,6 @@ import treadle.executable.StopException
 import treadle.stage.TreadleTesterPhase
 import treadle.{CallResetAtStartupAnnotation, TreadleTesterAnnotation, WriteVcdAnnotation}
 
-//scalastyle:off magic.number method.length
 object TesterDriver extends BackendCompilationUtilities {
   var MaxTreadleCycles = 10000L
 
@@ -125,7 +124,6 @@ object TesterDriver extends BackendCompilationUtilities {
     }
   }
 
-  //scalastyle:off cyclomatic.complexity method.length
   def executeTreadle(t:                    () => BasicTester,
                      additionalVResources: Seq[String] = Seq(),
                      annotations:          AnnotationSeq = Seq(),
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 7c0abdb2..27de9982 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -86,16 +86,16 @@ object BitPat {
     final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
 
     /** @group SourceInfoTransformMacro */
-    def do_=== (that: BitPat)  // scalastyle:ignore method.name
+    def do_=== (that: BitPat)
                (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that === x
     /** @group SourceInfoTransformMacro */
-    def do_=/= (that: BitPat)  // scalastyle:ignore method.name
+    def do_=/= (that: BitPat)
                (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that =/= x
 
     final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     @chiselRuntimeDeprecated
     @deprecated("Use '=/=', which avoids potential precedence problems", "3.0")
-    def do_!= (that: BitPat)  // scalastyle:ignore method.name
+    def do_!= (that: BitPat)
               (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that != x
   }
 }
@@ -115,12 +115,12 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) extends Sou
   def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg
 
   /** @group SourceInfoTransformMacro */
-  def do_=== (that: UInt)  // scalastyle:ignore method.name
+  def do_=== (that: UInt)
       (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
     value.asUInt === (that & mask.asUInt)
   }
   /** @group SourceInfoTransformMacro */
-  def do_=/= (that: UInt)  // scalastyle:ignore method.name
+  def do_=/= (that: UInt)
       (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
     !(this === that)
   }
@@ -128,7 +128,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) extends Sou
   def != (that: UInt): Bool = macro SourceInfoTransform.thatArg
   @chiselRuntimeDeprecated
   @deprecated("Use '=/=', which avoids potential precedence problems", "3.0")
-  def do_!= (that: UInt)  // scalastyle:ignore method.name
+  def do_!= (that: UInt)
       (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = {
     this =/= that
   }
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 4681b34a..3583b7d1 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -90,7 +90,7 @@ object Fill {
   * }}}
   */
 object Reverse {
-  private def doit(in: UInt, length: Int): UInt = length match { // scalastyle:ignore cyclomatic.complexity
+  private def doit(in: UInt, length: Int): UInt = length match {
     case _ if length < 0 => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.")
     case _ if length <= 1 => in
     case _ if isPow2(length) && length >= 8 && length <= 64 =>
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 7aebc815..4938d075 100644
--- a/src/main/scala/chisel3/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -12,7 +12,7 @@ import scala.reflect.macros.blackbox._
 import chisel3._
 
 @deprecated("The unless conditional is deprecated, use when(!condition){...} instead", "3.2")
-object unless {  // scalastyle:ignore object.name
+object unless {
   /** Does the same thing as [[when$ when]], but with the condition inverted.
     */
   def apply(c: Bool)(block: => Any) {
@@ -56,7 +56,7 @@ class SwitchContext[T <: Element](cond: T, whenContext: Option[WhenContext], lit
   * @note dummy implementation, a macro inside [[switch]] transforms this into the actual
   * implementation
   */
-object is {   // scalastyle:ignore object.name
+object is {
   // TODO: Begin deprecation of non-type-parameterized is statements.
   /** Executes `block` if the switch condition is equal to any of the values in `v`.
     */
@@ -90,7 +90,7 @@ object is {   // scalastyle:ignore object.name
   * }
   * }}}
   */
-object switch {  // scalastyle:ignore object.name
+object switch {
   def apply[T <: Element](cond: T)(x: => Any): Unit = macro impl
   def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
     val q"..$body" = x
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 82511ee5..884235bf 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -107,7 +107,7 @@ object Decoupled
     */
   @chiselName
   def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = {
-    require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") // scalastyle:ignore line.size.limit
+    require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.")
     val d = Wire(new DecoupledIO(irr.bits))
     d.bits := irr.bits
     d.valid := irr.valid
@@ -138,7 +138,7 @@ object Irrevocable
     * @note unsafe (and will error) on the consumer (output) side of an DecoupledIO
     */
   def apply[T <: Data](dec: DecoupledIO[T]): IrrevocableIO[T] = {
-    require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.") // scalastyle:ignore line.size.limit
+    require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.")
     val i = Wire(new IrrevocableIO(dec.bits))
     dec.bits := i.bits
     dec.valid := i.valid
diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index 3d14b5c2..92bfcde7 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -123,7 +123,6 @@ object loadMemoryFromFile {
   * Currently the only non-Verilog based simulation that can support loading memory from a file is treadle but it does
   * not need this transform to do that.
   */
-//scalastyle:off method.length
 class LoadMemoryTransform extends Transform {
   def inputForm: CircuitForm  = LowForm
   def outputForm: CircuitForm = LowForm
diff --git a/src/main/scala/chisel3/util/random/LFSR.scala b/src/main/scala/chisel3/util/random/LFSR.scala
index 5b67c509..17e10311 100644
--- a/src/main/scala/chisel3/util/random/LFSR.scala
+++ b/src/main/scala/chisel3/util/random/LFSR.scala
@@ -103,7 +103,7 @@ object LFSR {
   lazy val tapsMaxPeriod: Map[Int, Seq[Set[Int]]] = tapsFirst ++ tapsSecond
 
   /** First portion of known taps (a combined map hits the 64KB JVM method limit) */
-  private def tapsFirst = Map( // scalastyle:off magic.number
+  private def tapsFirst = Map(
     2    -> Seq(Set(2, 1)),
     3    -> Seq(Set(3, 2)),
     4    -> Seq(Set(4, 3)),
@@ -894,6 +894,6 @@ object LFSR {
     786  -> Seq(Set(786, 782, 780, 771)),
     1024 -> Seq(Set(1024, 1015, 1002, 1001)),
     2048 -> Seq(Set(2048, 2035, 2034, 2029)),
-    4096 -> Seq(Set(4096, 4095, 4081, 4069)) ) // scalastyle:on magic.number
+    4096 -> Seq(Set(4096, 4095, 4081, 4069)) )
 
 }
diff --git a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
index 70a62555..aa1ca7f5 100644
--- a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
+++ b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
@@ -31,7 +31,7 @@ case class IdentityChiselAnnotation(target: InstanceId, value: String)
   def toFirrtl: IdentityAnnotation = IdentityAnnotation(target.toNamed, value)
   def transformClass: Class[IdentityTransform] = classOf[IdentityTransform]
 }
-object identify { // scalastyle:ignore object.name
+object identify {
   def apply(component: InstanceId, value: String): Unit = {
     val anno = IdentityChiselAnnotation(component, value)
     annotate(anno)
diff --git a/src/test/scala/chiselTests/AnnotationNoDedup.scala b/src/test/scala/chiselTests/AnnotationNoDedup.scala
index ff0005b4..5515f740 100644
--- a/src/test/scala/chiselTests/AnnotationNoDedup.scala
+++ b/src/test/scala/chiselTests/AnnotationNoDedup.scala
@@ -43,7 +43,6 @@ class UsesMuchUsedModule(addAnnos: Boolean) extends Module {
 
 class AnnotationNoDedup extends AnyFreeSpec with Matchers {
   val stage = new ChiselStage
-  // scalastyle:off line.size.limit
   "Firrtl provides transform that reduces identical modules to a single instance" - {
     "Annotations can be added which will prevent this deduplication for specific modules instances" in {
       val lowFirrtl = stage
@@ -72,5 +71,4 @@ class AnnotationNoDedup extends AnyFreeSpec with Matchers {
       lowFirrtl should not include "module MuchUsedModule_4 :"
     }
   }
-  // scalastyle:on line.size.limit
 }
diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala
index da89a326..b88db8f4 100644
--- a/src/test/scala/chiselTests/BlackBoxImpl.scala
+++ b/src/test/scala/chiselTests/BlackBoxImpl.scala
@@ -13,7 +13,6 @@ import org.scalatest.Succeeded
 import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 
-//scalastyle:off magic.number
 
 class BlackBoxAdd(n : Int) extends HasBlackBoxInline {
   val io = IO(new Bundle {
@@ -21,7 +20,6 @@ class BlackBoxAdd(n : Int) extends HasBlackBoxInline {
     val out = Output(UInt(16.W))
   })
 
-  //scalastyle:off regex
   setInline("BlackBoxAdd.v",
     s"""
       |module BlackBoxAdd(
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 09ec40ee..183540af 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -60,7 +60,7 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     val value: Int = Gen.choose(2, 2048).sample.get
     log2Up(value) shouldBe (1 max BigInt(value - 1).bitLength)
     log2Ceil(value) shouldBe (BigInt(value - 1).bitLength)
-    log2Down(value) shouldBe ((1 max BigInt(value - 1).bitLength) - (if (value > 0 && ((value & (value - 1)) == 0)) 0 else 1)) // scalastyle:ignore line.size.limit
+    log2Down(value) shouldBe ((1 max BigInt(value - 1).bitLength) - (if (value > 0 && ((value & (value - 1)) == 0)) 0 else 1))
     log2Floor(value) shouldBe (BigInt(value - 1).bitLength - (if (value > 0 && ((value & (value - 1)) == 0)) 0 else 1))
     isPow2(BigInt(1) << value) shouldBe true
     isPow2((BigInt(1) << value) - 1) shouldBe false
@@ -201,7 +201,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type]
   }
 
-  // scalastyle:off line.size.limit
   "A Module with missing bundle fields when compiled with the Chisel compatibility package" should "not throw an exception" in {
 
     class ConnectFieldMismatchModule extends Module {
@@ -348,7 +347,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       Chisel.assert(io.bar.dir == INPUT)
     })
   }
-  // scalastyle:on line.size.limit
 
   behavior of "BitPat"
 
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 1bd0327a..092e6f11 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -21,7 +21,6 @@ class CompileOptionsSpec extends ChiselFlatSpec with Utils {
     override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type]
   }
 
-  // scalastyle:off line.size.limit
   "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy extractCause[ChiselException] {
       import chisel3.ExplicitCompileOptions.Strict
@@ -185,5 +184,4 @@ class CompileOptionsSpec extends ChiselFlatSpec with Utils {
     }
     ChiselStage.elaborate { new DirectionLessConnectionModule() }
   }
-  // scalastyle:on line.size.limit
 }
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 5f023df8..fd3249fd 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -23,14 +23,13 @@ class EnableShiftRegister extends Module {
   io.out := r3
 }
 
-// scalastyle:off regex
 /*
 class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
   val reg = Array.fill(4){ 0 }
   for (t <- 0 until 16) {
     val in    = rnd.nextInt(16)
     val shift = rnd.nextInt(2)
-    println("SHIFT " + shift + " IN " + in)   // scalastyle:ignore regex
+    println("SHIFT " + shift + " IN " + in)
     poke(c.io.in,    in)
     poke(c.io.shift, shift)
     step(1)
@@ -43,7 +42,6 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
   }
 }
 */
-// scalastyle:on regex
 
 class EnableShiftRegisterSpec extends ChiselPropSpec {
 
diff --git a/src/test/scala/chiselTests/FixedPointSpec.scala b/src/test/scala/chiselTests/FixedPointSpec.scala
index c5aab7e4..35d7f786 100644
--- a/src/test/scala/chiselTests/FixedPointSpec.scala
+++ b/src/test/scala/chiselTests/FixedPointSpec.scala
@@ -11,7 +11,6 @@ import org.scalatest._
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
-//scalastyle:off magic.number
 class FixedPointLiteralSpec extends AnyFlatSpec with Matchers {
   behavior of "fixed point utilities"
 
diff --git a/src/test/scala/chiselTests/IntegerMathSpec.scala b/src/test/scala/chiselTests/IntegerMathSpec.scala
index e78a780c..945ea8c5 100644
--- a/src/test/scala/chiselTests/IntegerMathSpec.scala
+++ b/src/test/scala/chiselTests/IntegerMathSpec.scala
@@ -5,7 +5,6 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 
-//scalastyle:off magic.number
 class IntegerMathTester extends BasicTester {
 
   //TODO: Add more operators
diff --git a/src/test/scala/chiselTests/IntervalRangeSpec.scala b/src/test/scala/chiselTests/IntervalRangeSpec.scala
index 3aaedb1d..a1f4ed02 100644
--- a/src/test/scala/chiselTests/IntervalRangeSpec.scala
+++ b/src/test/scala/chiselTests/IntervalRangeSpec.scala
@@ -9,7 +9,6 @@ import chisel3.internal.firrtl.{BinaryPoint, IntervalRange, KnownBinaryPoint, Un
 import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 
-//scalastyle:off method.name magic.number
 class IntervalRangeSpec extends AnyFreeSpec with Matchers {
 
   "IntervalRanges" - {
diff --git a/src/test/scala/chiselTests/IntervalSpec.scala b/src/test/scala/chiselTests/IntervalSpec.scala
index 1f813442..0babed41 100644
--- a/src/test/scala/chiselTests/IntervalSpec.scala
+++ b/src/test/scala/chiselTests/IntervalSpec.scala
@@ -19,7 +19,6 @@ import firrtl.{FIRRTLException, HighFirrtlCompiler, LowFirrtlCompiler, MiddleFir
 import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 
-//scalastyle:off magic.number
 //noinspection TypeAnnotation
 
 object IntervalTestHelper {
@@ -30,7 +29,6 @@ object IntervalTestHelper {
     * @param gen the generator for the module
     * @return the Verilog code as a string.
     */
-  //scalastyle:off cyclomatic.complexity
   def makeFirrtl[T <: RawModule](compilerName: String)(gen: () => T): String = {
     (new ChiselStage)
       .execute(Array("--compiler", compilerName,
diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala
index f0841ef0..5890310e 100644
--- a/src/test/scala/chiselTests/InvalidateAPISpec.scala
+++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala
@@ -24,7 +24,6 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila
     val out = Output(Bool())
   }
 
-  // scalastyle:off line.size.limit
   property("an output connected to DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") {
     import chisel3.ExplicitCompileOptions.Strict
     class ModuleWithDontCare extends Module {
@@ -215,5 +214,4 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila
     val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare)
     firrtlOutput should include("is invalid")
   }
-  // scalastyle:on line.size.limit
 }
diff --git a/src/test/scala/chiselTests/LiteralExtractorSpec.scala b/src/test/scala/chiselTests/LiteralExtractorSpec.scala
index 0c485368..864f2d9f 100644
--- a/src/test/scala/chiselTests/LiteralExtractorSpec.scala
+++ b/src/test/scala/chiselTests/LiteralExtractorSpec.scala
@@ -110,7 +110,7 @@ class LiteralExtractorSpec extends ChiselFlatSpec {
 
       // the following errors with "assertion failed"
 
-      println(outsideLiteral === insideLiteral) // scalastyle:ignore regex
+      println(outsideLiteral === insideLiteral)
       // chisel3.assert(outsideLiteral === insideLiteral)
 
       // the following lines of code error
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index f4b51927..f91b6293 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -72,7 +72,7 @@ class ModuleWrapper(gen: => Module) extends Module {
 class NullModuleWrapper extends Module {
   val io = IO(new Bundle{})
   override lazy val desiredName = s"${child.desiredName}Wrapper"
-  println(s"My name is ${name}") // scalastyle:ignore regex
+  println(s"My name is ${name}")
   val child = Module(new ModuleWire)
 }
 
diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala
index 41cba1de..e77d3d70 100644
--- a/src/test/scala/chiselTests/NamingAnnotationTest.scala
+++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala
@@ -67,7 +67,7 @@ class NonModule {
 @chiselName
 class NamedModule extends NamedModuleTester {
   @chiselName
-  def FunctionMockupInner(): UInt = { // scalastyle:ignore method.name
+  def FunctionMockupInner(): UInt = {
     val my2A = 1.U
     val my2B = expectName(my2A +& 2.U, "test_myNested_my2B")
     val my2C = my2B +& 3.U  // should get named at enclosing scope
@@ -75,7 +75,7 @@ class NamedModule extends NamedModuleTester {
   }
 
   @chiselName
-  def FunctionMockup(): UInt = { // scalastyle:ignore method.name
+  def FunctionMockup(): UInt = {
     val myNested = expectName(FunctionMockupInner(), "test_myNested")
     val myA = expectName(1.U + myNested, "test_myA")
     val myB = expectName(myA +& 2.U, "test_myB")
@@ -89,14 +89,14 @@ class NamedModule extends NamedModuleTester {
   }
 
   // chiselName "implicitly" applied
-  def ImplicitlyNamed(): UInt = { // scalastyle:ignore method.name
+  def ImplicitlyNamed(): UInt = {
     val implicitA = expectName(1.U + 2.U, "test3_implicitA")
     val implicitB = expectName(implicitA + 3.U, "test3_implicitB")
     implicitB + 2.U  // named at enclosing scope
   }
 
   // Ensure this applies a partial name if there is no return value
-  def NoReturnFunction() { // scalastyle:ignore method.name
+  def NoReturnFunction() {
     val noreturn = expectName(1.U + 2.U, "noreturn")
   }
 
@@ -149,7 +149,7 @@ class NameCollisionModule extends NamedModuleTester {
   */
 class NonNamedModule extends NamedModuleTester {
   @chiselName
-  def NamedFunction(): UInt = { // scalastyle:ignore method.name
+  def NamedFunction(): UInt = {
     val myVal = 1.U + 2.U
     myVal
   }
@@ -162,18 +162,18 @@ class NonNamedModule extends NamedModuleTester {
   */
 object NonNamedHelper {
   @chiselName
-  def NamedFunction(): UInt = { // scalastyle:ignore method.name
+  def NamedFunction(): UInt = {
     val myVal = 1.U + 2.U
     myVal
   }
 
-  def NonNamedFunction() : UInt = { // scalastyle:ignore method.name
+  def NonNamedFunction() : UInt = {
     val myVal = NamedFunction()
     myVal
   }
 
   @chiselName
-  def NonBuilderFunction(): Int = { // scalastyle:ignore method.name
+  def NonBuilderFunction(): Int = {
     1 + 1
   }
 }
diff --git a/src/test/scala/chiselTests/OneHotMuxSpec.scala b/src/test/scala/chiselTests/OneHotMuxSpec.scala
index 78ae5a66..cc359e8e 100644
--- a/src/test/scala/chiselTests/OneHotMuxSpec.scala
+++ b/src/test/scala/chiselTests/OneHotMuxSpec.scala
@@ -11,7 +11,6 @@ import org.scalatest._
 import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 
-//scalastyle:off magic.number
 
 class OneHotMuxSpec extends AnyFreeSpec with Matchers with ChiselRunners {
   "simple one hot mux with uint should work" in {
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index 8e39d405..2ac2ad5d 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -128,7 +128,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers {
       printf(p"${FullName(myInst.io.fizz)}")
     }
     val firrtl = (new ChiselStage).emitChirrtl(new MyModule)
-    println(firrtl) // scalastyle:ignore regex
+    println(firrtl)
     getPrintfs(firrtl) match {
       case Seq(Printf("foo", Seq()),
                Printf("myWire.foo", Seq()),
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index de39e723..765e1e56 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -55,7 +55,6 @@ class Risc extends Module {
   }
 }
 
-// scalastyle:off regex
 /*
 class RiscTester(c: Risc) extends Tester(c) {
   def wr(addr: BigInt, data: BigInt)  = {
@@ -77,7 +76,7 @@ class RiscTester(c: Risc) extends Tester(c) {
   def I (op: UInt, rc: Int, ra: Int, rb: Int) = {
     // val cr = Cat(op, rc.asUInt(8.W), ra.asUInt(8.W), rb.asUInt(8.W)).litValue()
     val cr = op.litValue() << 24 | rc << 16 | ra << 8 | rb
-    println("I = " + cr)    // scalastyle:ignore regex
+    println("I = " + cr)
     cr
   }
 
@@ -89,7 +88,7 @@ class RiscTester(c: Risc) extends Tester(c) {
   for (addr <- 0 until app.length)
     wr(addr, app(addr))
   def dump(k: Int) {
-    println("K = " + k)  // scalastyle:ignore regex
+    println("K = " + k)
     peek(c.ra)
     peek(c.rb)
     peek(c.rc)
@@ -113,7 +112,6 @@ class RiscTester(c: Risc) extends Tester(c) {
   expect(c.io.out, 4)
 }
 */
-// scalastyle:on regex
 
 class RiscSpec extends ChiselPropSpec {
 
diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala
index f052e783..e71a0461 100644
--- a/src/test/scala/chiselTests/StrongEnum.scala
+++ b/src/test/scala/chiselTests/StrongEnum.scala
@@ -255,7 +255,7 @@ class StrongEnumFSMTester extends BasicTester {
 
   // Inputs and expected results
   val inputs: Vec[Bool] = VecInit(false.B, true.B, false.B, true.B, true.B, true.B, false.B, true.B, true.B, false.B)
-  val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) // scalastyle:ignore line.size.limit
+  val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B)
   val expected_state = VecInit(sNone, sNone, sOne1, sNone, sOne1, sTwo1s, sTwo1s, sNone, sOne1, sTwo1s)
 
   val cntr = Counter(inputs.length)
@@ -538,7 +538,6 @@ class StrongEnumAnnotationSpec extends AnyFreeSpec with Matchers {
     CorrectVecAnno("bund.inner_bundle1.v", enumExampleName, Set())
   )
 
-  // scalastyle:off regex
   def printAnnos(annos: Seq[Annotation]) {
     println("Enum definitions:")
     annos.foreach {
@@ -556,7 +555,6 @@ class StrongEnumAnnotationSpec extends AnyFreeSpec with Matchers {
       case _ =>
     }
   }
-  // scalastyle:on regex
 
   def isCorrect(anno: EnumDefAnnotation, correct: CorrectDefAnno): Boolean = {
     (anno.typeName == correct.typeName ||
diff --git a/src/test/scala/chiselTests/util/random/LFSRSpec.scala b/src/test/scala/chiselTests/util/random/LFSRSpec.scala
index 90986637..4bd5b2ed 100644
--- a/src/test/scala/chiselTests/util/random/LFSRSpec.scala
+++ b/src/test/scala/chiselTests/util/random/LFSRSpec.scala
@@ -38,7 +38,6 @@ class LFSRMaxPeriod(gen: => UInt) extends BasicTester {
   * Each cycle it adds them together and adds a count to the bin corresponding to that value
   * The asserts check that the bins show the correct distribution.
   */
-//scalastyle:off magic.number
 class LFSRDistribution(gen: => UInt, cycles: Int = 10000) extends BasicTester {
 
   val rv = gen
diff --git a/src/test/scala/cookbook/FSM.scala b/src/test/scala/cookbook/FSM.scala
index f33bfee4..170d110f 100644
--- a/src/test/scala/cookbook/FSM.scala
+++ b/src/test/scala/cookbook/FSM.scala
@@ -53,7 +53,7 @@ class DetectTwoOnesTester extends CookbookTester(10) {
 
   // Inputs and expected results
   val inputs: Vec[Bool] = VecInit(false.B, true.B, false.B, true.B, true.B, true.B, false.B, true.B, true.B, false.B)
-  val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) // scalastyle:ignore line.size.limit
+  val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B)
 
   dut.io.in := inputs(cycle)
   assert(dut.io.out === expected(cycle))
-- 
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