From 78dd6b801f0988c381f47c76ca23b58f17eee942 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 30 Oct 2015 14:53:17 -0700
Subject: Move Cat into utils

---
 src/main/scala/Chisel/Bits.scala     |  5 ++++-
 src/main/scala/Chisel/Cat.scala      | 31 -------------------------------
 src/main/scala/Chisel/util/Cat.scala | 26 ++++++++++++++++++++++++++
 3 files changed, 30 insertions(+), 32 deletions(-)
 delete mode 100644 src/main/scala/Chisel/Cat.scala
 create mode 100644 src/main/scala/Chisel/util/Cat.scala

(limited to 'src')

diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 209dbd1f..021532a1 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -175,7 +175,10 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     *
     * The width of the output is sum of the inputs. Generates no logic.
     */
-  def ## (other: Bits): UInt = Cat(this, other)
+  def ## (other: Bits): UInt = {
+    val w = this.width + other.width
+    pushOp(DefPrim(UInt(w), ConcatOp, this.ref, other.ref))
+  }
 
   @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3")
   override def toBits: UInt = asUInt
diff --git a/src/main/scala/Chisel/Cat.scala b/src/main/scala/Chisel/Cat.scala
deleted file mode 100644
index 8075c11d..00000000
--- a/src/main/scala/Chisel/Cat.scala
+++ /dev/null
@@ -1,31 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-import Builder.pushOp
-import PrimOp._
-
-// REVIEW TODO: Should the FIRRTL emission be part of Bits, with a separate
-// Cat in stdlib that can do a reduction among multiple elements?
-object Cat {
-  /** Combine data elements together
-    * @param a Data to combine with
-    * @param r any number of other Data elements to be combined in order
-    * @return A UInt which is all of the bits combined together
-    */
-  def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList)
-
-  /** Combine data elements together
-    * @param r any number of other Data elements to be combined in order
-    * @return A UInt which is all of the bits combined together
-    */
-  def apply[T <: Bits](r: Seq[T]): UInt = {
-    if (r.tail.isEmpty) {
-      r.head.asUInt
-    } else {
-      val left = apply(r.slice(0, r.length/2))
-      val right = apply(r.slice(r.length/2, r.length))
-      val w = left.width + right.width
-      pushOp(DefPrim(UInt(w), ConcatOp, left.ref, right.ref))
-    }
-  }
-}
diff --git a/src/main/scala/Chisel/util/Cat.scala b/src/main/scala/Chisel/util/Cat.scala
new file mode 100644
index 00000000..088a208e
--- /dev/null
+++ b/src/main/scala/Chisel/util/Cat.scala
@@ -0,0 +1,26 @@
+// See LICENSE for license details.
+
+package Chisel
+
+object Cat {
+  /** Combine data elements together
+    * @param a Data to combine with
+    * @param r any number of other Data elements to be combined in order
+    * @return A UInt which is all of the bits combined together
+    */
+  def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList)
+
+  /** Combine data elements together
+    * @param r any number of other Data elements to be combined in order
+    * @return A UInt which is all of the bits combined together
+    */
+  def apply[T <: Bits](r: Seq[T]): UInt = {
+    if (r.tail.isEmpty) {
+      r.head.asUInt
+    } else {
+      val left = apply(r.slice(0, r.length/2))
+      val right = apply(r.slice(r.length/2, r.length))
+      left ## right
+    }
+  }
+}
-- 
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