From 783bcb8b3436e342a04169eaf967db2dbc58abc7 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Fri, 15 Dec 2023 09:22:44 -0800
Subject: Add abstract module

---
 src/test/scala/chiselTests/AbstractModule.scala | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/AbstractModule.scala b/src/test/scala/chiselTests/AbstractModule.scala
index dc381120..9942f290 100644
--- a/src/test/scala/chiselTests/AbstractModule.scala
+++ b/src/test/scala/chiselTests/AbstractModule.scala
@@ -13,8 +13,9 @@ class AbstractModuleContainer extends Module {
   mod2.node := mod1.node
 }
 
-class AbstractModuleSpec extends ChiselPropSpec with Utils {
-  property("Abstract module should elaborate") {
-    ChiselStage.elaborate { new AbstractModuleContainer }
+object AbstractModuleSpec {
+  def main(args: Array[String]): Unit = {
+    // println(getVerilogString(new Example))
+    println(chisel3.stage.ChiselStage.emitVerilog(new AbstractModuleContainer))
   }
 }
-- 
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