From 6d37cc8b9d731fa4c844f097b11057c46771961b Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jan 2016 08:25:41 -0800
Subject: Don't silence legitimate warnings - these println()s should be
 controlled by a diagnostic/debugging infrastructure.

---
 src/main/scala/Chisel/Driver.scala       | 2 +-
 src/test/scala/chiselTests/UIntOps.scala | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index 900d53ce..cd88c302 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -84,7 +84,7 @@ trait BackendCompilationUtilities {
     val e = Process(s"./V${prefix}", dir) !
       ProcessLogger(line => {
         triggered = triggered || line.contains(assertionMsg)
-        System.out.println(line)  // scalastyle:ignore regex
+        System.out.println(line)
       })
     triggered
   }
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 24cb8fc9..bb0b0f06 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -48,13 +48,13 @@ class UIntOps extends Module {
 class UIntOpsTester(c: UIntOps) extends Tester(c) {
   def uintExpect(d: Bits, x: BigInt) {
     val mask = (1 << 16) - 1
-    println(" E = " + x + " X&M = " + (x & mask))  // scalastyle:ignore regex
+    println(" E = " + x + " X&M = " + (x & mask))
     expect(d, x & mask)
   }
   for (t <- 0 until 16) {
     val test_a = rnd.nextInt(1 << 16)
     val test_b = rnd.nextInt(1 << 16)
-    println("A = " + test_a + " B = " + test_b)  // scalastyle:ignore regex
+    println("A = " + test_a + " B = " + test_b)
     poke(c.io.a, test_a)
     poke(c.io.b, test_b)
     step(1)
-- 
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