From 614551236186d35ff42ea9c90130a3b80646ba69 Mon Sep 17 00:00:00 2001 From: Abongwa Bonalais Date: Wed, 3 Nov 2021 06:46:49 +0100 Subject: Add field grouping ScalaDoc for ArbiterIO (#2208) * Update Arbiter.scala * Update src/main/scala/chisel3/util/Arbiter.scala changed group name Co-authored-by: Megan Wachs * minor changes on grouping ArbiterIO * removed unmatched closing brace * Remove groupdesc from Arbiter.scala * Added groupdesc to Aggregate.scala * Update Arbiter.scala * Update core/src/main/scala/chisel3/Aggregate.scala Co-authored-by: Megan Wachs * Update Arbiter.scala * Update src/main/scala/chisel3/util/Arbiter.scala Added suugestions. Co-authored-by: Megan Wachs * added suggestions from review * added suggestions from review * Resolved conflicts * update Arbiter.scala * Update core/src/main/scala/chisel3/Aggregate.scala deleted groudesc for ArbiterIO Co-authored-by: Megan Wachs * Update Scaladoc syntax * removed some lines * Better documentation * Removed @param and @gen * Update core/src/main/scala/chisel3/Aggregate.scala Co-authored-by: Megan Wachs * Update src/main/scala/chisel3/util/Arbiter.scala Co-authored-by: Megan Wachs * Added groupdesc to ArbiterIO * Update src/main/scala/chisel3/util/Arbiter.scala Co-authored-by: Megan Wachs * Update core/src/main/scala/chisel3/Aggregate.scala Co-authored-by: Megan Wachs * Update Arbiter.scala * Update src/main/scala/chisel3/util/Arbiter.scala Co-authored-by: Megan Wachs * Update Arbiter.scala Co-authored-by: Megan Wachs --- src/main/scala/chisel3/util/Arbiter.scala | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src') diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 135700fa..b68acae1 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -10,6 +10,7 @@ import chisel3.internal.naming.chiselName // can't use chisel3_ version because /** IO bundle definition for an Arbiter, which takes some number of ready-valid inputs and outputs * (selects) at most one. + * @groupdesc Signals The actual hardware fields of the Bundle * * @param gen data type * @param n number of inputs @@ -17,8 +18,20 @@ import chisel3.internal.naming.chiselName // can't use chisel3_ version because class ArbiterIO[T <: Data](private val gen: T, val n: Int) extends Bundle { // See github.com/freechipsproject/chisel3/issues/765 for why gen is a private val and proposed replacement APIs. +/** Input data, one per potential sender + * + * @group Signals + */ val in = Flipped(Vec(n, Decoupled(gen))) +/** Output data after arbitration + * + * @group Signals + */ val out = Decoupled(gen) +/** One-Hot vector indicating which output was chosen + * + * @group Signals + */ val chosen = Output(UInt(log2Ceil(n).W)) } -- cgit v1.2.3