From 5ca2820216a4c4b8c28438967d6e4680412f6580 Mon Sep 17 00:00:00 2001
From: Donggyu Kim
Date: Thu, 25 Aug 2016 14:05:31 -0700
Subject: fix a bug in setModName

---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 79f86ae9..8b94c68f 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -87,7 +87,7 @@ private class Emitter(circuit: Circuit) {
         ""
       case None =>
         defnMap((m.id.desiredName, defn)) = m
-        m.id setModName m.id.name
+        m.id setModName m.name
         moduleDecl(m) + defn
     }
   }
-- 
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