From 581e551526f91cf0b6311637709d8fb99bb24c74 Mon Sep 17 00:00:00 2001 From: ducky Date: Tue, 20 Oct 2015 16:35:43 -0700 Subject: Make if / else braces style conformant to Scalastyle checker --- src/main/scala/Chisel/Core.scala | 73 ++++++++++++++++++++++++++------------- src/main/scala/Chisel/IR.scala | 6 ++-- src/main/scala/Chisel/Utils.scala | 39 ++++++++++++++------- 3 files changed, 78 insertions(+), 40 deletions(-) (limited to 'src') diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index b5787c40..872f4a2a 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -111,23 +111,30 @@ object Wire { def apply[T <: Data](t: T = null, init: T = null): T = { val x = Reg.makeType(t, null.asInstanceOf[T], init) pushCommand(DefWire(x)) - if (init != null) + if (init != null) { x := init - else + } else { x.flatten.foreach(e => e := e.fromInt(0)) + } x } } object Reg { private[Chisel] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = { - if (t ne null) t.cloneType - else if (next ne null) next.cloneTypeWidth(Width()) - else if (init ne null) init.litArg match { - // For e.g. Reg(init=UInt(0, k)), fix the Reg's width to k - case Some(lit) if lit.forcedWidth => init.cloneType - case _ => init.cloneTypeWidth(Width()) - } else throwException("cannot infer type") + if (t ne null) { + t.cloneType + } else if (next ne null) { + next.cloneTypeWidth(Width()) + } else if (init ne null) { + init.litArg match { + // For e.g. Reg(init=UInt(0, k)), fix the Reg's width to k + case Some(lit) if lit.forcedWidth => init.cloneType + case _ => init.cloneTypeWidth(Width()) + } + } else { + throwException("cannot infer type") + } } /** Creates a register with optional next and initialization values. @@ -143,10 +150,12 @@ object Reg { // that doesn't need two implementations of apply() val x = makeType(t, next, init) pushCommand(DefRegister(x, Node(x._parent.get.clock), Node(x._parent.get.reset))) // TODO multi-clock - if (init != null) + if (init != null) { pushCommand(ConnectInit(x.lref, init.ref)) - if (next != null) + } + if (next != null) { x := next + } x } @@ -580,10 +589,14 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: */ // REVIEW TODO: Ddeduplicate constructor with apply(Int) final def apply(x: BigInt): Bool = { - if (x < 0) + if (x < 0) { Builder.error(s"Negative bit indices are illegal (got $x)") - if (isLit()) Bool(((litValue() >> x.toInt) & 1) == 1) - else pushOp(DefPrim(Bool(), BitSelectOp, this.ref, ILit(x))) + } + if (isLit()) { + Bool(((litValue() >> x.toInt) & 1) == 1) + } else { + pushOp(DefPrim(Bool(), BitSelectOp, this.ref, ILit(x))) + } } final def apply(x: Int): Bool = @@ -605,13 +618,17 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: * }}} */ final def apply(x: Int, y: Int): UInt = { - if (x < y || y < 0) + if (x < y || y < 0) { Builder.error(s"Invalid bit range ($x,$y)") + } // REVIEW TODO: should we support negative indexing Python style, at least // where widths are known? val w = x - y + 1 - if (isLit()) UInt((litValue >> y) & ((BigInt(1) << w) - 1), w) - else pushOp(DefPrim(UInt(width = w), BitsExtractOp, this.ref, ILit(x), ILit(y))) + if (isLit()) { + UInt((litValue >> y) & ((BigInt(1) << w) - 1), w) + } else { + pushOp(DefPrim(UInt(width = w), BitsExtractOp, this.ref, ILit(x), ILit(y))) + } } // REVIEW TODO: again, is this necessary? Or just have this and use implicits? @@ -900,9 +917,13 @@ sealed trait UIntFactory { } private def parsedWidth(n: String) = - if (n(0) == 'b') Width(n.length-1) - else if (n(0) == 'h') Width((n.length-1) * 4) - else Width() + if (n(0) == 'b') { + Width(n.length-1) + } else if (n(0) == 'h') { + Width((n.length-1) * 4) + } else { + Width() + } } object UInt extends UIntFactory @@ -1084,8 +1105,9 @@ object Cat { * @return A UInt which is all of the bits combined together */ def apply[T <: Bits](r: Seq[T]): UInt = { - if (r.tail.isEmpty) r.head.asUInt - else { + if (r.tail.isEmpty) { + r.head.asUInt + } else { val left = apply(r.slice(0, r.length/2)) val right = apply(r.slice(r.length/2, r.length)) val w = left.width + right.width @@ -1158,8 +1180,11 @@ class Bundle extends Aggregate(NO_DIR) { for (m <- getClass.getMethods.sortWith(_.getName < _.getName); if isBundleField(m)) { m.invoke(this) match { case d: Data => - if (nameMap contains m.getName) require(nameMap(m.getName) eq d) - else if (!seen(d)) { nameMap(m.getName) = d; seen += d } + if (nameMap contains m.getName) { + require(nameMap(m.getName) eq d) + } else if (!seen(d)) { + nameMap(m.getName) = d; seen += d + } case _ => } } diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala index 2c6b0a4c..78c08c7e 100644 --- a/src/main/scala/Chisel/IR.scala +++ b/src/main/scala/Chisel/IR.scala @@ -55,8 +55,9 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { private[Chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth) protected def minWidth: Int - if (forcedWidth) + if (forcedWidth) { require(widthArg.get >= minWidth) + } } case class ILit(n: BigInt) extends Arg { @@ -85,8 +86,7 @@ case class ModuleIO(mod: Module, name: String) extends Arg { } case class Slot(imm: Node, name: String) extends Arg { override def fullName(ctx: Component) = - if (imm.fullName(ctx).isEmpty) name - else s"${imm.fullName(ctx)}.${name}" + if (imm.fullName(ctx).isEmpty) name else s"${imm.fullName(ctx)}.${name}" } case class Index(imm: Arg, value: Int) extends Arg { def name = s"[$value]" diff --git a/src/main/scala/Chisel/Utils.scala b/src/main/scala/Chisel/Utils.scala index 617ebb3d..61bf28a8 100644 --- a/src/main/scala/Chisel/Utils.scala +++ b/src/main/scala/Chisel/Utils.scala @@ -106,8 +106,9 @@ object Mux1H def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in) def apply[T <: Data](in: Iterable[(Bool, T)]): T = { - if (in.tail.isEmpty) in.head._2 - else { + if (in.tail.isEmpty) { + in.head._2 + } else { val masked = in map {case (s, i) => Mux(s, i.toBits, Bits(0))} val width = in.map(_._2.width).reduce(_ max _) in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_)) @@ -219,8 +220,11 @@ object Fill { } /** Fan out x n times */ def apply(n: Int, x: Bool): UInt = - if (n > 1) UInt(0,n) - x - else apply(n, x: UInt) + if (n > 1) { + UInt(0,n) - x + } else { + apply(n, x: UInt) + } } /** MuxCase returns the first value that is enabled in a map of values */ @@ -305,9 +309,13 @@ object ShiftRegister object Log2 { /** Compute the Log2 on the least significant n bits of x */ def apply(x: Bits, width: Int): UInt = { - if (width < 2) UInt(0) - else if (width == 2) x(1) - else Mux(x(width-1), UInt(width-1), apply(x, width-1)) + if (width < 2) { + UInt(0) + } else if (width == 2) { + x(1) + } else { + Mux(x(width-1), UInt(width-1), apply(x, width-1)) + } } def apply(x: Bits): UInt = apply(x, x.getWidth) @@ -321,8 +329,9 @@ object OHToUInt { def apply(in: Bits): UInt = apply(in, in.getWidth) def apply(in: Bits, width: Int): UInt = { - if (width <= 2) Log2(in, width) - else { + if (width <= 2) { + Log2(in, width) + } else { val mid = 1 << (log2Up(width)-1) val hi = in(width-1, mid) val lo = in(mid-1, 0) @@ -345,8 +354,11 @@ object PriorityEncoder { object UIntToOH { def apply(in: UInt, width: Int = -1): UInt = - if (width == -1) UInt(1) << in - else (UInt(1) << in(log2Up(width)-1,0))(width-1,0) + if (width == -1) { + UInt(1) << in + } else { + (UInt(1) << in(log2Up(width)-1,0))(width-1,0) + } } /** A counter module @@ -355,8 +367,9 @@ object UIntToOH class Counter(val n: Int) { val value = if (n == 1) UInt(0) else Reg(init=UInt(0, log2Up(n))) def inc(): Bool = { - if (n == 1) Bool(true) - else { + if (n == 1) { + Bool(true) + } else { val wrap = value === UInt(n-1) value := Mux(Bool(!isPow2(n)) && wrap, UInt(0), value + UInt(1)) wrap -- cgit v1.2.3