From 4c512593fb5688f3de502ba1ed70681a0802b6c9 Mon Sep 17 00:00:00 2001
From: edwardcwang
Date: Tue, 19 Feb 2019 16:14:39 -0800
Subject: Mainline Chisel multi-clock functionality (#1013)

Close #1009---
 src/main/scala/chisel3/package.scala             | 8 ++++++++
 src/test/scala/chiselTests/CloneModuleSpec.scala | 2 +-
 src/test/scala/chiselTests/Module.scala          | 1 -
 src/test/scala/chiselTests/MultiClockSpec.scala  | 1 -
 src/test/scala/chiselTests/RawModuleSpec.scala   | 2 +-
 5 files changed, 10 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 3fa461ad..6c1ab588 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -47,6 +47,11 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   val Clock = chisel3.core.Clock
   type Clock = chisel3.core.Clock
 
+  // Clock and reset scoping functions
+  val withClockAndReset = chisel3.core.withClockAndReset
+  val withClock = chisel3.core.withClock
+  val withReset = chisel3.core.withReset
+
   implicit class AddDirectionToData[T<:Data](target: T) {
     @chiselRuntimeDeprecated
     @deprecated("Input(Data) should be used over Data.asInput", "chisel3")
@@ -424,8 +429,11 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     type ChiselEnum = chisel3.core.EnumFactory
     val EnumAnnotations = chisel3.core.EnumAnnotations
 
+    @deprecated("Use the version in chisel3._", "chisel3.2")
     val withClockAndReset = chisel3.core.withClockAndReset
+    @deprecated("Use the version in chisel3._", "chisel3.2")
     val withClock = chisel3.core.withClock
+    @deprecated("Use the version in chisel3._", "chisel3.2")
     val withReset = chisel3.core.withReset
 
     val dontTouch = chisel3.core.dontTouch
diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala
index 9a637df9..bef29fce 100644
--- a/src/test/scala/chiselTests/CloneModuleSpec.scala
+++ b/src/test/scala/chiselTests/CloneModuleSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util.{Queue, EnqIO, DeqIO, QueueIO, log2Ceil}
-import chisel3.experimental.{CloneModuleAsRecord, MultiIOModule, withClockAndReset}
+import chisel3.experimental.{CloneModuleAsRecord, MultiIOModule}
 import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index b3d1899c..a973412e 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{withClock, withReset}
 
 class SimpleIO extends Bundle {
   val in  = Input(UInt(32.W))
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 6e84c9b2..770a9e9a 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{withClockAndReset, withClock, withReset}
 import chisel3.util.Counter
 import chisel3.testers.BasicTester
 
diff --git a/src/test/scala/chiselTests/RawModuleSpec.scala b/src/test/scala/chiselTests/RawModuleSpec.scala
index b864a669..88b53457 100644
--- a/src/test/scala/chiselTests/RawModuleSpec.scala
+++ b/src/test/scala/chiselTests/RawModuleSpec.scala
@@ -3,7 +3,7 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{RawModule, withClockAndReset}
+import chisel3.experimental.RawModule
 import chisel3.testers.BasicTester
 
 class UnclockedPlusOne extends RawModule {
-- 
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