From 4b8584b1d2c46c76b1540e265a84eeb247d684e4 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 15 Feb 2022 22:35:23 +0000 Subject: Make TruthTable accept unknown input width (#2387) (#2417) Widths are now padded to the maximum width of the inputs. Co-authored-by: Jack Koenig (cherry picked from commit 546b4e13fe90ff09d24b63664c072d46c13c0c38) Co-authored-by: Jiuyang Liu --- .../util/experimental/decode/TruthTable.scala | 9 ++++++-- .../util/experimental/TruthTableSpec.scala | 24 ++++++++++++++++++++++ 2 files changed, 31 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala b/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala index e742fd66..00fa0f9c 100644 --- a/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala +++ b/src/main/scala/chisel3/util/experimental/decode/TruthTable.scala @@ -31,10 +31,15 @@ object TruthTable { /** Convert a table and default output into a [[TruthTable]]. */ def apply(table: Iterable[(BitPat, BitPat)], default: BitPat, sort: Boolean = true): TruthTable = { - require(table.map(_._1.getWidth).toSet.size == 1, "input width not equal.") + val inputWidth = table.map(_._1.getWidth).max require(table.map(_._2.getWidth).toSet.size == 1, "output width not equal.") val outputWidth = table.map(_._2.getWidth).head - val mergedTable = table + val mergedTable = table.map { + // pad input signals if necessary + case (in, out) if inputWidth > in.width => + (BitPat.N(inputWidth - in.width) ## in, out) + case (in, out) => (in, out) + } .groupBy(_._1.toString) .map { case (key, values) => diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala index 2ef316bb..fa2c6f08 100644 --- a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala +++ b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala @@ -80,4 +80,28 @@ class TruthTableSpec extends AnyFlatSpec { } assert(chisel3.stage.ChiselStage.emitChirrtl(new Foo) == chisel3.stage.ChiselStage.emitChirrtl(new Foo)) } + "TruthTable" should "accept unknown input width" in { + val t = TruthTable( + Seq( + BitPat(0.U) -> BitPat.dontCare(1), + BitPat(1.U) -> BitPat.dontCare(1), + BitPat(2.U) -> BitPat.dontCare(1), + BitPat(3.U) -> BitPat.dontCare(1), + BitPat(4.U) -> BitPat.dontCare(1), + BitPat(5.U) -> BitPat.dontCare(1), + BitPat(6.U) -> BitPat.dontCare(1), + BitPat(7.U) -> BitPat.dontCare(1) + ), + BitPat.N(1) + ) + assert(t.toString contains "000->?") + assert(t.toString contains "001->?") + assert(t.toString contains "010->?") + assert(t.toString contains "011->?") + assert(t.toString contains "100->?") + assert(t.toString contains "101->?") + assert(t.toString contains "110->?") + assert(t.toString contains "111->?") + assert(t.toString contains " 0") + } } -- cgit v1.2.3