From 492a71d6d4d3acef39f29345835637bca028a089 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 17 Mar 2021 14:00:27 -0400 Subject: Fix incorrect usage of emitFirrtl in test (#1817) Change a test to use emitChirrtl instead of emitFirrtl. This test isn't supposed to be running the Scala FIRRTL Compiler, but the latter method causes this to happen. Signed-off-by: Schuyler Eldridge --- .../scala/chiselTests/experimental/verification/VerificationSpec.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala b/src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala index 52293abb..fe642156 100644 --- a/src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala +++ b/src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala @@ -28,7 +28,7 @@ class VerificationSpec extends ChiselPropSpec { } property("basic equality check should work") { - val fir = ChiselStage.emitFirrtl(new VerificationModule) + val fir = ChiselStage.emitChirrtl(new VerificationModule) val lines = fir.split("\n").map(_.trim) assertContains(lines, "cover(clock, _T, UInt<1>(\"h1\"), \"\") @[VerificationSpec.scala 16:15]") assertContains(lines, "assume(clock, _T_2, UInt<1>(\"h1\"), \"\") @[VerificationSpec.scala 18:18]") -- cgit v1.2.3