From 3f21bbb52363c3105f6a0ff961fa7a411dd0c7ab Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Thu, 9 Dec 2021 11:19:27 -0800
Subject: Better MonoConnect error messages (#2248)

Co-authored-by: Megan Wachs <megan@sifive.com>---
 src/test/scala/chiselTests/ConnectSpec.scala       | 35 ++++++++++++++++++++++
 src/test/scala/chiselTests/InvalidateAPISpec.scala |  2 +-
 2 files changed, 36 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/ConnectSpec.scala b/src/test/scala/chiselTests/ConnectSpec.scala
index 367864e6..f9ef5946 100644
--- a/src/test/scala/chiselTests/ConnectSpec.scala
+++ b/src/test/scala/chiselTests/ConnectSpec.scala
@@ -2,6 +2,8 @@
 
 package chiselTests
 
+import org.scalatest._
+
 import chisel3._
 import chisel3.experimental.{Analog, FixedPoint}
 import chisel3.stage.ChiselStage
@@ -126,4 +128,37 @@ class ConnectSpec extends ChiselPropSpec with Utils {
   property("Pipe internal connections should succeed") {
     ChiselStage.elaborate( new PipeInternalWires)
   }
+
+  property("Connect error messages should have meaningful information") {
+    class InnerExample extends Module {
+      val myReg = RegInit(0.U(8.W))
+    }
+
+    class OuterAssignExample extends Module {
+      val inner = Module(new InnerExample())
+      inner.myReg := false.B // ERROR
+    }
+
+    val assignError = the [ChiselException] thrownBy {ChiselStage.elaborate { new OuterAssignExample}}
+    val expectedAssignError = """.*@: myReg in InnerExample cannot be written from module OuterAssignExample."""
+    assignError.getMessage should fullyMatch regex expectedAssignError
+
+    class OuterReadExample extends Module {
+      val myReg = RegInit(0.U(8.W))
+      val inner = Module(new InnerExample())
+      myReg := inner.myReg // ERROR
+    }
+
+    val readError = the [ChiselException] thrownBy {ChiselStage.elaborate { new OuterReadExample }}
+    val expectedReadError = """.*@: myReg in InnerExample cannot be read from module OuterReadExample."""
+    readError.getMessage should fullyMatch regex expectedReadError
+
+    val typeMismatchError = the [ChiselException] thrownBy {ChiselStage.elaborate { new RawModule {
+      val myUInt = Wire(UInt(4.W))
+      val mySInt = Wire(SInt(4.W))
+      myUInt := mySInt
+    }}}
+    val expectedTypeMismatchError = """.*@: Sink \(UInt<4>\) and Source \(SInt<4>\) have different types."""
+    typeMismatchError.getMessage should fullyMatch regex expectedTypeMismatchError
+  }
 }
diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala
index b7db33cc..52ad02b4 100644
--- a/src/test/scala/chiselTests/InvalidateAPISpec.scala
+++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala
@@ -105,7 +105,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila
         ChiselStage.elaborate(new ModuleWithDontCareSink)
       }
     }
-    exception.getMessage should include("DontCare cannot be a connection sink (LHS)")
+    exception.getMessage should include("DontCare cannot be a connection sink")
   }
 
   property("a DontCare cannot be a connection sink (LHS) for <>") {
-- 
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