From f36524e388b060b1bb535ae21cb1bcbbea220be9 Mon Sep 17 00:00:00 2001 From: ducky Date: Fri, 20 May 2016 18:09:57 -0700 Subject: Rename packages to lowercase chisel, add compatibility layer --- src/main/scala/Chisel/BitPat.scala | 4 +- src/main/scala/Chisel/Driver.scala | 132 --------------- src/main/scala/Chisel/FileSystemUtilities.scala | 10 -- src/main/scala/Chisel/ImplicitConversions.scala | 8 - src/main/scala/Chisel/Main.scala | 17 -- .../scala/Chisel/internal/firrtl/Emitter.scala | 112 ------------- src/main/scala/Chisel/package.scala | 31 ---- src/main/scala/Chisel/testers/BasicTester.scala | 38 ----- src/main/scala/Chisel/testers/TesterDriver.scala | 68 -------- src/main/scala/Chisel/throwException.scala | 12 -- src/main/scala/Chisel/util/Arbiter.scala | 117 ------------- src/main/scala/Chisel/util/Bitwise.scala | 71 -------- src/main/scala/Chisel/util/Cat.scala | 18 -- src/main/scala/Chisel/util/CircuitMath.scala | 26 --- src/main/scala/Chisel/util/Conditional.scala | 69 -------- src/main/scala/Chisel/util/Counter.scala | 44 ----- src/main/scala/Chisel/util/Decoupled.scala | 183 --------------------- src/main/scala/Chisel/util/Enum.scala | 21 --- src/main/scala/Chisel/util/LFSR.scala | 22 --- src/main/scala/Chisel/util/Lookup.scala | 17 -- src/main/scala/Chisel/util/Math.scala | 42 ----- src/main/scala/Chisel/util/Mux.scala | 61 ------- src/main/scala/Chisel/util/OneHot.scala | 62 ------- src/main/scala/Chisel/util/Reg.scala | 55 ------- src/main/scala/Chisel/util/TransitName.scala | 21 --- src/main/scala/Chisel/util/Valid.scala | 59 ------- src/main/scala/chisel/Driver.scala | 132 +++++++++++++++ src/main/scala/chisel/FileSystemUtilities.scala | 10 ++ src/main/scala/chisel/ImplicitConversions.scala | 8 + src/main/scala/chisel/Main.scala | 17 ++ src/main/scala/chisel/compatibility.scala | 139 ++++++++++++++++ .../scala/chisel/internal/firrtl/Emitter.scala | 112 +++++++++++++ src/main/scala/chisel/package.scala | 31 ++++ src/main/scala/chisel/testers/BasicTester.scala | 38 +++++ src/main/scala/chisel/testers/TesterDriver.scala | 69 ++++++++ src/main/scala/chisel/throwException.scala | 12 ++ src/main/scala/chisel/util/Arbiter.scala | 117 +++++++++++++ src/main/scala/chisel/util/Bitwise.scala | 71 ++++++++ src/main/scala/chisel/util/Cat.scala | 18 ++ src/main/scala/chisel/util/CircuitMath.scala | 26 +++ src/main/scala/chisel/util/Conditional.scala | 71 ++++++++ src/main/scala/chisel/util/Counter.scala | 44 +++++ src/main/scala/chisel/util/Decoupled.scala | 183 +++++++++++++++++++++ src/main/scala/chisel/util/Enum.scala | 21 +++ src/main/scala/chisel/util/LFSR.scala | 22 +++ src/main/scala/chisel/util/Lookup.scala | 17 ++ src/main/scala/chisel/util/Math.scala | 42 +++++ src/main/scala/chisel/util/Mux.scala | 61 +++++++ src/main/scala/chisel/util/OneHot.scala | 62 +++++++ src/main/scala/chisel/util/Reg.scala | 55 +++++++ src/main/scala/chisel/util/TransitName.scala | 21 +++ src/main/scala/chisel/util/Valid.scala | 59 +++++++ 52 files changed, 1460 insertions(+), 1318 deletions(-) delete mode 100644 src/main/scala/Chisel/Driver.scala delete mode 100644 src/main/scala/Chisel/FileSystemUtilities.scala delete mode 100644 src/main/scala/Chisel/ImplicitConversions.scala delete mode 100644 src/main/scala/Chisel/Main.scala delete mode 100644 src/main/scala/Chisel/internal/firrtl/Emitter.scala delete mode 100644 src/main/scala/Chisel/package.scala delete mode 100644 src/main/scala/Chisel/testers/BasicTester.scala delete mode 100644 src/main/scala/Chisel/testers/TesterDriver.scala delete mode 100644 src/main/scala/Chisel/throwException.scala delete mode 100644 src/main/scala/Chisel/util/Arbiter.scala delete mode 100644 src/main/scala/Chisel/util/Bitwise.scala delete mode 100644 src/main/scala/Chisel/util/Cat.scala delete mode 100644 src/main/scala/Chisel/util/CircuitMath.scala delete mode 100644 src/main/scala/Chisel/util/Conditional.scala delete mode 100644 src/main/scala/Chisel/util/Counter.scala delete mode 100644 src/main/scala/Chisel/util/Decoupled.scala delete mode 100644 src/main/scala/Chisel/util/Enum.scala delete mode 100644 src/main/scala/Chisel/util/LFSR.scala delete mode 100644 src/main/scala/Chisel/util/Lookup.scala delete mode 100644 src/main/scala/Chisel/util/Math.scala delete mode 100644 src/main/scala/Chisel/util/Mux.scala delete mode 100644 src/main/scala/Chisel/util/OneHot.scala delete mode 100644 src/main/scala/Chisel/util/Reg.scala delete mode 100644 src/main/scala/Chisel/util/TransitName.scala delete mode 100644 src/main/scala/Chisel/util/Valid.scala create mode 100644 src/main/scala/chisel/Driver.scala create mode 100644 src/main/scala/chisel/FileSystemUtilities.scala create mode 100644 src/main/scala/chisel/ImplicitConversions.scala create mode 100644 src/main/scala/chisel/Main.scala create mode 100644 src/main/scala/chisel/compatibility.scala create mode 100644 src/main/scala/chisel/internal/firrtl/Emitter.scala create mode 100644 src/main/scala/chisel/package.scala create mode 100644 src/main/scala/chisel/testers/BasicTester.scala create mode 100644 src/main/scala/chisel/testers/TesterDriver.scala create mode 100644 src/main/scala/chisel/throwException.scala create mode 100644 src/main/scala/chisel/util/Arbiter.scala create mode 100644 src/main/scala/chisel/util/Bitwise.scala create mode 100644 src/main/scala/chisel/util/Cat.scala create mode 100644 src/main/scala/chisel/util/CircuitMath.scala create mode 100644 src/main/scala/chisel/util/Conditional.scala create mode 100644 src/main/scala/chisel/util/Counter.scala create mode 100644 src/main/scala/chisel/util/Decoupled.scala create mode 100644 src/main/scala/chisel/util/Enum.scala create mode 100644 src/main/scala/chisel/util/LFSR.scala create mode 100644 src/main/scala/chisel/util/Lookup.scala create mode 100644 src/main/scala/chisel/util/Math.scala create mode 100644 src/main/scala/chisel/util/Mux.scala create mode 100644 src/main/scala/chisel/util/OneHot.scala create mode 100644 src/main/scala/chisel/util/Reg.scala create mode 100644 src/main/scala/chisel/util/TransitName.scala create mode 100644 src/main/scala/chisel/util/Valid.scala (limited to 'src') diff --git a/src/main/scala/Chisel/BitPat.scala b/src/main/scala/Chisel/BitPat.scala index 96206f63..a6833ed2 100644 --- a/src/main/scala/Chisel/BitPat.scala +++ b/src/main/scala/Chisel/BitPat.scala @@ -1,10 +1,10 @@ // See LICENSE for license details. -package Chisel +package chisel import scala.language.experimental.macros -import Chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform} +import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform} object BitPat { /** Parses a bit pattern string into (bits, mask, width). diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala deleted file mode 100644 index 02204684..00000000 --- a/src/main/scala/Chisel/Driver.scala +++ /dev/null @@ -1,132 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -import scala.sys.process._ -import java.io._ - -import internal._ -import internal.firrtl._ - -trait BackendCompilationUtilities { - /** Create a temporary directory with the prefix name. Exists here because it doesn't in Java 6. - */ - def createTempDirectory(prefix: String): File = { - val temp = File.createTempFile(prefix, "") - if (!temp.delete()) { - throw new IOException(s"Unable to delete temp file '$temp'") - } - if (!temp.mkdir()) { - throw new IOException(s"Unable to create temp directory '$temp'") - } - temp - } - - def makeHarness(template: String => String, post: String)(f: File): File = { - val prefix = f.toString.split("/").last - val vf = new File(f.toString + post) - val w = new FileWriter(vf) - w.write(template(prefix)) - w.close() - vf - } - - def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder = { - Process( - Seq("firrtl", - "-i", s"$prefix.fir", - "-o", s"$prefix.v", - "-X", "verilog"), - dir) - } - - /** Generates a Verilator invocation to convert Verilog sources to C++ - * simulation sources. - * - * The Verilator prefix will be V$dutFile, and running this will generate - * C++ sources and headers as well as a makefile to compile them. - * - * @param dutFile name of the DUT .v without the .v extension - * @param name of the top-level module in the design - * @param dir output directory - * @param vSources list of additional Verilog sources to compile - * @param cppHarness C++ testharness to compile/link against - */ - def verilogToCpp( - dutFile: String, - topModule: String, - dir: File, - vSources: Seq[File], - cppHarness: File - ): ProcessBuilder = { - val command = Seq("verilator", - "--cc", s"$dutFile.v") ++ - vSources.map(file => Seq("-v", file.toString)).flatten ++ - Seq("--assert", - "-Wno-fatal", - "-Wno-WIDTH", - "-Wno-STMTDLY", - "--trace", - "-O2", - "--top-module", topModule, - "+define+TOP_TYPE=V" + dutFile, - s"+define+PRINTF_COND=!$topModule.reset", - "-CFLAGS", - s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""", - "-Mdir", dir.toString, - "--exe", cppHarness.toString) - System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex - command - } - - def cppToExe(prefix: String, dir: File): ProcessBuilder = - Seq("make", "-C", dir.toString, "-j", "-f", s"V${prefix}.mk", s"V${prefix}") - - def executeExpectingFailure( - prefix: String, - dir: File, - assertionMsg: String = "Assertion failed"): Boolean = { - var triggered = false - val e = Process(s"./V${prefix}", dir) ! - ProcessLogger(line => { - triggered = triggered || line.contains(assertionMsg) - System.out.println(line) // scalastyle:ignore regex - }) - triggered - } - - def executeExpectingSuccess(prefix: String, dir: File): Boolean = { - !executeExpectingFailure(prefix, dir) - } -} - -object Driver extends BackendCompilationUtilities { - - /** Elaborates the Module specified in the gen function into a Circuit - * - * @param gen a function that creates a Module hierarchy - * @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR) - */ - def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen())) - - def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen)) - - def dumpFirrtl(ir: Circuit, optName: Option[File]): File = { - val f = optName.getOrElse(new File(ir.name + ".fir")) - val w = new FileWriter(f) - w.write(Emitter.emit(ir)) - w.close() - f - } - - private var target_dir: Option[String] = None - def parseArgs(args: Array[String]): Unit = { - for (i <- 0 until args.size) { - if (args(i) == "--targetDir") { - target_dir = Some(args(i + 1)) - } - } - } - - def targetDir(): String = { target_dir getOrElse new File(".").getCanonicalPath } -} diff --git a/src/main/scala/Chisel/FileSystemUtilities.scala b/src/main/scala/Chisel/FileSystemUtilities.scala deleted file mode 100644 index 575ae138..00000000 --- a/src/main/scala/Chisel/FileSystemUtilities.scala +++ /dev/null @@ -1,10 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -@deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0") -trait FileSystemUtilities { - def createOutputFile(name: String): java.io.FileWriter = { - new java.io.FileWriter(Driver.targetDir + "/" + name) - } -} diff --git a/src/main/scala/Chisel/ImplicitConversions.scala b/src/main/scala/Chisel/ImplicitConversions.scala deleted file mode 100644 index 6a230022..00000000 --- a/src/main/scala/Chisel/ImplicitConversions.scala +++ /dev/null @@ -1,8 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -object ImplicitConversions { - implicit def intToUInt(x: Int): UInt = UInt(x) - implicit def booleanToBool(x: Boolean): Bool = Bool(x) -} diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala deleted file mode 100644 index a72debc3..00000000 --- a/src/main/scala/Chisel/Main.scala +++ /dev/null @@ -1,17 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -import java.io.File - -@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain { - def apply[T <: Module](args: Array[String], gen: () => T): Unit = - Predef.assert(false, "No more chiselMain in Chisel3") - - def run[T <: Module] (args: Array[String], gen: () => T): Unit = { - val circuit = Driver.elaborate(gen) - Driver.parseArgs(args) - val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir") - Driver.dumpFirrtl(circuit, Option(output_file)) - } -} diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/Chisel/internal/firrtl/Emitter.scala deleted file mode 100644 index 7ca3268a..00000000 --- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala +++ /dev/null @@ -1,112 +0,0 @@ -// See LICENSE for license details. - -package Chisel.internal.firrtl -import Chisel._ -import Chisel.internal.sourceinfo.{NoSourceInfo, SourceLine} - -private[Chisel] object Emitter { - def emit(circuit: Circuit): String = new Emitter(circuit).toString -} - -private class Emitter(circuit: Circuit) { - override def toString: String = res.toString - - private def emitPort(e: Port): String = - s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}" - private def emit(e: Command, ctx: Component): String = { - val firrtlLine = e match { - case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})" - case e: DefWire => s"wire ${e.name} : ${e.id.toType}" - case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}" - case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" - case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]" - case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]" - case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" - case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" - case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" - case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})" - case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})""" - case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid" - case e: DefInstance => { - val modName = moduleMap.get(e.id.name).get - s"inst ${e.name} of $modName" - } - - case w: WhenBegin => - indent() - s"when ${w.pred.fullName(ctx)} :" - case _: WhenEnd => - unindent() - s"skip" - } - e.sourceInfo match { - case SourceLine(filename, line, col) => s"${firrtlLine} @[${filename} ${line}:${col}] " - case _: NoSourceInfo => firrtlLine - } - } - - // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already. - private val defnMap = collection.mutable.HashMap[String, String]() - // Map of Component name to FIRRTL id. - private val moduleMap = collection.mutable.HashMap[String, String]() - - /** Generates the FIRRTL module definition with a specified name. - */ - private def moduleDefn(m: Component, name: String): String = { - val body = new StringBuilder - m.id match { - case _: BlackBox => body ++= newline + s"extmodule $name : " - case _: Module => body ++= newline + s"module $name : " - } - withIndent { - for (p <- m.ports) - body ++= newline + emitPort(p) - body ++= newline - - m.id match { - case _: BlackBox => - // TODO: BlackBoxes should be empty, but funkiness in Module() means - // it's not for now. Eventually, this should assert out. - case _: Module => for (cmd <- m.commands) { - body ++= newline + emit(cmd, m) - } - } - body ++= newline - } - body.toString() - } - - /** Returns the FIRRTL declaration and body of a module, or nothing if it's a - * duplicate of something already emitted (on the basis of simple string - * matching). - */ - private def emit(m: Component): String = { - // Generate the body. - val moduleName = m.id.getClass.getName.split('.').last - val defn = moduleDefn(m, moduleName) - - defnMap get defn match { - case Some(deduplicatedName) => - moduleMap(m.name) = deduplicatedName - "" - case None => - require(!(moduleMap contains m.name), - "emitting module with same name but different contents") - - moduleMap(m.name) = m.name - defnMap(defn) = m.name - - moduleDefn(m, m.name) - } - } - - private var indentLevel = 0 - private def newline = "\n" + (" " * indentLevel) - private def indent(): Unit = indentLevel += 1 - private def unindent() { require(indentLevel > 0); indentLevel -= 1 } - private def withIndent(f: => Unit) { indent(); f; unindent() } - - private val res = new StringBuilder(s"circuit ${circuit.name} : ") - withIndent { circuit.components.foreach(c => res ++= emit(c)) } - res ++= newline -} diff --git a/src/main/scala/Chisel/package.scala b/src/main/scala/Chisel/package.scala deleted file mode 100644 index f05e8b5d..00000000 --- a/src/main/scala/Chisel/package.scala +++ /dev/null @@ -1,31 +0,0 @@ -package object Chisel { - import scala.language.experimental.macros - - import internal.firrtl.Width - import internal.sourceinfo.{SourceInfo, SourceInfoTransform} - - implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { - def U: UInt = UInt(x, Width()) - def S: SInt = SInt(x, Width()) - } - implicit class fromIntToLiteral(val x: Int) extends AnyVal { - def U: UInt = UInt(BigInt(x), Width()) - def S: SInt = SInt(BigInt(x), Width()) - } - implicit class fromStringToLiteral(val x: String) extends AnyVal { - def U: UInt = UInt(x) - } - implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { - def B: Bool = Bool(x) - } - - implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal { - final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg - final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg - final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg - - def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x - def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x - def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x - } -} diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/Chisel/testers/BasicTester.scala deleted file mode 100644 index b8c1494a..00000000 --- a/src/main/scala/Chisel/testers/BasicTester.scala +++ /dev/null @@ -1,38 +0,0 @@ -// See LICENSE for license details. - -package Chisel.testers -import Chisel._ - -import scala.language.experimental.macros - -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.SourceInfo - -class BasicTester extends Module { - // The testbench has no IOs, rather it should communicate using printf, assert, and stop. - val io = new Bundle() - - def popCount(n: Long): Int = n.toBinaryString.count(_=='1') - - /** Ends the test reporting success. - * - * Does not fire when in reset (defined as the encapsulating Module's - * reset). If your definition of reset is not the encapsulating Module's - * reset, you will need to gate this externally. - */ - def stop()(implicit sourceInfo: SourceInfo) { - // TODO: rewrite this using library-style SourceInfo passing. - when (!reset) { - pushCommand(Stop(sourceInfo, Node(clock), 0)) - } - } - - /** The finish method provides a hook that subclasses of BasicTester can use to - * alter a circuit after their constructor has been called. - * For example, a specialized tester subclassing BasicTester could override finish in order to - * add flow control logic for a decoupled io port of a device under test - */ - def finish(): Unit = {} -} diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala deleted file mode 100644 index a56bb8b7..00000000 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ /dev/null @@ -1,68 +0,0 @@ -// See LICENSE for license details. - -package Chisel.testers -import Chisel._ -import scala.io.Source -import scala.sys.process._ -import java.io._ - -object TesterDriver extends BackendCompilationUtilities { - /** Copy the contents of a resource to a destination file. - */ - def copyResourceToFile(name: String, file: File) { - val in = getClass().getResourceAsStream(name) - if (in == null) { - throw new FileNotFoundException(s"Resource '$name'") - } - val out = new FileOutputStream(file) - Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write) - out.close() - } - - /** For use with modules that should successfully be elaborated by the - * frontend, and which can be turned into executables with assertions. */ - def execute(t: () => BasicTester, additionalVResources: Seq[String] = Seq()): Boolean = { - // Invoke the chisel compiler to get the circuit's IR - val circuit = Driver.elaborate(finishWrapper(t)) - - // Set up a bunch of file handlers based on a random temp filename, - // plus the quirks of Verilator's naming conventions - val target = circuit.name - - val path = createTempDirectory(target) - val fname = new File(path, target) - - // For now, dump the IR out to a file - Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir"))) - - // Copy CPP harness and other Verilog sources from resources into files - val cppHarness = new File(path, "top.cpp") - copyResourceToFile("/top.cpp", cppHarness) - val additionalVFiles = additionalVResources.map((name: String) => { - val mangledResourceName = name.replace("/", "_") - val out = new File(path, mangledResourceName) - copyResourceToFile(name, out) - out - }) - - // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe - if ((firrtlToVerilog(target, path) #&& - verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& - cppToExe(target, path)).! == 0) { - executeExpectingSuccess(target, path) - } else { - false - } - } - /** - * Calls the finish method of an BasicTester or a class that extends it. - * The finish method is a hook for code that augments the circuit built in the constructor. - */ - def finishWrapper(test: () => BasicTester): () => BasicTester = { - () => { - val tester = test() - tester.finish() - tester - } - } -} diff --git a/src/main/scala/Chisel/throwException.scala b/src/main/scala/Chisel/throwException.scala deleted file mode 100644 index 702884aa..00000000 --- a/src/main/scala/Chisel/throwException.scala +++ /dev/null @@ -1,12 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -@deprecated("throwException doesn't exist in Chisel3", "3.0.0") -@throws(classOf[Exception]) -object throwException { - def apply(s: String, t: Throwable = null) = { - val xcpt = new Exception(s, t) - throw xcpt - } -} diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/Chisel/util/Arbiter.scala deleted file mode 100644 index 16ae9be5..00000000 --- a/src/main/scala/Chisel/util/Arbiter.scala +++ /dev/null @@ -1,117 +0,0 @@ -// See LICENSE for license details. - -/** Arbiters in all shapes and sizes. - */ - -package Chisel - -/** An I/O bundle for the Arbiter */ -class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { - val in = Vec(n, Decoupled(gen)).flip - val out = Decoupled(gen) - val chosen = UInt(OUTPUT, log2Up(n)) -} - -/** Arbiter Control determining which producer has access */ -private object ArbiterCtrl -{ - def apply(request: Seq[Bool]): Seq[Bool] = request.length match { - case 0 => Seq() - case 1 => Seq(Bool(true)) - case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_) - } -} - -abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module { - def grant: Seq[Bool] - def choice: UInt - val io = new ArbiterIO(gen, n) - - io.chosen := choice - io.out.valid := io.in(io.chosen).valid - io.out.bits := io.in(io.chosen).bits - - if (count > 1) { - val lockCount = Counter(count) - val lockIdx = Reg(UInt()) - val locked = lockCount.value =/= UInt(0) - val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true)) - - when (io.out.fire() && wantsLock) { - lockIdx := io.chosen - lockCount.inc() - } - - when (locked) { io.chosen := lockIdx } - for ((in, (g, i)) <- io.in zip grant.zipWithIndex) - in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready - } else { - for ((in, g) <- io.in zip grant) - in.ready := g && io.out.ready - } -} - -class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) - extends LockingArbiterLike[T](gen, n, count, needsLock) { - lazy val lastGrant = RegEnable(io.chosen, io.out.fire()) - lazy val grantMask = (0 until n).map(UInt(_) > lastGrant) - lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g } - - override def grant: Seq[Bool] = { - val ctrl = ArbiterCtrl((0 until n).map(i => validMask(i)) ++ io.in.map(_.valid)) - (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n)) - } - - override lazy val choice = Wire(init=UInt(n-1)) - for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } - for (i <- n-1 to 1 by -1) - when (validMask(i)) { choice := UInt(i) } -} - -class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) - extends LockingArbiterLike[T](gen, n, count, needsLock) { - def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid)) - - override lazy val choice = Wire(init=UInt(n-1)) - for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } -} - -/** Hardware module that is used to sequence n producers into 1 consumer. - Producers are chosen in round robin order. - - Example usage: - val arb = new RRArbiter(2, UInt()) - arb.io.in(0) <> producer0.io.out - arb.io.in(1) <> producer1.io.out - consumer.io.in <> arb.io.out - */ -class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) - -/** Hardware module that is used to sequence n producers into 1 consumer. - Priority is given to lower producer - - Example usage: - val arb = Module(new Arbiter(2, UInt())) - arb.io.in(0) <> producer0.io.out - arb.io.in(1) <> producer1.io.out - consumer.io.in <> arb.io.out - */ -class Arbiter[T <: Data](gen: T, n: Int) extends Module { - val io = new ArbiterIO(gen, n) - - io.chosen := UInt(n-1) - io.out.bits := io.in(n-1).bits - for (i <- n-2 to 0 by -1) { - when (io.in(i).valid) { - io.chosen := UInt(i) - io.out.bits := io.in(i).bits - } - } - - val grant = ArbiterCtrl(io.in.map(_.valid)) - for ((in, g) <- io.in zip grant) - in.ready := g && io.out.ready - io.out.valid := !grant.last || io.in.last.valid -} diff --git a/src/main/scala/Chisel/util/Bitwise.scala b/src/main/scala/Chisel/util/Bitwise.scala deleted file mode 100644 index 239a295e..00000000 --- a/src/main/scala/Chisel/util/Bitwise.scala +++ /dev/null @@ -1,71 +0,0 @@ -// See LICENSE for license details. - -/** Miscellaneous circuit generators operating on bits. - */ - -package Chisel - -object FillInterleaved -{ - def apply(n: Int, in: UInt): UInt = apply(n, in.toBools) - def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits -} - -/** Returns the number of bits set (i.e value is 1) in the input signal. - */ -object PopCount -{ - def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq) - def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_))) -} - -/** Fill fans out a UInt to multiple copies */ -object Fill { - /** Fan out x n times */ - def apply(n: Int, x: UInt): UInt = { - n match { - case 0 => UInt(width=0) - case 1 => x - case y if n > 1 => - val p2 = Array.ofDim[UInt](log2Up(n + 1)) - p2(0) = x - for (i <- 1 until p2.length) - p2(i) = Cat(p2(i-1), p2(i-1)) - Cat((0 until log2Up(y + 1)).filter(i => (y & (1 << i)) != 0).map(p2(_))) - case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.") - } - } - /** Fan out x n times */ - def apply(n: Int, x: Bool): UInt = - if (n > 1) { - UInt(0,n) - x - } else { - apply(n, x: UInt) - } -} - -/** Litte/big bit endian convertion: reverse the order of the bits in a UInt. -*/ -object Reverse -{ - private def doit(in: UInt, length: Int): UInt = { - if (length == 1) { - in - } else if (isPow2(length) && length >= 8 && length <= 64) { - // This esoterica improves simulation performance - var res = in - var shift = length >> 1 - var mask = UInt((BigInt(1) << length) - 1, length) - do { - mask = mask ^ (mask(length-shift-1,0) << shift) - res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask) - shift = shift >> 1 - } while (shift > 0) - res - } else { - val half = (1 << log2Up(length))/2 - Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half)) - } - } - def apply(in: UInt): UInt = doit(in, in.getWidth) -} diff --git a/src/main/scala/Chisel/util/Cat.scala b/src/main/scala/Chisel/util/Cat.scala deleted file mode 100644 index dd706e62..00000000 --- a/src/main/scala/Chisel/util/Cat.scala +++ /dev/null @@ -1,18 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -object Cat { - /** Combine data elements together - * @param a Data to combine with - * @param r any number of other Data elements to be combined in order - * @return A UInt which is all of the bits combined together - */ - def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList) - - /** Combine data elements together - * @param r any number of other Data elements to be combined in order - * @return A UInt which is all of the bits combined together - */ - def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse) -} diff --git a/src/main/scala/Chisel/util/CircuitMath.scala b/src/main/scala/Chisel/util/CircuitMath.scala deleted file mode 100644 index 06cab903..00000000 --- a/src/main/scala/Chisel/util/CircuitMath.scala +++ /dev/null @@ -1,26 +0,0 @@ -// See LICENSE for license details. - -/** Circuit-land math operations. - */ - -package Chisel - -/** Compute Log2 with truncation of a UInt in hardware using a Mux Tree - * An alternative interpretation is it computes the minimum number of bits needed to represent x - * @example - * {{{ data_out := Log2(data_in) }}} - * @note Truncation is used so Log2(UInt(12412)) = 13*/ -object Log2 { - /** Compute the Log2 on the least significant n bits of x */ - def apply(x: Bits, width: Int): UInt = { - if (width < 2) { - UInt(0) - } else if (width == 2) { - x(1) - } else { - Mux(x(width-1), UInt(width-1), apply(x, width-1)) - } - } - - def apply(x: Bits): UInt = apply(x, x.getWidth) -} diff --git a/src/main/scala/Chisel/util/Conditional.scala b/src/main/scala/Chisel/util/Conditional.scala deleted file mode 100644 index 9cab25ef..00000000 --- a/src/main/scala/Chisel/util/Conditional.scala +++ /dev/null @@ -1,69 +0,0 @@ -// See LICENSE for license details. - -/** Conditional blocks. - */ - -package Chisel - -import scala.language.reflectiveCalls -import scala.language.experimental.macros -import scala.reflect.runtime.universe._ -import scala.reflect.macros.blackbox._ - -/** This is identical to [[Chisel.when when]] with the condition inverted */ -object unless { // scalastyle:ignore object.name - def apply(c: Bool)(block: => Unit) { - when (!c) { block } - } -} - -class SwitchContext[T <: Bits](cond: T) { - def is(v: Iterable[T])(block: => Unit) { - if (!v.isEmpty) when (v.map(_.asUInt === cond.asUInt).reduce(_||_)) { block } - } - def is(v: T)(block: => Unit) { is(Seq(v))(block) } - def is(v: T, vr: T*)(block: => Unit) { is(v :: vr.toList)(block) } -} - -/** An object for separate cases in [[Chisel.switch switch]] - * It is equivalent to a [[Chisel.when$ when]] block comparing to the condition - * Use outside of a switch statement is illegal */ -object is { // scalastyle:ignore object.name - // Begin deprecation of non-type-parameterized is statements. - def apply(v: Iterable[Bits])(block: => Unit) { - require(false, "The 'is' keyword may not be used outside of a switch.") - } - - def apply(v: Bits)(block: => Unit) { - require(false, "The 'is' keyword may not be used outside of a switch.") - } - - def apply(v: Bits, vr: Bits*)(block: => Unit) { - require(false, "The 'is' keyword may not be used outside of a switch.") - } -} - -/** Conditional logic to form a switch block - * @example - * {{{ ... // default values here - * switch ( myState ) { - * is( state1 ) { - * ... // some logic here - * } - * is( state2 ) { - * ... // some logic here - * } - * } }}}*/ -object switch { // scalastyle:ignore object.name - def apply[T <: Bits](cond: T)(x: => Unit): Unit = macro impl - def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._ - val sc = c.universe.internal.reificationSupport.freshTermName("sc") - def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match { - case q"Chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") - case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.") - } - val q"..$body" = x - val ises = body.flatMap(extractIsStatement(_)) - q"""{ val $sc = new SwitchContext($cond); ..$ises }""" - } -} diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/Chisel/util/Counter.scala deleted file mode 100644 index 872e830a..00000000 --- a/src/main/scala/Chisel/util/Counter.scala +++ /dev/null @@ -1,44 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -/** A counter module - * @param n number of counts before the counter resets (or one more than the - * maximum output value of the counter), need not be a power of two - */ -class Counter(val n: Int) { - require(n >= 0) - val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0) - /** Increment the counter, returning whether the counter currently is at the - * maximum and will wrap. The incremented value is registered and will be - * visible on the next cycle. - */ - def inc(): Bool = { - if (n > 1) { - val wrap = value === UInt(n-1) - value := value + UInt(1) - if (!isPow2(n)) { - when (wrap) { value := UInt(0) } - } - wrap - } else { - Bool(true) - } - } -} - -/** Counter Object - * Example Usage: - * {{{ val countOn = Bool(true) // increment counter every clock cycle - * val myCounter = Counter(countOn, n) - * when ( myCounter.value === UInt(3) ) { ... } }}}*/ -object Counter -{ - def apply(n: Int): Counter = new Counter(n) - def apply(cond: Bool, n: Int): (UInt, Bool) = { - val c = new Counter(n) - var wrap: Bool = null - when (cond) { wrap = c.inc() } - (c.value, cond && wrap) - } -} diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/Chisel/util/Decoupled.scala deleted file mode 100644 index 8e045855..00000000 --- a/src/main/scala/Chisel/util/Decoupled.scala +++ /dev/null @@ -1,183 +0,0 @@ -// See LICENSE for license details. - -/** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them. - */ - -package Chisel - -/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/ -class DecoupledIO[+T <: Data](gen: T) extends Bundle -{ - val ready = Bool(INPUT) - val valid = Bool(OUTPUT) - val bits = gen.cloneType.asOutput - def fire(dummy: Int = 0): Bool = ready && valid - override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type] -} - -/** Adds a ready-valid handshaking protocol to any interface. - * The standard used is that the consumer uses the flipped interface. - */ -object Decoupled { - def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen) -} - -/** An I/O bundle for enqueuing data with valid/ready handshaking - * Initialization must be handled, if necessary, by the parent circuit - */ -class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen) -{ - /** push dat onto the output bits of this interface to let the consumer know it has happened. - * @param dat the values to assign to bits. - * @return dat. - */ - def enq(dat: T): T = { valid := Bool(true); bits := dat; dat } - - /** Initialize this Bundle. Valid is set to false, and all bits are set to zero. - * NOTE: This method of initialization is still being discussed and could change in the - * future. - */ - def init(): Unit = { - valid := Bool(false) - for (io <- bits.flatten) - io := UInt(0) - } - override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; } -} - -/** An I/O bundle for dequeuing data with valid/ready handshaking. - * Initialization must be handled, if necessary, by the parent circuit - */ -class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped -{ - /** Assert ready on this port and return the associated data bits. - * This is typically used when valid has been asserted by the producer side. - * @param b ignored - * @return the data for this device, - */ - def deq(b: Boolean = false): T = { ready := Bool(true); bits } - - /** Initialize this Bundle. - * NOTE: This method of initialization is still being discussed and could change in the - * future. - */ - def init(): Unit = { - ready := Bool(false) - } - override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; } -} - -/** An I/O bundle for dequeuing data with valid/ready handshaking */ -class DecoupledIOC[+T <: Data](gen: T) extends Bundle -{ - val ready = Bool(INPUT) - val valid = Bool(OUTPUT) - val bits = gen.cloneType.asOutput -} - -/** An I/O Bundle for Queues - * @param gen The type of data to queue - * @param entries The max number of entries in the queue */ -class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle -{ - /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */ - val enq = Decoupled(gen.cloneType).flip() - /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/ - val deq = Decoupled(gen.cloneType) - /** The current amount of data in the queue */ - val count = UInt(OUTPUT, log2Up(entries + 1)) -} - -/** A hardware module implementing a Queue - * @param gen The type of data to queue - * @param entries The max number of entries in the queue - * @param pipe True if a single entry queue can run at full throughput (like a pipeline). The ''ready'' signals are - * combinationally coupled. - * @param flow True if the inputs can be consumed on the same cycle (the inputs "flow" through the queue immediately). - * The ''valid'' signals are coupled. - * - * Example usage: - * {{{ val q = new Queue(UInt(), 16) - * q.io.enq <> producer.io.out - * consumer.io.in <> q.io.deq }}} - */ -class Queue[T <: Data](gen: T, val entries: Int, - pipe: Boolean = false, - flow: Boolean = false, - override_reset: Option[Bool] = None) -extends Module(override_reset=override_reset) { - def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) = - this(gen, entries, pipe, flow, Some(_reset)) - - val io = new QueueIO(gen, entries) - - val ram = Mem(entries, gen) - val enq_ptr = Counter(entries) - val deq_ptr = Counter(entries) - val maybe_full = Reg(init=Bool(false)) - - val ptr_match = enq_ptr.value === deq_ptr.value - val empty = ptr_match && !maybe_full - val full = ptr_match && maybe_full - val do_enq = Wire(init=io.enq.fire()) - val do_deq = Wire(init=io.deq.fire()) - - when (do_enq) { - ram(enq_ptr.value) := io.enq.bits - enq_ptr.inc() - } - when (do_deq) { - deq_ptr.inc() - } - when (do_enq != do_deq) { - maybe_full := do_enq - } - - io.deq.valid := !empty - io.enq.ready := !full - io.deq.bits := ram(deq_ptr.value) - - if (flow) { - when (io.enq.valid) { io.deq.valid := Bool(true) } - when (empty) { - io.deq.bits := io.enq.bits - do_deq := Bool(false) - when (io.deq.ready) { do_enq := Bool(false) } - } - } - - if (pipe) { - when (io.deq.ready) { io.enq.ready := Bool(true) } - } - - val ptr_diff = enq_ptr.value - deq_ptr.value - if (isPow2(entries)) { - io.count := Cat(maybe_full && ptr_match, ptr_diff) - } else { - io.count := Mux(ptr_match, - Mux(maybe_full, - UInt(entries), UInt(0)), - Mux(deq_ptr.value > enq_ptr.value, - UInt(entries) + ptr_diff, ptr_diff)) - } -} - -/** Generic hardware queue. Required parameter entries controls - the depth of the queues. The width of the queue is determined - from the inputs. - - Example usage: - {{{ val q = Queue(Decoupled(UInt()), 16) - q.io.enq <> producer.io.out - consumer.io.in <> q.io.deq }}} - */ -object Queue -{ - def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T] = { - val q = Module(new Queue(enq.bits.cloneType, entries, pipe)) - q.io.enq.valid := enq.valid // not using <> so that override is allowed - q.io.enq.bits := enq.bits - enq.ready := q.io.enq.ready - TransitName(q.io.deq, q) - } -} diff --git a/src/main/scala/Chisel/util/Enum.scala b/src/main/scala/Chisel/util/Enum.scala deleted file mode 100644 index 20057197..00000000 --- a/src/main/scala/Chisel/util/Enum.scala +++ /dev/null @@ -1,21 +0,0 @@ -// See LICENSE for license details. - -/** Enum generators, allowing circuit constants to have more meaningful names. - */ - -package Chisel - -object Enum { - /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */ - private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] = - (0 until n).map(x => nodeType.fromInt(x, log2Up(n))) - - /** create n enum values of given type */ - def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList - - /** create enum values of given type and names */ - def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap - - /** create enum values of given type and names */ - def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap -} diff --git a/src/main/scala/Chisel/util/LFSR.scala b/src/main/scala/Chisel/util/LFSR.scala deleted file mode 100644 index 839b1d1f..00000000 --- a/src/main/scala/Chisel/util/LFSR.scala +++ /dev/null @@ -1,22 +0,0 @@ -// See LICENSE for license details. - -/** LFSRs in all shapes and sizes. - */ - -package Chisel - -// scalastyle:off magic.number -/** linear feedback shift register - */ -object LFSR16 -{ - def apply(increment: Bool = Bool(true)): UInt = - { - val width = 16 - val lfsr = Reg(init=UInt(1, width)) - when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } - lfsr - } -} -// scalastyle:on magic.number - diff --git a/src/main/scala/Chisel/util/Lookup.scala b/src/main/scala/Chisel/util/Lookup.scala deleted file mode 100644 index 54922fc4..00000000 --- a/src/main/scala/Chisel/util/Lookup.scala +++ /dev/null @@ -1,17 +0,0 @@ -// See LICENSE for license details. - -package Chisel - -object ListLookup { - def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = { - val map = mapping.map(m => (m._1 === addr, m._2)) - default.zipWithIndex map { case (d, i) => - map.foldRight(d)((m, n) => Mux(m._1, m._2(i), n)) - } - } -} - -object Lookup { - def apply[T <: Bits](addr: UInt, default: T, mapping: Seq[(BitPat, T)]): T = - ListLookup(addr, List(default), mapping.map(m => (m._1, List(m._2))).toArray).head -} diff --git a/src/main/scala/Chisel/util/Math.scala b/src/main/scala/Chisel/util/Math.scala deleted file mode 100644 index 5f8212d8..00000000 --- a/src/main/scala/Chisel/util/Math.scala +++ /dev/null @@ -1,42 +0,0 @@ -// See LICENSE for license details. - -/** Scala-land math helper functions, like logs. - */ - -package Chisel - -/** Compute the log2 rounded up with min value of 1 */ -object log2Up { - def apply(in: BigInt): Int = { - require(in >= 0) - 1 max (in-1).bitLength - } - def apply(in: Int): Int = apply(BigInt(in)) -} - -/** Compute the log2 rounded up */ -object log2Ceil { - def apply(in: BigInt): Int = { - require(in > 0) - (in-1).bitLength - } - def apply(in: Int): Int = apply(BigInt(in)) -} - -/** Compute the log2 rounded down with min value of 1 */ -object log2Down { - def apply(in: BigInt): Int = log2Up(in) - (if (isPow2(in)) 0 else 1) - def apply(in: Int): Int = apply(BigInt(in)) -} - -/** Compute the log2 rounded down */ -object log2Floor { - def apply(in: BigInt): Int = log2Ceil(in) - (if (isPow2(in)) 0 else 1) - def apply(in: Int): Int = apply(BigInt(in)) -} - -/** Check if an Integer is a power of 2 */ -object isPow2 { - def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0) - def apply(in: Int): Boolean = apply(BigInt(in)) -} diff --git a/src/main/scala/Chisel/util/Mux.scala b/src/main/scala/Chisel/util/Mux.scala deleted file mode 100644 index 9d92321a..00000000 --- a/src/main/scala/Chisel/util/Mux.scala +++ /dev/null @@ -1,61 +0,0 @@ -// See LICENSE for license details. - -/** Mux circuit generators. - */ - -package Chisel - -/** Builds a Mux tree out of the input signal vector using a one hot encoded - select signal. Returns the output of the Mux tree. - */ -object Mux1H -{ - def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = - apply(sel zip in) - def apply[T <: Data](in: Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in) - def apply[T <: Data](sel: UInt, in: Seq[T]): T = - apply((0 until in.size).map(sel(_)), in) - def apply(sel: UInt, in: UInt): Bool = (sel & in).orR -} - -/** Builds a Mux tree under the assumption that multiple select signals - can be enabled. Priority is given to the first select signal. - - Returns the output of the Mux tree. - */ -object PriorityMux -{ - def apply[T <: Data](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in) - def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in) - def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in) -} - -/** MuxLookup creates a cascade of n Muxs to search for a key value */ -object MuxLookup { - /** @param key a key to search for - * @param default a default value if nothing is found - * @param mapping a sequence to search of keys and values - * @return the value found or the default if not - */ - def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = { - var res = default - for ((k, v) <- mapping.reverse) - res = Mux(k === key, v, res) - res - } - -} - -/** MuxCase returns the first value that is enabled in a map of values */ -object MuxCase { - /** @param default the default value if none are enabled - * @param mapping a set of data values with associated enables - * @return the first value in mapping that is enabled */ - def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = { - var res = default - for ((t, v) <- mapping.reverse){ - res = Mux(t, v, res) - } - res - } -} diff --git a/src/main/scala/Chisel/util/OneHot.scala b/src/main/scala/Chisel/util/OneHot.scala deleted file mode 100644 index 73f27403..00000000 --- a/src/main/scala/Chisel/util/OneHot.scala +++ /dev/null @@ -1,62 +0,0 @@ -// See LICENSE for license details. - -/** Circuit generators for working with one-hot representations. - */ - -package Chisel - -/** Converts from One Hot Encoding to a UInt indicating which bit is active - * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/ -object OHToUInt { - def apply(in: Seq[Bool]): UInt = apply(Vec(in)) - def apply(in: Vec[Bool]): UInt = apply(in.toBits, in.size) - def apply(in: Bits): UInt = apply(in, in.getWidth) - - def apply(in: Bits, width: Int): UInt = { - if (width <= 2) { - Log2(in, width) - } else { - val mid = 1 << (log2Up(width)-1) - val hi = in(width-1, mid) - val lo = in(mid-1, 0) - Cat(hi.orR, apply(hi | lo, mid)) - } - } -} - -/** @return the bit position of the trailing 1 in the input vector - * with the assumption that multiple bits of the input bit vector can be set - * @example {{{ data_out := PriorityEncoder(data_in) }}} - */ -object PriorityEncoder { - def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_))) - def apply(in: Bits): UInt = apply(in.toBools) -} - -/** Returns the one hot encoding of the input UInt. - */ -object UIntToOH -{ - def apply(in: UInt, width: Int = -1): UInt = - if (width == -1) { - UInt(1) << in - } else { - (UInt(1) << in(log2Up(width)-1,0))(width-1,0) - } -} - -/** Returns a bit vector in which only the least-significant 1 bit in - the input vector, if any, is set. - */ -object PriorityEncoderOH -{ - private def encode(in: Seq[Bool]): UInt = { - val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size)) - PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size)) - } - def apply(in: Seq[Bool]): Seq[Bool] = { - val enc = encode(in) - Seq.tabulate(in.size)(enc(_)) - } - def apply(in: Bits): UInt = encode((0 until in.getWidth).map(i => in(i))) -} diff --git a/src/main/scala/Chisel/util/Reg.scala b/src/main/scala/Chisel/util/Reg.scala deleted file mode 100644 index 6584a4bf..00000000 --- a/src/main/scala/Chisel/util/Reg.scala +++ /dev/null @@ -1,55 +0,0 @@ -// See LICENSE for license details. - -/** Variations and helpers for registers. - */ - -package Chisel - -object RegNext { - - def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T]) - - def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init) - -} - -object RegInit { - - def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init) - -} - -/** A register with an Enable signal */ -object RegEnable -{ - def apply[T <: Data](updateData: T, enable: Bool): T = { - val r = Reg(updateData) - when (enable) { r := updateData } - r - } - def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = { - val r = RegInit(resetData) - when (enable) { r := updateData } - r - } -} - -/** Returns the n-cycle delayed version of the input signal. - */ -object ShiftRegister -{ - /** @param in input to delay - * @param n number of cycles to delay - * @param en enable the shift */ - def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = - { - // The order of tests reflects the expected use cases. - if (n == 1) { - RegEnable(in, en) - } else if (n != 0) { - RegNext(apply(in, n-1, en)) - } else { - in - } - } -} diff --git a/src/main/scala/Chisel/util/TransitName.scala b/src/main/scala/Chisel/util/TransitName.scala deleted file mode 100644 index ec5a11cc..00000000 --- a/src/main/scala/Chisel/util/TransitName.scala +++ /dev/null @@ -1,21 +0,0 @@ -package Chisel - -import internal.HasId - -object TransitName { - // The purpose of this is to allow a library to 'move' a name call to a more - // appropriate place. - // For example, a library factory function may create a module and return - // the io. The only user-exposed field is that given IO, which can't use - // any name supplied by the user. This can add a hook so that the supplied - // name then names the Module. - // See Queue companion object for working example - def apply[T<:HasId](from: T, to: HasId): T = { - from.addPostnameHook((given_name: String) => {to.suggestName(given_name)}) - from - } - def withSuffix[T<:HasId](suffix: String)(from: T, to: HasId): T = { - from.addPostnameHook((given_name: String) => {to.suggestName(given_name+suffix)}) - from - } -} diff --git a/src/main/scala/Chisel/util/Valid.scala b/src/main/scala/Chisel/util/Valid.scala deleted file mode 100644 index 9e2202bb..00000000 --- a/src/main/scala/Chisel/util/Valid.scala +++ /dev/null @@ -1,59 +0,0 @@ -// See LICENSE for license details. - -/** Wrappers for valid interfaces and associated circuit generators using them. - */ - -package Chisel - -/** An I/O Bundle containing data and a signal determining if it is valid */ -class ValidIO[+T <: Data](gen2: T) extends Bundle -{ - val valid = Bool(OUTPUT) - val bits = gen2.cloneType.asOutput - def fire(dummy: Int = 0): Bool = valid - override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type] -} - -/** Adds a valid protocol to any interface. The standard used is - that the consumer uses the flipped interface. -*/ -object Valid { - def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen) -} - -/** A hardware module that delays data coming down the pipeline - by the number of cycles set by the latency parameter. Functionality - is similar to ShiftRegister but this exposes a Pipe interface. - - Example usage: - val pipe = new Pipe(UInt()) - pipe.io.enq <> produce.io.out - consumer.io.in <> pipe.io.deq - */ -object Pipe -{ - def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = { - if (latency == 0) { - val out = Wire(Valid(enqBits)) - out.valid <> enqValid - out.bits <> enqBits - out - } else { - val v = Reg(Bool(), next=enqValid, init=Bool(false)) - val b = RegEnable(enqBits, enqValid) - apply(v, b, latency-1) - } - } - def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1) - def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency) -} - -class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module -{ - val io = new Bundle { - val enq = Valid(gen).flip - val deq = Valid(gen) - } - - io.deq <> Pipe(io.enq, latency) -} diff --git a/src/main/scala/chisel/Driver.scala b/src/main/scala/chisel/Driver.scala new file mode 100644 index 00000000..ba2b1389 --- /dev/null +++ b/src/main/scala/chisel/Driver.scala @@ -0,0 +1,132 @@ +// See LICENSE for license details. + +package chisel + +import scala.sys.process._ +import java.io._ + +import internal._ +import internal.firrtl._ + +trait BackendCompilationUtilities { + /** Create a temporary directory with the prefix name. Exists here because it doesn't in Java 6. + */ + def createTempDirectory(prefix: String): File = { + val temp = File.createTempFile(prefix, "") + if (!temp.delete()) { + throw new IOException(s"Unable to delete temp file '$temp'") + } + if (!temp.mkdir()) { + throw new IOException(s"Unable to create temp directory '$temp'") + } + temp + } + + def makeHarness(template: String => String, post: String)(f: File): File = { + val prefix = f.toString.split("/").last + val vf = new File(f.toString + post) + val w = new FileWriter(vf) + w.write(template(prefix)) + w.close() + vf + } + + def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder = { + Process( + Seq("firrtl", + "-i", s"$prefix.fir", + "-o", s"$prefix.v", + "-X", "verilog"), + dir) + } + + /** Generates a Verilator invocation to convert Verilog sources to C++ + * simulation sources. + * + * The Verilator prefix will be V$dutFile, and running this will generate + * C++ sources and headers as well as a makefile to compile them. + * + * @param dutFile name of the DUT .v without the .v extension + * @param name of the top-level module in the design + * @param dir output directory + * @param vSources list of additional Verilog sources to compile + * @param cppHarness C++ testharness to compile/link against + */ + def verilogToCpp( + dutFile: String, + topModule: String, + dir: File, + vSources: Seq[File], + cppHarness: File + ): ProcessBuilder = { + val command = Seq("verilator", + "--cc", s"$dutFile.v") ++ + vSources.map(file => Seq("-v", file.toString)).flatten ++ + Seq("--assert", + "-Wno-fatal", + "-Wno-WIDTH", + "-Wno-STMTDLY", + "--trace", + "-O2", + "--top-module", topModule, + "+define+TOP_TYPE=V" + dutFile, + s"+define+PRINTF_COND=!$topModule.reset", + "-CFLAGS", + s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""", + "-Mdir", dir.toString, + "--exe", cppHarness.toString) + System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex + command + } + + def cppToExe(prefix: String, dir: File): ProcessBuilder = + Seq("make", "-C", dir.toString, "-j", "-f", s"V${prefix}.mk", s"V${prefix}") + + def executeExpectingFailure( + prefix: String, + dir: File, + assertionMsg: String = "Assertion failed"): Boolean = { + var triggered = false + val e = Process(s"./V${prefix}", dir) ! + ProcessLogger(line => { + triggered = triggered || line.contains(assertionMsg) + System.out.println(line) // scalastyle:ignore regex + }) + triggered + } + + def executeExpectingSuccess(prefix: String, dir: File): Boolean = { + !executeExpectingFailure(prefix, dir) + } +} + +object Driver extends BackendCompilationUtilities { + + /** Elaborates the Module specified in the gen function into a Circuit + * + * @param gen a function that creates a Module hierarchy + * @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR) + */ + def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen())) + + def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen)) + + def dumpFirrtl(ir: Circuit, optName: Option[File]): File = { + val f = optName.getOrElse(new File(ir.name + ".fir")) + val w = new FileWriter(f) + w.write(Emitter.emit(ir)) + w.close() + f + } + + private var target_dir: Option[String] = None + def parseArgs(args: Array[String]): Unit = { + for (i <- 0 until args.size) { + if (args(i) == "--targetDir") { + target_dir = Some(args(i + 1)) + } + } + } + + def targetDir(): String = { target_dir getOrElse new File(".").getCanonicalPath } +} diff --git a/src/main/scala/chisel/FileSystemUtilities.scala b/src/main/scala/chisel/FileSystemUtilities.scala new file mode 100644 index 00000000..f100eaf6 --- /dev/null +++ b/src/main/scala/chisel/FileSystemUtilities.scala @@ -0,0 +1,10 @@ +// See LICENSE for license details. + +package chisel + +@deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0") +trait FileSystemUtilities { + def createOutputFile(name: String): java.io.FileWriter = { + new java.io.FileWriter(Driver.targetDir + "/" + name) + } +} diff --git a/src/main/scala/chisel/ImplicitConversions.scala b/src/main/scala/chisel/ImplicitConversions.scala new file mode 100644 index 00000000..f786d4f1 --- /dev/null +++ b/src/main/scala/chisel/ImplicitConversions.scala @@ -0,0 +1,8 @@ +// See LICENSE for license details. + +package chisel + +object ImplicitConversions { + implicit def intToUInt(x: Int): UInt = UInt(x) + implicit def booleanToBool(x: Boolean): Bool = Bool(x) +} diff --git a/src/main/scala/chisel/Main.scala b/src/main/scala/chisel/Main.scala new file mode 100644 index 00000000..79e5c9ca --- /dev/null +++ b/src/main/scala/chisel/Main.scala @@ -0,0 +1,17 @@ +// See LICENSE for license details. + +package chisel + +import java.io.File + +@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain { + def apply[T <: Module](args: Array[String], gen: () => T): Unit = + Predef.assert(false, "No more chiselMain in Chisel3") + + def run[T <: Module] (args: Array[String], gen: () => T): Unit = { + val circuit = Driver.elaborate(gen) + Driver.parseArgs(args) + val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir") + Driver.dumpFirrtl(circuit, Option(output_file)) + } +} diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala new file mode 100644 index 00000000..80936a42 --- /dev/null +++ b/src/main/scala/chisel/compatibility.scala @@ -0,0 +1,139 @@ +// See LICENSE for license details. + +// Allows legacy users to continue using Chisel (capital C) package name while +// moving to the more standard package naming convention chisel (lowercase c). + +package object Chisel { + type Direction = chisel.Direction + val INPUT = chisel.INPUT + val OUTPUT = chisel.OUTPUT + val NO_DIR = chisel.NO_DIR + val debug = chisel.debug + type Flipped = chisel.Flipped + type Data = chisel.Data + val Wire = chisel.Wire + val Clock = chisel.Clock + type Clock = chisel.Clock + + type Aggregate = chisel.Aggregate + val Vec = chisel.Vec + type Vec[T <: Data] = chisel.Vec[T] + type VecLike[T <: Data] = chisel.VecLike[T] + type Bundle = chisel.Bundle + + val assert = chisel.assert + + val BitPat = chisel.BitPat + type BitPat = chisel.BitPat + + type Bits = chisel.Bits + val Bits = chisel.Bits + type Num[T <: Data] = chisel.Num[T] + type UInt = chisel.UInt + val UInt = chisel.UInt + type SInt = chisel.SInt + val SInt = chisel.SInt + type Bool = chisel.Bool + val Bool = chisel.Bool + val Mux = chisel.Mux + + type BlackBox = chisel.BlackBox + + val Mem = chisel.Mem + type MemBase[T <: Data] = chisel.MemBase[T] + type Mem[T <: Data] = chisel.Mem[T] + val SeqMem = chisel.SeqMem + type SeqMem[T <: Data] = chisel.SeqMem[T] + + val Module = chisel.Module + type Module = chisel.Module + + val printf = chisel.printf + + val Reg = chisel.Reg + + val when = chisel.when + type WhenContext = chisel.WhenContext + + + type BackendCompilationUtilities = chisel.BackendCompilationUtilities + val Driver = chisel.Driver + type FileSystemUtilities = chisel.FileSystemUtilities + val ImplicitConversions = chisel.ImplicitConversions + val chiselMain = chisel.chiselMain + val throwException = chisel.throwException + + + val log2Up = chisel.log2Up + val log2Ceil = chisel.log2Ceil + val log2Down = chisel.log2Down + val log2Floor = chisel.log2Floor + val isPow2 = chisel.isPow2 + + type ArbiterIO[T <: Data] = chisel.ArbiterIO[T] + type LockingArbiterLike[T <: Data] = chisel.LockingArbiterLike[T] + type LockingRRArbiter[T <: Data] = chisel.LockingRRArbiter[T] + type LockingArbiter[T <: Data] = chisel.LockingArbiter[T] + type RRArbiter[T <: Data] = chisel.RRArbiter[T] + type Arbiter[T <: Data] = chisel.Arbiter[T] + + val FillInterleaved = chisel.FillInterleaved + val PopCount = chisel.PopCount + val Fill = chisel.Fill + val Reverse = chisel.Reverse + + val Cat = chisel.Cat + + val Log2 = chisel.Log2 + + val unless = chisel.unless + type SwitchContext[T <: Bits] = chisel.SwitchContext[T] + val is = chisel.is + val switch = chisel.switch + + type Counter = chisel.Counter + val Counter = chisel.Counter + + type DecoupledIO[+T <: Data] = chisel.DecoupledIO[T] + val Decoupled = chisel.Decoupled + type EnqIO[T <: Data] = chisel.EnqIO[T] + type DeqIO[T <: Data] = chisel.DeqIO[T] + type DecoupledIOC[+T <: Data] = chisel.DecoupledIOC[T] + type QueueIO[T <: Data] = chisel.QueueIO[T] + type Queue[T <: Data] = chisel.Queue[T] + val Queue = chisel.Queue + + val Enum = chisel.Enum + + val LFSR16 = chisel.LFSR16 + + val ListLookup = chisel.ListLookup + val Lookup = chisel.Lookup + + val Mux1H = chisel.Mux1H + val PriorityMux = chisel.PriorityMux + val MuxLookup = chisel.MuxLookup + val MuxCase = chisel.MuxCase + + val OHToUInt = chisel.OHToUInt + val PriorityEncoder = chisel.PriorityEncoder + val UIntToOH = chisel.UIntToOH + val PriorityEncoderOH = chisel.PriorityEncoderOH + + val RegNext = chisel.RegNext + val RegInit = chisel.RegInit + val RegEnable = chisel.RegEnable + val ShiftRegister = chisel.ShiftRegister + + type ValidIO[+T <: Data] = chisel.ValidIO[T] + val Valid = chisel.Valid + val Pipe = chisel.Pipe + type Pipe[T <: Data] = chisel.Pipe[T] +} + +package Chisel { + package object testers { + type BasicTester = chisel.testers.BasicTester + val TesterDriver = chisel.testers.TesterDriver + } +} diff --git a/src/main/scala/chisel/internal/firrtl/Emitter.scala b/src/main/scala/chisel/internal/firrtl/Emitter.scala new file mode 100644 index 00000000..e48eb226 --- /dev/null +++ b/src/main/scala/chisel/internal/firrtl/Emitter.scala @@ -0,0 +1,112 @@ +// See LICENSE for license details. + +package chisel.internal.firrtl +import chisel._ +import chisel.internal.sourceinfo.{NoSourceInfo, SourceLine} + +private[chisel] object Emitter { + def emit(circuit: Circuit): String = new Emitter(circuit).toString +} + +private class Emitter(circuit: Circuit) { + override def toString: String = res.toString + + private def emitPort(e: Port): String = + s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}" + private def emit(e: Command, ctx: Component): String = { + val firrtlLine = e match { + case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})" + case e: DefWire => s"wire ${e.name} : ${e.id.toType}" + case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}" + case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" + case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]" + case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]" + case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" + case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" + case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" + case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})" + case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})""" + case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid" + case e: DefInstance => { + val modName = moduleMap.get(e.id.name).get + s"inst ${e.name} of $modName" + } + + case w: WhenBegin => + indent() + s"when ${w.pred.fullName(ctx)} :" + case _: WhenEnd => + unindent() + s"skip" + } + e.sourceInfo match { + case SourceLine(filename, line, col) => s"${firrtlLine} @[${filename} ${line}:${col}] " + case _: NoSourceInfo => firrtlLine + } + } + + // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already. + private val defnMap = collection.mutable.HashMap[String, String]() + // Map of Component name to FIRRTL id. + private val moduleMap = collection.mutable.HashMap[String, String]() + + /** Generates the FIRRTL module definition with a specified name. + */ + private def moduleDefn(m: Component, name: String): String = { + val body = new StringBuilder + m.id match { + case _: BlackBox => body ++= newline + s"extmodule $name : " + case _: Module => body ++= newline + s"module $name : " + } + withIndent { + for (p <- m.ports) + body ++= newline + emitPort(p) + body ++= newline + + m.id match { + case _: BlackBox => + // TODO: BlackBoxes should be empty, but funkiness in Module() means + // it's not for now. Eventually, this should assert out. + case _: Module => for (cmd <- m.commands) { + body ++= newline + emit(cmd, m) + } + } + body ++= newline + } + body.toString() + } + + /** Returns the FIRRTL declaration and body of a module, or nothing if it's a + * duplicate of something already emitted (on the basis of simple string + * matching). + */ + private def emit(m: Component): String = { + // Generate the body. + val moduleName = m.id.getClass.getName.split('.').last + val defn = moduleDefn(m, moduleName) + + defnMap get defn match { + case Some(deduplicatedName) => + moduleMap(m.name) = deduplicatedName + "" + case None => + require(!(moduleMap contains m.name), + "emitting module with same name but different contents") + + moduleMap(m.name) = m.name + defnMap(defn) = m.name + + moduleDefn(m, m.name) + } + } + + private var indentLevel = 0 + private def newline = "\n" + (" " * indentLevel) + private def indent(): Unit = indentLevel += 1 + private def unindent() { require(indentLevel > 0); indentLevel -= 1 } + private def withIndent(f: => Unit) { indent(); f; unindent() } + + private val res = new StringBuilder(s"circuit ${circuit.name} : ") + withIndent { circuit.components.foreach(c => res ++= emit(c)) } + res ++= newline +} diff --git a/src/main/scala/chisel/package.scala b/src/main/scala/chisel/package.scala new file mode 100644 index 00000000..1abbc74f --- /dev/null +++ b/src/main/scala/chisel/package.scala @@ -0,0 +1,31 @@ +package object chisel { + import scala.language.experimental.macros + + import internal.firrtl.Width + import internal.sourceinfo.{SourceInfo, SourceInfoTransform} + + implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { + def U: UInt = UInt(x, Width()) + def S: SInt = SInt(x, Width()) + } + implicit class fromIntToLiteral(val x: Int) extends AnyVal { + def U: UInt = UInt(BigInt(x), Width()) + def S: SInt = SInt(BigInt(x), Width()) + } + implicit class fromStringToLiteral(val x: String) extends AnyVal { + def U: UInt = UInt(x) + } + implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { + def B: Bool = Bool(x) + } + + implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal { + final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg + final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg + final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg + + def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x + def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x + def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x + } +} diff --git a/src/main/scala/chisel/testers/BasicTester.scala b/src/main/scala/chisel/testers/BasicTester.scala new file mode 100644 index 00000000..36ff7c52 --- /dev/null +++ b/src/main/scala/chisel/testers/BasicTester.scala @@ -0,0 +1,38 @@ +// See LICENSE for license details. + +package chisel.testers +import chisel._ + +import scala.language.experimental.macros + +import internal._ +import internal.Builder.pushCommand +import internal.firrtl._ +import internal.sourceinfo.SourceInfo + +class BasicTester extends Module { + // The testbench has no IOs, rather it should communicate using printf, assert, and stop. + val io = new Bundle() + + def popCount(n: Long): Int = n.toBinaryString.count(_=='1') + + /** Ends the test reporting success. + * + * Does not fire when in reset (defined as the encapsulating Module's + * reset). If your definition of reset is not the encapsulating Module's + * reset, you will need to gate this externally. + */ + def stop()(implicit sourceInfo: SourceInfo) { + // TODO: rewrite this using library-style SourceInfo passing. + when (!reset) { + pushCommand(Stop(sourceInfo, Node(clock), 0)) + } + } + + /** The finish method provides a hook that subclasses of BasicTester can use to + * alter a circuit after their constructor has been called. + * For example, a specialized tester subclassing BasicTester could override finish in order to + * add flow control logic for a decoupled io port of a device under test + */ + def finish(): Unit = {} +} diff --git a/src/main/scala/chisel/testers/TesterDriver.scala b/src/main/scala/chisel/testers/TesterDriver.scala new file mode 100644 index 00000000..5c0275e0 --- /dev/null +++ b/src/main/scala/chisel/testers/TesterDriver.scala @@ -0,0 +1,69 @@ +// See LICENSE for license details. + +package chisel.testers + +import chisel._ +import scala.io.Source +import scala.sys.process._ +import java.io._ + +object TesterDriver extends BackendCompilationUtilities { + /** Copy the contents of a resource to a destination file. + */ + def copyResourceToFile(name: String, file: File) { + val in = getClass().getResourceAsStream(name) + if (in == null) { + throw new FileNotFoundException(s"Resource '$name'") + } + val out = new FileOutputStream(file) + Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write) + out.close() + } + + /** For use with modules that should successfully be elaborated by the + * frontend, and which can be turned into executables with assertions. */ + def execute(t: () => BasicTester, additionalVResources: Seq[String] = Seq()): Boolean = { + // Invoke the chisel compiler to get the circuit's IR + val circuit = Driver.elaborate(finishWrapper(t)) + + // Set up a bunch of file handlers based on a random temp filename, + // plus the quirks of Verilator's naming conventions + val target = circuit.name + + val path = createTempDirectory(target) + val fname = new File(path, target) + + // For now, dump the IR out to a file + Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir"))) + + // Copy CPP harness and other Verilog sources from resources into files + val cppHarness = new File(path, "top.cpp") + copyResourceToFile("/top.cpp", cppHarness) + val additionalVFiles = additionalVResources.map((name: String) => { + val mangledResourceName = name.replace("/", "_") + val out = new File(path, mangledResourceName) + copyResourceToFile(name, out) + out + }) + + // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe + if ((firrtlToVerilog(target, path) #&& + verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& + cppToExe(target, path)).! == 0) { + executeExpectingSuccess(target, path) + } else { + false + } + } + /** + * Calls the finish method of an BasicTester or a class that extends it. + * The finish method is a hook for code that augments the circuit built in the constructor. + */ + def finishWrapper(test: () => BasicTester): () => BasicTester = { + () => { + val tester = test() + tester.finish() + tester + } + } +} diff --git a/src/main/scala/chisel/throwException.scala b/src/main/scala/chisel/throwException.scala new file mode 100644 index 00000000..fdd62c7e --- /dev/null +++ b/src/main/scala/chisel/throwException.scala @@ -0,0 +1,12 @@ +// See LICENSE for license details. + +package chisel + +@deprecated("throwException doesn't exist in Chisel3", "3.0.0") +@throws(classOf[Exception]) +object throwException { + def apply(s: String, t: Throwable = null) = { + val xcpt = new Exception(s, t) + throw xcpt + } +} diff --git a/src/main/scala/chisel/util/Arbiter.scala b/src/main/scala/chisel/util/Arbiter.scala new file mode 100644 index 00000000..afe48963 --- /dev/null +++ b/src/main/scala/chisel/util/Arbiter.scala @@ -0,0 +1,117 @@ +// See LICENSE for license details. + +/** Arbiters in all shapes and sizes. + */ + +package chisel + +/** An I/O bundle for the Arbiter */ +class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { + val in = Vec(n, Decoupled(gen)).flip + val out = Decoupled(gen) + val chosen = UInt(OUTPUT, log2Up(n)) +} + +/** Arbiter Control determining which producer has access */ +private object ArbiterCtrl +{ + def apply(request: Seq[Bool]): Seq[Bool] = request.length match { + case 0 => Seq() + case 1 => Seq(Bool(true)) + case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_) + } +} + +abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module { + def grant: Seq[Bool] + def choice: UInt + val io = new ArbiterIO(gen, n) + + io.chosen := choice + io.out.valid := io.in(io.chosen).valid + io.out.bits := io.in(io.chosen).bits + + if (count > 1) { + val lockCount = Counter(count) + val lockIdx = Reg(UInt()) + val locked = lockCount.value =/= UInt(0) + val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true)) + + when (io.out.fire() && wantsLock) { + lockIdx := io.chosen + lockCount.inc() + } + + when (locked) { io.chosen := lockIdx } + for ((in, (g, i)) <- io.in zip grant.zipWithIndex) + in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready + } else { + for ((in, g) <- io.in zip grant) + in.ready := g && io.out.ready + } +} + +class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) + extends LockingArbiterLike[T](gen, n, count, needsLock) { + lazy val lastGrant = RegEnable(io.chosen, io.out.fire()) + lazy val grantMask = (0 until n).map(UInt(_) > lastGrant) + lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g } + + override def grant: Seq[Bool] = { + val ctrl = ArbiterCtrl((0 until n).map(i => validMask(i)) ++ io.in.map(_.valid)) + (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n)) + } + + override lazy val choice = Wire(init=UInt(n-1)) + for (i <- n-2 to 0 by -1) + when (io.in(i).valid) { choice := UInt(i) } + for (i <- n-1 to 1 by -1) + when (validMask(i)) { choice := UInt(i) } +} + +class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) + extends LockingArbiterLike[T](gen, n, count, needsLock) { + def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid)) + + override lazy val choice = Wire(init=UInt(n-1)) + for (i <- n-2 to 0 by -1) + when (io.in(i).valid) { choice := UInt(i) } +} + +/** Hardware module that is used to sequence n producers into 1 consumer. + Producers are chosen in round robin order. + + Example usage: + val arb = new RRArbiter(2, UInt()) + arb.io.in(0) <> producer0.io.out + arb.io.in(1) <> producer1.io.out + consumer.io.in <> arb.io.out + */ +class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) + +/** Hardware module that is used to sequence n producers into 1 consumer. + Priority is given to lower producer + + Example usage: + val arb = Module(new Arbiter(2, UInt())) + arb.io.in(0) <> producer0.io.out + arb.io.in(1) <> producer1.io.out + consumer.io.in <> arb.io.out + */ +class Arbiter[T <: Data](gen: T, n: Int) extends Module { + val io = new ArbiterIO(gen, n) + + io.chosen := UInt(n-1) + io.out.bits := io.in(n-1).bits + for (i <- n-2 to 0 by -1) { + when (io.in(i).valid) { + io.chosen := UInt(i) + io.out.bits := io.in(i).bits + } + } + + val grant = ArbiterCtrl(io.in.map(_.valid)) + for ((in, g) <- io.in zip grant) + in.ready := g && io.out.ready + io.out.valid := !grant.last || io.in.last.valid +} diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala new file mode 100644 index 00000000..27064059 --- /dev/null +++ b/src/main/scala/chisel/util/Bitwise.scala @@ -0,0 +1,71 @@ +// See LICENSE for license details. + +/** Miscellaneous circuit generators operating on bits. + */ + +package chisel + +object FillInterleaved +{ + def apply(n: Int, in: UInt): UInt = apply(n, in.toBools) + def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits +} + +/** Returns the number of bits set (i.e value is 1) in the input signal. + */ +object PopCount +{ + def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq) + def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_))) +} + +/** Fill fans out a UInt to multiple copies */ +object Fill { + /** Fan out x n times */ + def apply(n: Int, x: UInt): UInt = { + n match { + case 0 => UInt(width=0) + case 1 => x + case y if n > 1 => + val p2 = Array.ofDim[UInt](log2Up(n + 1)) + p2(0) = x + for (i <- 1 until p2.length) + p2(i) = Cat(p2(i-1), p2(i-1)) + Cat((0 until log2Up(y + 1)).filter(i => (y & (1 << i)) != 0).map(p2(_))) + case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.") + } + } + /** Fan out x n times */ + def apply(n: Int, x: Bool): UInt = + if (n > 1) { + UInt(0,n) - x + } else { + apply(n, x: UInt) + } +} + +/** Litte/big bit endian convertion: reverse the order of the bits in a UInt. +*/ +object Reverse +{ + private def doit(in: UInt, length: Int): UInt = { + if (length == 1) { + in + } else if (isPow2(length) && length >= 8 && length <= 64) { + // This esoterica improves simulation performance + var res = in + var shift = length >> 1 + var mask = UInt((BigInt(1) << length) - 1, length) + do { + mask = mask ^ (mask(length-shift-1,0) << shift) + res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask) + shift = shift >> 1 + } while (shift > 0) + res + } else { + val half = (1 << log2Up(length))/2 + Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half)) + } + } + def apply(in: UInt): UInt = doit(in, in.getWidth) +} diff --git a/src/main/scala/chisel/util/Cat.scala b/src/main/scala/chisel/util/Cat.scala new file mode 100644 index 00000000..a35619df --- /dev/null +++ b/src/main/scala/chisel/util/Cat.scala @@ -0,0 +1,18 @@ +// See LICENSE for license details. + +package chisel + +object Cat { + /** Combine data elements together + * @param a Data to combine with + * @param r any number of other Data elements to be combined in order + * @return A UInt which is all of the bits combined together + */ + def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList) + + /** Combine data elements together + * @param r any number of other Data elements to be combined in order + * @return A UInt which is all of the bits combined together + */ + def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse) +} diff --git a/src/main/scala/chisel/util/CircuitMath.scala b/src/main/scala/chisel/util/CircuitMath.scala new file mode 100644 index 00000000..001be802 --- /dev/null +++ b/src/main/scala/chisel/util/CircuitMath.scala @@ -0,0 +1,26 @@ +// See LICENSE for license details. + +/** Circuit-land math operations. + */ + +package chisel + +/** Compute Log2 with truncation of a UInt in hardware using a Mux Tree + * An alternative interpretation is it computes the minimum number of bits needed to represent x + * @example + * {{{ data_out := Log2(data_in) }}} + * @note Truncation is used so Log2(UInt(12412)) = 13*/ +object Log2 { + /** Compute the Log2 on the least significant n bits of x */ + def apply(x: Bits, width: Int): UInt = { + if (width < 2) { + UInt(0) + } else if (width == 2) { + x(1) + } else { + Mux(x(width-1), UInt(width-1), apply(x, width-1)) + } + } + + def apply(x: Bits): UInt = apply(x, x.getWidth) +} diff --git a/src/main/scala/chisel/util/Conditional.scala b/src/main/scala/chisel/util/Conditional.scala new file mode 100644 index 00000000..94f00080 --- /dev/null +++ b/src/main/scala/chisel/util/Conditional.scala @@ -0,0 +1,71 @@ +// See LICENSE for license details. + +/** Conditional blocks. + */ + +package chisel + +import scala.language.reflectiveCalls +import scala.language.experimental.macros +import scala.reflect.runtime.universe._ +import scala.reflect.macros.blackbox._ + +/** This is identical to [[Chisel.when when]] with the condition inverted */ +object unless { // scalastyle:ignore object.name + def apply(c: Bool)(block: => Unit) { + when (!c) { block } + } +} + +class SwitchContext[T <: Bits](cond: T) { + def is(v: Iterable[T])(block: => Unit) { + if (!v.isEmpty) when (v.map(_.asUInt === cond.asUInt).reduce(_||_)) { block } + } + def is(v: T)(block: => Unit) { is(Seq(v))(block) } + def is(v: T, vr: T*)(block: => Unit) { is(v :: vr.toList)(block) } +} + +/** An object for separate cases in [[Chisel.switch switch]] + * It is equivalent to a [[Chisel.when$ when]] block comparing to the condition + * Use outside of a switch statement is illegal */ +object is { // scalastyle:ignore object.name + // Begin deprecation of non-type-parameterized is statements. + def apply(v: Iterable[Bits])(block: => Unit) { + require(false, "The 'is' keyword may not be used outside of a switch.") + } + + def apply(v: Bits)(block: => Unit) { + require(false, "The 'is' keyword may not be used outside of a switch.") + } + + def apply(v: Bits, vr: Bits*)(block: => Unit) { + require(false, "The 'is' keyword may not be used outside of a switch.") + } +} + +/** Conditional logic to form a switch block + * @example + * {{{ ... // default values here + * switch ( myState ) { + * is( state1 ) { + * ... // some logic here + * } + * is( state2 ) { + * ... // some logic here + * } + * } }}}*/ +object switch { // scalastyle:ignore object.name + def apply[T <: Bits](cond: T)(x: => Unit): Unit = macro impl + def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._ + val sc = c.universe.internal.reificationSupport.freshTermName("sc") + def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match { + // TODO: remove when Chisel compatibility package is removed + case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") + case q"chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") + case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.") + } + val q"..$body" = x + val ises = body.flatMap(extractIsStatement(_)) + q"""{ val $sc = new SwitchContext($cond); ..$ises }""" + } +} diff --git a/src/main/scala/chisel/util/Counter.scala b/src/main/scala/chisel/util/Counter.scala new file mode 100644 index 00000000..dde1e347 --- /dev/null +++ b/src/main/scala/chisel/util/Counter.scala @@ -0,0 +1,44 @@ +// See LICENSE for license details. + +package chisel + +/** A counter module + * @param n number of counts before the counter resets (or one more than the + * maximum output value of the counter), need not be a power of two + */ +class Counter(val n: Int) { + require(n >= 0) + val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0) + /** Increment the counter, returning whether the counter currently is at the + * maximum and will wrap. The incremented value is registered and will be + * visible on the next cycle. + */ + def inc(): Bool = { + if (n > 1) { + val wrap = value === UInt(n-1) + value := value + UInt(1) + if (!isPow2(n)) { + when (wrap) { value := UInt(0) } + } + wrap + } else { + Bool(true) + } + } +} + +/** Counter Object + * Example Usage: + * {{{ val countOn = Bool(true) // increment counter every clock cycle + * val myCounter = Counter(countOn, n) + * when ( myCounter.value === UInt(3) ) { ... } }}}*/ +object Counter +{ + def apply(n: Int): Counter = new Counter(n) + def apply(cond: Bool, n: Int): (UInt, Bool) = { + val c = new Counter(n) + var wrap: Bool = null + when (cond) { wrap = c.inc() } + (c.value, cond && wrap) + } +} diff --git a/src/main/scala/chisel/util/Decoupled.scala b/src/main/scala/chisel/util/Decoupled.scala new file mode 100644 index 00000000..955b0870 --- /dev/null +++ b/src/main/scala/chisel/util/Decoupled.scala @@ -0,0 +1,183 @@ +// See LICENSE for license details. + +/** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them. + */ + +package chisel + +/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/ +class DecoupledIO[+T <: Data](gen: T) extends Bundle +{ + val ready = Bool(INPUT) + val valid = Bool(OUTPUT) + val bits = gen.cloneType.asOutput + def fire(dummy: Int = 0): Bool = ready && valid + override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type] +} + +/** Adds a ready-valid handshaking protocol to any interface. + * The standard used is that the consumer uses the flipped interface. + */ +object Decoupled { + def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen) +} + +/** An I/O bundle for enqueuing data with valid/ready handshaking + * Initialization must be handled, if necessary, by the parent circuit + */ +class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen) +{ + /** push dat onto the output bits of this interface to let the consumer know it has happened. + * @param dat the values to assign to bits. + * @return dat. + */ + def enq(dat: T): T = { valid := Bool(true); bits := dat; dat } + + /** Initialize this Bundle. Valid is set to false, and all bits are set to zero. + * NOTE: This method of initialization is still being discussed and could change in the + * future. + */ + def init(): Unit = { + valid := Bool(false) + for (io <- bits.flatten) + io := UInt(0) + } + override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; } +} + +/** An I/O bundle for dequeuing data with valid/ready handshaking. + * Initialization must be handled, if necessary, by the parent circuit + */ +class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped +{ + /** Assert ready on this port and return the associated data bits. + * This is typically used when valid has been asserted by the producer side. + * @param b ignored + * @return the data for this device, + */ + def deq(b: Boolean = false): T = { ready := Bool(true); bits } + + /** Initialize this Bundle. + * NOTE: This method of initialization is still being discussed and could change in the + * future. + */ + def init(): Unit = { + ready := Bool(false) + } + override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; } +} + +/** An I/O bundle for dequeuing data with valid/ready handshaking */ +class DecoupledIOC[+T <: Data](gen: T) extends Bundle +{ + val ready = Bool(INPUT) + val valid = Bool(OUTPUT) + val bits = gen.cloneType.asOutput +} + +/** An I/O Bundle for Queues + * @param gen The type of data to queue + * @param entries The max number of entries in the queue */ +class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle +{ + /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */ + val enq = Decoupled(gen.cloneType).flip() + /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/ + val deq = Decoupled(gen.cloneType) + /** The current amount of data in the queue */ + val count = UInt(OUTPUT, log2Up(entries + 1)) +} + +/** A hardware module implementing a Queue + * @param gen The type of data to queue + * @param entries The max number of entries in the queue + * @param pipe True if a single entry queue can run at full throughput (like a pipeline). The ''ready'' signals are + * combinationally coupled. + * @param flow True if the inputs can be consumed on the same cycle (the inputs "flow" through the queue immediately). + * The ''valid'' signals are coupled. + * + * Example usage: + * {{{ val q = new Queue(UInt(), 16) + * q.io.enq <> producer.io.out + * consumer.io.in <> q.io.deq }}} + */ +class Queue[T <: Data](gen: T, val entries: Int, + pipe: Boolean = false, + flow: Boolean = false, + override_reset: Option[Bool] = None) +extends Module(override_reset=override_reset) { + def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) = + this(gen, entries, pipe, flow, Some(_reset)) + + val io = new QueueIO(gen, entries) + + val ram = Mem(entries, gen) + val enq_ptr = Counter(entries) + val deq_ptr = Counter(entries) + val maybe_full = Reg(init=Bool(false)) + + val ptr_match = enq_ptr.value === deq_ptr.value + val empty = ptr_match && !maybe_full + val full = ptr_match && maybe_full + val do_enq = Wire(init=io.enq.fire()) + val do_deq = Wire(init=io.deq.fire()) + + when (do_enq) { + ram(enq_ptr.value) := io.enq.bits + enq_ptr.inc() + } + when (do_deq) { + deq_ptr.inc() + } + when (do_enq != do_deq) { + maybe_full := do_enq + } + + io.deq.valid := !empty + io.enq.ready := !full + io.deq.bits := ram(deq_ptr.value) + + if (flow) { + when (io.enq.valid) { io.deq.valid := Bool(true) } + when (empty) { + io.deq.bits := io.enq.bits + do_deq := Bool(false) + when (io.deq.ready) { do_enq := Bool(false) } + } + } + + if (pipe) { + when (io.deq.ready) { io.enq.ready := Bool(true) } + } + + val ptr_diff = enq_ptr.value - deq_ptr.value + if (isPow2(entries)) { + io.count := Cat(maybe_full && ptr_match, ptr_diff) + } else { + io.count := Mux(ptr_match, + Mux(maybe_full, + UInt(entries), UInt(0)), + Mux(deq_ptr.value > enq_ptr.value, + UInt(entries) + ptr_diff, ptr_diff)) + } +} + +/** Generic hardware queue. Required parameter entries controls + the depth of the queues. The width of the queue is determined + from the inputs. + + Example usage: + {{{ val q = Queue(Decoupled(UInt()), 16) + q.io.enq <> producer.io.out + consumer.io.in <> q.io.deq }}} + */ +object Queue +{ + def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T] = { + val q = Module(new Queue(enq.bits.cloneType, entries, pipe)) + q.io.enq.valid := enq.valid // not using <> so that override is allowed + q.io.enq.bits := enq.bits + enq.ready := q.io.enq.ready + TransitName(q.io.deq, q) + } +} diff --git a/src/main/scala/chisel/util/Enum.scala b/src/main/scala/chisel/util/Enum.scala new file mode 100644 index 00000000..2757a06c --- /dev/null +++ b/src/main/scala/chisel/util/Enum.scala @@ -0,0 +1,21 @@ +// See LICENSE for license details. + +/** Enum generators, allowing circuit constants to have more meaningful names. + */ + +package chisel + +object Enum { + /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */ + private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] = + (0 until n).map(x => nodeType.fromInt(x, log2Up(n))) + + /** create n enum values of given type */ + def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList + + /** create enum values of given type and names */ + def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap + + /** create enum values of given type and names */ + def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap +} diff --git a/src/main/scala/chisel/util/LFSR.scala b/src/main/scala/chisel/util/LFSR.scala new file mode 100644 index 00000000..1befb8ca --- /dev/null +++ b/src/main/scala/chisel/util/LFSR.scala @@ -0,0 +1,22 @@ +// See LICENSE for license details. + +/** LFSRs in all shapes and sizes. + */ + +package chisel + +// scalastyle:off magic.number +/** linear feedback shift register + */ +object LFSR16 +{ + def apply(increment: Bool = Bool(true)): UInt = + { + val width = 16 + val lfsr = Reg(init=UInt(1, width)) + when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } + lfsr + } +} +// scalastyle:on magic.number + diff --git a/src/main/scala/chisel/util/Lookup.scala b/src/main/scala/chisel/util/Lookup.scala new file mode 100644 index 00000000..1fdfd6ae --- /dev/null +++ b/src/main/scala/chisel/util/Lookup.scala @@ -0,0 +1,17 @@ +// See LICENSE for license details. + +package chisel + +object ListLookup { + def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = { + val map = mapping.map(m => (m._1 === addr, m._2)) + default.zipWithIndex map { case (d, i) => + map.foldRight(d)((m, n) => Mux(m._1, m._2(i), n)) + } + } +} + +object Lookup { + def apply[T <: Bits](addr: UInt, default: T, mapping: Seq[(BitPat, T)]): T = + ListLookup(addr, List(default), mapping.map(m => (m._1, List(m._2))).toArray).head +} diff --git a/src/main/scala/chisel/util/Math.scala b/src/main/scala/chisel/util/Math.scala new file mode 100644 index 00000000..1bf667ce --- /dev/null +++ b/src/main/scala/chisel/util/Math.scala @@ -0,0 +1,42 @@ +// See LICENSE for license details. + +/** Scala-land math helper functions, like logs. + */ + +package chisel + +/** Compute the log2 rounded up with min value of 1 */ +object log2Up { + def apply(in: BigInt): Int = { + require(in >= 0) + 1 max (in-1).bitLength + } + def apply(in: Int): Int = apply(BigInt(in)) +} + +/** Compute the log2 rounded up */ +object log2Ceil { + def apply(in: BigInt): Int = { + require(in > 0) + (in-1).bitLength + } + def apply(in: Int): Int = apply(BigInt(in)) +} + +/** Compute the log2 rounded down with min value of 1 */ +object log2Down { + def apply(in: BigInt): Int = log2Up(in) - (if (isPow2(in)) 0 else 1) + def apply(in: Int): Int = apply(BigInt(in)) +} + +/** Compute the log2 rounded down */ +object log2Floor { + def apply(in: BigInt): Int = log2Ceil(in) - (if (isPow2(in)) 0 else 1) + def apply(in: Int): Int = apply(BigInt(in)) +} + +/** Check if an Integer is a power of 2 */ +object isPow2 { + def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0) + def apply(in: Int): Boolean = apply(BigInt(in)) +} diff --git a/src/main/scala/chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala new file mode 100644 index 00000000..97467240 --- /dev/null +++ b/src/main/scala/chisel/util/Mux.scala @@ -0,0 +1,61 @@ +// See LICENSE for license details. + +/** Mux circuit generators. + */ + +package chisel + +/** Builds a Mux tree out of the input signal vector using a one hot encoded + select signal. Returns the output of the Mux tree. + */ +object Mux1H +{ + def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = + apply(sel zip in) + def apply[T <: Data](in: Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in) + def apply[T <: Data](sel: UInt, in: Seq[T]): T = + apply((0 until in.size).map(sel(_)), in) + def apply(sel: UInt, in: UInt): Bool = (sel & in).orR +} + +/** Builds a Mux tree under the assumption that multiple select signals + can be enabled. Priority is given to the first select signal. + + Returns the output of the Mux tree. + */ +object PriorityMux +{ + def apply[T <: Data](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in) + def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in) + def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in) +} + +/** MuxLookup creates a cascade of n Muxs to search for a key value */ +object MuxLookup { + /** @param key a key to search for + * @param default a default value if nothing is found + * @param mapping a sequence to search of keys and values + * @return the value found or the default if not + */ + def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = { + var res = default + for ((k, v) <- mapping.reverse) + res = Mux(k === key, v, res) + res + } + +} + +/** MuxCase returns the first value that is enabled in a map of values */ +object MuxCase { + /** @param default the default value if none are enabled + * @param mapping a set of data values with associated enables + * @return the first value in mapping that is enabled */ + def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = { + var res = default + for ((t, v) <- mapping.reverse){ + res = Mux(t, v, res) + } + res + } +} diff --git a/src/main/scala/chisel/util/OneHot.scala b/src/main/scala/chisel/util/OneHot.scala new file mode 100644 index 00000000..5d1de1a7 --- /dev/null +++ b/src/main/scala/chisel/util/OneHot.scala @@ -0,0 +1,62 @@ +// See LICENSE for license details. + +/** Circuit generators for working with one-hot representations. + */ + +package chisel + +/** Converts from One Hot Encoding to a UInt indicating which bit is active + * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/ +object OHToUInt { + def apply(in: Seq[Bool]): UInt = apply(Vec(in)) + def apply(in: Vec[Bool]): UInt = apply(in.toBits, in.size) + def apply(in: Bits): UInt = apply(in, in.getWidth) + + def apply(in: Bits, width: Int): UInt = { + if (width <= 2) { + Log2(in, width) + } else { + val mid = 1 << (log2Up(width)-1) + val hi = in(width-1, mid) + val lo = in(mid-1, 0) + Cat(hi.orR, apply(hi | lo, mid)) + } + } +} + +/** @return the bit position of the trailing 1 in the input vector + * with the assumption that multiple bits of the input bit vector can be set + * @example {{{ data_out := PriorityEncoder(data_in) }}} + */ +object PriorityEncoder { + def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_))) + def apply(in: Bits): UInt = apply(in.toBools) +} + +/** Returns the one hot encoding of the input UInt. + */ +object UIntToOH +{ + def apply(in: UInt, width: Int = -1): UInt = + if (width == -1) { + UInt(1) << in + } else { + (UInt(1) << in(log2Up(width)-1,0))(width-1,0) + } +} + +/** Returns a bit vector in which only the least-significant 1 bit in + the input vector, if any, is set. + */ +object PriorityEncoderOH +{ + private def encode(in: Seq[Bool]): UInt = { + val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size)) + PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size)) + } + def apply(in: Seq[Bool]): Seq[Bool] = { + val enc = encode(in) + Seq.tabulate(in.size)(enc(_)) + } + def apply(in: Bits): UInt = encode((0 until in.getWidth).map(i => in(i))) +} diff --git a/src/main/scala/chisel/util/Reg.scala b/src/main/scala/chisel/util/Reg.scala new file mode 100644 index 00000000..1808af76 --- /dev/null +++ b/src/main/scala/chisel/util/Reg.scala @@ -0,0 +1,55 @@ +// See LICENSE for license details. + +/** Variations and helpers for registers. + */ + +package chisel + +object RegNext { + + def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T]) + + def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init) + +} + +object RegInit { + + def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init) + +} + +/** A register with an Enable signal */ +object RegEnable +{ + def apply[T <: Data](updateData: T, enable: Bool): T = { + val r = Reg(updateData) + when (enable) { r := updateData } + r + } + def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = { + val r = RegInit(resetData) + when (enable) { r := updateData } + r + } +} + +/** Returns the n-cycle delayed version of the input signal. + */ +object ShiftRegister +{ + /** @param in input to delay + * @param n number of cycles to delay + * @param en enable the shift */ + def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = + { + // The order of tests reflects the expected use cases. + if (n == 1) { + RegEnable(in, en) + } else if (n != 0) { + RegNext(apply(in, n-1, en)) + } else { + in + } + } +} diff --git a/src/main/scala/chisel/util/TransitName.scala b/src/main/scala/chisel/util/TransitName.scala new file mode 100644 index 00000000..141b10bc --- /dev/null +++ b/src/main/scala/chisel/util/TransitName.scala @@ -0,0 +1,21 @@ +package chisel + +import internal.HasId + +object TransitName { + // The purpose of this is to allow a library to 'move' a name call to a more + // appropriate place. + // For example, a library factory function may create a module and return + // the io. The only user-exposed field is that given IO, which can't use + // any name supplied by the user. This can add a hook so that the supplied + // name then names the Module. + // See Queue companion object for working example + def apply[T<:HasId](from: T, to: HasId): T = { + from.addPostnameHook((given_name: String) => {to.suggestName(given_name)}) + from + } + def withSuffix[T<:HasId](suffix: String)(from: T, to: HasId): T = { + from.addPostnameHook((given_name: String) => {to.suggestName(given_name+suffix)}) + from + } +} diff --git a/src/main/scala/chisel/util/Valid.scala b/src/main/scala/chisel/util/Valid.scala new file mode 100644 index 00000000..cffed0a7 --- /dev/null +++ b/src/main/scala/chisel/util/Valid.scala @@ -0,0 +1,59 @@ +// See LICENSE for license details. + +/** Wrappers for valid interfaces and associated circuit generators using them. + */ + +package chisel + +/** An I/O Bundle containing data and a signal determining if it is valid */ +class ValidIO[+T <: Data](gen2: T) extends Bundle +{ + val valid = Bool(OUTPUT) + val bits = gen2.cloneType.asOutput + def fire(dummy: Int = 0): Bool = valid + override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type] +} + +/** Adds a valid protocol to any interface. The standard used is + that the consumer uses the flipped interface. +*/ +object Valid { + def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen) +} + +/** A hardware module that delays data coming down the pipeline + by the number of cycles set by the latency parameter. Functionality + is similar to ShiftRegister but this exposes a Pipe interface. + + Example usage: + val pipe = new Pipe(UInt()) + pipe.io.enq <> produce.io.out + consumer.io.in <> pipe.io.deq + */ +object Pipe +{ + def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = { + if (latency == 0) { + val out = Wire(Valid(enqBits)) + out.valid <> enqValid + out.bits <> enqBits + out + } else { + val v = Reg(Bool(), next=enqValid, init=Bool(false)) + val b = RegEnable(enqBits, enqValid) + apply(v, b, latency-1) + } + } + def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1) + def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency) +} + +class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module +{ + val io = new Bundle { + val enq = Valid(gen).flip + val deq = Valid(gen) + } + + io.deq <> Pipe(io.enq, latency) +} -- cgit v1.2.3 From 65df106578e12e8bd71f9775e0435bbe107ee4da Mon Sep 17 00:00:00 2001 From: ducky Date: Fri, 20 May 2016 18:25:22 -0700 Subject: Rename Chisel -> chisel in tests --- src/test/scala/chiselTests/Assert.scala | 4 ++-- src/test/scala/chiselTests/BitwiseOps.scala | 4 ++-- src/test/scala/chiselTests/BlackBox.scala | 4 ++-- src/test/scala/chiselTests/BundleWire.scala | 4 ++-- src/test/scala/chiselTests/ChiselSpec.scala | 4 ++-- src/test/scala/chiselTests/ComplexAssign.scala | 4 ++-- src/test/scala/chiselTests/Counter.scala | 4 ++-- src/test/scala/chiselTests/Decoder.scala | 4 ++-- src/test/scala/chiselTests/DeqIOSpec.scala | 4 ++-- src/test/scala/chiselTests/Direction.scala | 4 ++-- src/test/scala/chiselTests/EnableShiftRegister.scala | 4 ++-- src/test/scala/chiselTests/GCD.scala | 4 ++-- src/test/scala/chiselTests/Harness.scala | 5 +++-- src/test/scala/chiselTests/LFSR16.scala | 5 +++-- src/test/scala/chiselTests/MemorySearch.scala | 5 +++-- src/test/scala/chiselTests/Module.scala | 3 ++- src/test/scala/chiselTests/MulLookup.scala | 4 ++-- src/test/scala/chiselTests/MultiAssign.scala | 4 ++-- src/test/scala/chiselTests/OptionBundle.scala | 4 ++-- src/test/scala/chiselTests/Padding.scala | 3 ++- src/test/scala/chiselTests/ParameterizedModule.scala | 4 ++-- src/test/scala/chiselTests/Printf.scala | 4 ++-- src/test/scala/chiselTests/Reg.scala | 4 ++-- src/test/scala/chiselTests/Risc.scala | 3 ++- src/test/scala/chiselTests/SIntOps.scala | 5 +++-- src/test/scala/chiselTests/Stack.scala | 3 ++- src/test/scala/chiselTests/Stop.scala | 4 ++-- src/test/scala/chiselTests/Tbl.scala | 4 ++-- src/test/scala/chiselTests/TesterDriverSpec.scala | 4 ++-- src/test/scala/chiselTests/UIntOps.scala | 5 +++-- src/test/scala/chiselTests/Vec.scala | 4 ++-- src/test/scala/chiselTests/VectorPacketIO.scala | 4 ++-- src/test/scala/chiselTests/VendingMachine.scala | 3 ++- src/test/scala/chiselTests/When.scala | 4 ++-- 34 files changed, 73 insertions(+), 63 deletions(-) (limited to 'src') diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index 24eb8b55..eccf98e1 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class FailingAssertTester() extends BasicTester { assert(Bool(false)) diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala index 19aa956c..0c1d4d74 100644 --- a/src/test/scala/chiselTests/BitwiseOps.scala +++ b/src/test/scala/chiselTests/BitwiseOps.scala @@ -2,10 +2,10 @@ package chiselTests -import Chisel._ +import chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester { val mask = (1 << w) - 1 diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index ca94087c..962a9db1 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -4,8 +4,8 @@ package chiselTests import java.io.File import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class BlackBoxInverter extends BlackBox { val io = new Bundle() { diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index d2e42fa9..36dbb365 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -1,10 +1,10 @@ // See LICENSE for license details. package chiselTests -import Chisel._ +import chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class Coord extends Bundle { val x = UInt(width = 32) diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index da68b0cb..9c66b0db 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -6,8 +6,8 @@ import java.io.File import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ -import Chisel._ -import Chisel.testers._ +import chisel._ +import chisel.testers._ /** Common utility functions for Chisel unit tests. */ trait ChiselRunners extends Assertions { diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index d79a2625..8f79f76d 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -1,11 +1,11 @@ // See LICENSE for license details. package chiselTests -import Chisel._ +import chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class Complex[T <: Data](val re: T, val im: T) extends Bundle { override def cloneType: this.type = diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala index 07a76cdc..cbc80b86 100644 --- a/src/test/scala/chiselTests/Counter.scala +++ b/src/test/scala/chiselTests/Counter.scala @@ -1,10 +1,10 @@ // See LICENSE for license details. package chiselTests -import Chisel._ +import chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class CountTester(max: Int) extends BasicTester { val cnt = Counter(max) diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index e5cdfd07..1e6e7648 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -1,11 +1,11 @@ // See LICENSE for license details. package chiselTests -import Chisel._ +import chisel._ import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class Decoder(bitpats: List[String]) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala index 8f7937ab..9fd47ab0 100644 --- a/src/test/scala/chiselTests/DeqIOSpec.scala +++ b/src/test/scala/chiselTests/DeqIOSpec.scala @@ -2,8 +2,8 @@ package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester /** * Created by chick on 2/8/16. diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index dd2f6572..3ed543aa 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -2,10 +2,10 @@ package chiselTests -import Chisel._ +import chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class DirectionHaver extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 6600df2a..30fc2486 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class EnableShiftRegister extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala index a1bfffda..77452db6 100644 --- a/src/test/scala/chiselTests/GCD.scala +++ b/src/test/scala/chiselTests/GCD.scala @@ -2,8 +2,8 @@ package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester import org.scalatest._ import org.scalatest.prop._ diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala index bc838766..805e2de9 100644 --- a/src/test/scala/chiselTests/Harness.scala +++ b/src/test/scala/chiselTests/Harness.scala @@ -1,13 +1,14 @@ // See LICENSE for license details. package chiselTests -import Chisel.testers.BasicTester + +import chisel.testers.BasicTester import org.scalatest._ import org.scalatest.prop._ import java.io.File class HarnessSpec extends ChiselPropSpec - with Chisel.BackendCompilationUtilities { + with chisel.BackendCompilationUtilities { def makeTrivialVerilog: (File => File) = makeHarness((prefix: String) => s""" module ${prefix}; diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index ed76a296..42024a3f 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -1,8 +1,9 @@ // See LICENSE for license details. package chiselTests -import Chisel._ -import Chisel.testers.BasicTester + +import chisel._ +import chisel.testers.BasicTester class LFSR16 extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index 55b704a0..b48d2881 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -1,8 +1,9 @@ // See LICENSE for license details. package chiselTests -import Chisel._ -import Chisel.testers.BasicTester + +import chisel._ +import chisel.testers.BasicTester class MemorySearch extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 88ba795b..64b00fab 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -1,7 +1,8 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel._ class SimpleIO extends Bundle { val in = UInt(INPUT, 32) diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala index 49ba13c7..5e223f91 100644 --- a/src/test/scala/chiselTests/MulLookup.scala +++ b/src/test/scala/chiselTests/MulLookup.scala @@ -2,10 +2,10 @@ package chiselTests -import Chisel._ +import chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class MulLookup(val w: Int) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 2f464123..ff3bc7a5 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class LastAssignTester() extends BasicTester { val cnt = Counter(2) diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala index c5a347e6..ab3b6860 100644 --- a/src/test/scala/chiselTests/OptionBundle.scala +++ b/src/test/scala/chiselTests/OptionBundle.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class OptionBundle(hasIn: Boolean) extends Bundle { val in = if (hasIn) { diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala index 999b7d36..03496649 100644 --- a/src/test/scala/chiselTests/Padding.scala +++ b/src/test/scala/chiselTests/Padding.scala @@ -1,7 +1,8 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel._ class Padder extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala index 35e3ba78..e2629224 100644 --- a/src/test/scala/chiselTests/ParameterizedModule.scala +++ b/src/test/scala/chiselTests/ParameterizedModule.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class ParameterizedModule(invert: Boolean) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala index eb8b4b25..b5e1e66e 100644 --- a/src/test/scala/chiselTests/Printf.scala +++ b/src/test/scala/chiselTests/Printf.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class SinglePrintfTester() extends BasicTester { val x = UInt(254) diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index f2620d88..8954c3ef 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class RegSpec extends ChiselFlatSpec { "A Reg" should "throw an exception if not given any parameters" in { diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 3daa5bd2..6b0742ae 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -1,7 +1,8 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel._ class Risc extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index 0835fb4d..07111af6 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -1,8 +1,9 @@ // See LICENSE for license details. package chiselTests -import Chisel._ -import Chisel.testers.BasicTester + +import chisel._ +import chisel.testers.BasicTester class SIntOps extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index ac799c8a..53c57b5b 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -1,8 +1,9 @@ // See LICENSE for license details. package chiselTests + import scala.collection.mutable.Stack -import Chisel._ +import chisel._ class ChiselStack(val depth: Int) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala index 878f090c..d57eb7c6 100644 --- a/src/test/scala/chiselTests/Stop.scala +++ b/src/test/scala/chiselTests/Stop.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class StopTester() extends BasicTester { stop() diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index c79eb8a4..918f9158 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -2,10 +2,10 @@ package chiselTests -import Chisel._ +import chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class Tbl(w: Int, n: Int) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index 3c57daae..e6b5bc1f 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -2,8 +2,8 @@ package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester /** Extend BasicTester with a simple circuit and finish method. TesterDriver will call the * finish method after the FinishTester's constructor has completed, which will alter the diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala index bb0b0f06..8b2a31fd 100644 --- a/src/test/scala/chiselTests/UIntOps.scala +++ b/src/test/scala/chiselTests/UIntOps.scala @@ -1,9 +1,10 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel._ import org.scalatest._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class UIntOps extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 943d9e4b..e35c765e 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -2,10 +2,10 @@ package chiselTests -import Chisel._ +import chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester +import chisel.testers.BasicTester class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala index 99ec66a6..26e87360 100644 --- a/src/test/scala/chiselTests/VectorPacketIO.scala +++ b/src/test/scala/chiselTests/VectorPacketIO.scala @@ -2,8 +2,8 @@ package chiselTests -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester /** * This test used to fail when assignment statements were diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala index 012fc493..e11e48dd 100644 --- a/src/test/scala/chiselTests/VendingMachine.scala +++ b/src/test/scala/chiselTests/VendingMachine.scala @@ -1,7 +1,8 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel._ class VendingMachine extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index a6572706..a1bd7c31 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel._ +import chisel.testers.BasicTester class WhenTester() extends BasicTester { val cnt = Counter(4) -- cgit v1.2.3 From 671117f3332ac10d1e7c5cc4f4cb5278f72ed6ab Mon Sep 17 00:00:00 2001 From: ducky Date: Fri, 20 May 2016 19:50:05 -0700 Subject: Add implicit xToLiteral, add Element, use internal package object --- src/main/scala/chisel/compatibility.scala | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala index 80936a42..fd45987b 100644 --- a/src/main/scala/chisel/compatibility.scala +++ b/src/main/scala/chisel/compatibility.scala @@ -26,6 +26,7 @@ package object Chisel { val BitPat = chisel.BitPat type BitPat = chisel.BitPat + type Element = chisel.Element type Bits = chisel.Bits val Bits = chisel.Bits type Num[T <: Data] = chisel.Num[T] @@ -64,6 +65,12 @@ package object Chisel { val throwException = chisel.throwException + object testers { + type BasicTester = chisel.testers.BasicTester + val TesterDriver = chisel.testers.TesterDriver + } + + val log2Up = chisel.log2Up val log2Ceil = chisel.log2Ceil val log2Down = chisel.log2Down @@ -129,11 +136,15 @@ package object Chisel { val Valid = chisel.Valid val Pipe = chisel.Pipe type Pipe[T <: Data] = chisel.Pipe[T] -} -package Chisel { - package object testers { - type BasicTester = chisel.testers.BasicTester - val TesterDriver = chisel.testers.TesterDriver - } + + import chisel.internal.firrtl.Width + implicit def fromBigIntToLiteral(x: BigInt): chisel.fromBigIntToLiteral = + new chisel.fromBigIntToLiteral(x) + implicit def fromIntToLiteral(x: Int): chisel.fromIntToLiteral= + new chisel.fromIntToLiteral(x) + implicit def fromStringToLiteral(x: String): chisel.fromStringToLiteral= + new chisel.fromStringToLiteral(x) + implicit def fromBooleanToLiteral(x: Boolean): chisel.fromBooleanToLiteral= + new chisel.fromBooleanToLiteral(x) } -- cgit v1.2.3 From 881ac3cb3a9da0c7827a161238468df4727996f0 Mon Sep 17 00:00:00 2001 From: ducky Date: Fri, 27 May 2016 13:24:36 -0700 Subject: Move utils into utils --- src/main/scala/chisel/compatibility.scala | 110 +++++++++++----------- src/main/scala/chisel/util/Arbiter.scala | 4 +- src/main/scala/chisel/util/Bitwise.scala | 4 +- src/main/scala/chisel/util/Cat.scala | 4 +- src/main/scala/chisel/util/CircuitMath.scala | 4 +- src/main/scala/chisel/util/Conditional.scala | 6 +- src/main/scala/chisel/util/Counter.scala | 4 +- src/main/scala/chisel/util/Decoupled.scala | 4 +- src/main/scala/chisel/util/Enum.scala | 4 +- src/main/scala/chisel/util/LFSR.scala | 4 +- src/main/scala/chisel/util/Lookup.scala | 4 +- src/main/scala/chisel/util/Math.scala | 4 +- src/main/scala/chisel/util/Mux.scala | 4 +- src/main/scala/chisel/util/OneHot.scala | 4 +- src/main/scala/chisel/util/Reg.scala | 4 +- src/main/scala/chisel/util/TransitName.scala | 3 +- src/main/scala/chisel/util/Valid.scala | 4 +- src/test/scala/chiselTests/Assert.scala | 1 + src/test/scala/chiselTests/BlackBox.scala | 2 + src/test/scala/chiselTests/ComplexAssign.scala | 4 +- src/test/scala/chiselTests/Counter.scala | 5 +- src/test/scala/chiselTests/Decoder.scala | 5 +- src/test/scala/chiselTests/DeqIOSpec.scala | 1 + src/test/scala/chiselTests/LFSR16.scala | 1 + src/test/scala/chiselTests/MultiAssign.scala | 2 + src/test/scala/chiselTests/Risc.scala | 1 + src/test/scala/chiselTests/Stack.scala | 2 + src/test/scala/chiselTests/Tbl.scala | 4 +- src/test/scala/chiselTests/TesterDriverSpec.scala | 1 + src/test/scala/chiselTests/Vec.scala | 4 +- src/test/scala/chiselTests/VectorPacketIO.scala | 1 + src/test/scala/chiselTests/VendingMachine.scala | 1 + src/test/scala/chiselTests/When.scala | 2 + 33 files changed, 135 insertions(+), 77 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala index fd45987b..9cdef80d 100644 --- a/src/main/scala/chisel/compatibility.scala +++ b/src/main/scala/chisel/compatibility.scala @@ -71,80 +71,80 @@ package object Chisel { } - val log2Up = chisel.log2Up - val log2Ceil = chisel.log2Ceil - val log2Down = chisel.log2Down - val log2Floor = chisel.log2Floor - val isPow2 = chisel.isPow2 + val log2Up = chisel.util.log2Up + val log2Ceil = chisel.util.log2Ceil + val log2Down = chisel.util.log2Down + val log2Floor = chisel.util.log2Floor + val isPow2 = chisel.util.isPow2 - type ArbiterIO[T <: Data] = chisel.ArbiterIO[T] - type LockingArbiterLike[T <: Data] = chisel.LockingArbiterLike[T] - type LockingRRArbiter[T <: Data] = chisel.LockingRRArbiter[T] - type LockingArbiter[T <: Data] = chisel.LockingArbiter[T] - type RRArbiter[T <: Data] = chisel.RRArbiter[T] - type Arbiter[T <: Data] = chisel.Arbiter[T] + type ArbiterIO[T <: Data] = chisel.util.ArbiterIO[T] + type LockingArbiterLike[T <: Data] = chisel.util.LockingArbiterLike[T] + type LockingRRArbiter[T <: Data] = chisel.util.LockingRRArbiter[T] + type LockingArbiter[T <: Data] = chisel.util.LockingArbiter[T] + type RRArbiter[T <: Data] = chisel.util.RRArbiter[T] + type Arbiter[T <: Data] = chisel.util.Arbiter[T] - val FillInterleaved = chisel.FillInterleaved - val PopCount = chisel.PopCount - val Fill = chisel.Fill - val Reverse = chisel.Reverse + val FillInterleaved = chisel.util.FillInterleaved + val PopCount = chisel.util.PopCount + val Fill = chisel.util.Fill + val Reverse = chisel.util.Reverse - val Cat = chisel.Cat + val Cat = chisel.util.Cat - val Log2 = chisel.Log2 + val Log2 = chisel.util.Log2 - val unless = chisel.unless - type SwitchContext[T <: Bits] = chisel.SwitchContext[T] - val is = chisel.is - val switch = chisel.switch + val unless = chisel.util.unless + type SwitchContext[T <: Bits] = chisel.util.SwitchContext[T] + val is = chisel.util.is + val switch = chisel.util.switch - type Counter = chisel.Counter - val Counter = chisel.Counter + type Counter = chisel.util.Counter + val Counter = chisel.util.Counter - type DecoupledIO[+T <: Data] = chisel.DecoupledIO[T] - val Decoupled = chisel.Decoupled - type EnqIO[T <: Data] = chisel.EnqIO[T] - type DeqIO[T <: Data] = chisel.DeqIO[T] - type DecoupledIOC[+T <: Data] = chisel.DecoupledIOC[T] - type QueueIO[T <: Data] = chisel.QueueIO[T] - type Queue[T <: Data] = chisel.Queue[T] - val Queue = chisel.Queue + type DecoupledIO[+T <: Data] = chisel.util.DecoupledIO[T] + val Decoupled = chisel.util.Decoupled + type EnqIO[T <: Data] = chisel.util.EnqIO[T] + type DeqIO[T <: Data] = chisel.util.DeqIO[T] + type DecoupledIOC[+T <: Data] = chisel.util.DecoupledIOC[T] + type QueueIO[T <: Data] = chisel.util.QueueIO[T] + type Queue[T <: Data] = chisel.util.Queue[T] + val Queue = chisel.util.Queue - val Enum = chisel.Enum + val Enum = chisel.util.Enum - val LFSR16 = chisel.LFSR16 + val LFSR16 = chisel.util.LFSR16 - val ListLookup = chisel.ListLookup - val Lookup = chisel.Lookup + val ListLookup = chisel.util.ListLookup + val Lookup = chisel.util.Lookup - val Mux1H = chisel.Mux1H - val PriorityMux = chisel.PriorityMux - val MuxLookup = chisel.MuxLookup - val MuxCase = chisel.MuxCase + val Mux1H = chisel.util.Mux1H + val PriorityMux = chisel.util.PriorityMux + val MuxLookup = chisel.util.MuxLookup + val MuxCase = chisel.util.MuxCase - val OHToUInt = chisel.OHToUInt - val PriorityEncoder = chisel.PriorityEncoder - val UIntToOH = chisel.UIntToOH - val PriorityEncoderOH = chisel.PriorityEncoderOH + val OHToUInt = chisel.util.OHToUInt + val PriorityEncoder = chisel.util.PriorityEncoder + val UIntToOH = chisel.util.UIntToOH + val PriorityEncoderOH = chisel.util.PriorityEncoderOH - val RegNext = chisel.RegNext - val RegInit = chisel.RegInit - val RegEnable = chisel.RegEnable - val ShiftRegister = chisel.ShiftRegister + val RegNext = chisel.util.RegNext + val RegInit = chisel.util.RegInit + val RegEnable = chisel.util.RegEnable + val ShiftRegister = chisel.util.ShiftRegister - type ValidIO[+T <: Data] = chisel.ValidIO[T] - val Valid = chisel.Valid - val Pipe = chisel.Pipe - type Pipe[T <: Data] = chisel.Pipe[T] + type ValidIO[+T <: Data] = chisel.util.ValidIO[T] + val Valid = chisel.util.Valid + val Pipe = chisel.util.Pipe + type Pipe[T <: Data] = chisel.util.Pipe[T] import chisel.internal.firrtl.Width - implicit def fromBigIntToLiteral(x: BigInt): chisel.fromBigIntToLiteral = + implicit def fromBigIntToLiteral(x: BigInt): chisel.fromBigIntToLiteral = new chisel.fromBigIntToLiteral(x) - implicit def fromIntToLiteral(x: Int): chisel.fromIntToLiteral= + implicit def fromIntToLiteral(x: Int): chisel.fromIntToLiteral= new chisel.fromIntToLiteral(x) - implicit def fromStringToLiteral(x: String): chisel.fromStringToLiteral= + implicit def fromStringToLiteral(x: String): chisel.fromStringToLiteral= new chisel.fromStringToLiteral(x) - implicit def fromBooleanToLiteral(x: Boolean): chisel.fromBooleanToLiteral= + implicit def fromBooleanToLiteral(x: Boolean): chisel.fromBooleanToLiteral= new chisel.fromBooleanToLiteral(x) } diff --git a/src/main/scala/chisel/util/Arbiter.scala b/src/main/scala/chisel/util/Arbiter.scala index afe48963..3723f2a9 100644 --- a/src/main/scala/chisel/util/Arbiter.scala +++ b/src/main/scala/chisel/util/Arbiter.scala @@ -3,7 +3,9 @@ /** Arbiters in all shapes and sizes. */ -package chisel +package chisel.util + +import chisel._ /** An I/O bundle for the Arbiter */ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala index 27064059..94413fc7 100644 --- a/src/main/scala/chisel/util/Bitwise.scala +++ b/src/main/scala/chisel/util/Bitwise.scala @@ -3,7 +3,9 @@ /** Miscellaneous circuit generators operating on bits. */ -package chisel +package chisel.util + +import chisel._ object FillInterleaved { diff --git a/src/main/scala/chisel/util/Cat.scala b/src/main/scala/chisel/util/Cat.scala index a35619df..5b3c613e 100644 --- a/src/main/scala/chisel/util/Cat.scala +++ b/src/main/scala/chisel/util/Cat.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. -package chisel +package chisel.util + +import chisel._ object Cat { /** Combine data elements together diff --git a/src/main/scala/chisel/util/CircuitMath.scala b/src/main/scala/chisel/util/CircuitMath.scala index 001be802..c3b94fdb 100644 --- a/src/main/scala/chisel/util/CircuitMath.scala +++ b/src/main/scala/chisel/util/CircuitMath.scala @@ -3,7 +3,9 @@ /** Circuit-land math operations. */ -package chisel +package chisel.util + +import chisel._ /** Compute Log2 with truncation of a UInt in hardware using a Mux Tree * An alternative interpretation is it computes the minimum number of bits needed to represent x diff --git a/src/main/scala/chisel/util/Conditional.scala b/src/main/scala/chisel/util/Conditional.scala index 94f00080..01c12799 100644 --- a/src/main/scala/chisel/util/Conditional.scala +++ b/src/main/scala/chisel/util/Conditional.scala @@ -3,13 +3,15 @@ /** Conditional blocks. */ -package chisel +package chisel.util import scala.language.reflectiveCalls import scala.language.experimental.macros import scala.reflect.runtime.universe._ import scala.reflect.macros.blackbox._ +import chisel._ + /** This is identical to [[Chisel.when when]] with the condition inverted */ object unless { // scalastyle:ignore object.name def apply(c: Bool)(block: => Unit) { @@ -61,7 +63,7 @@ object switch { // scalastyle:ignore object.name def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match { // TODO: remove when Chisel compatibility package is removed case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") - case q"chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") + case q"chisel.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.") } val q"..$body" = x diff --git a/src/main/scala/chisel/util/Counter.scala b/src/main/scala/chisel/util/Counter.scala index dde1e347..1c0b0203 100644 --- a/src/main/scala/chisel/util/Counter.scala +++ b/src/main/scala/chisel/util/Counter.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. -package chisel +package chisel.util + +import chisel._ /** A counter module * @param n number of counts before the counter resets (or one more than the diff --git a/src/main/scala/chisel/util/Decoupled.scala b/src/main/scala/chisel/util/Decoupled.scala index 955b0870..89b0e39d 100644 --- a/src/main/scala/chisel/util/Decoupled.scala +++ b/src/main/scala/chisel/util/Decoupled.scala @@ -3,7 +3,9 @@ /** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them. */ -package chisel +package chisel.util + +import chisel._ /** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/ class DecoupledIO[+T <: Data](gen: T) extends Bundle diff --git a/src/main/scala/chisel/util/Enum.scala b/src/main/scala/chisel/util/Enum.scala index 2757a06c..8babcd23 100644 --- a/src/main/scala/chisel/util/Enum.scala +++ b/src/main/scala/chisel/util/Enum.scala @@ -3,7 +3,9 @@ /** Enum generators, allowing circuit constants to have more meaningful names. */ -package chisel +package chisel.util + +import chisel._ object Enum { /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */ diff --git a/src/main/scala/chisel/util/LFSR.scala b/src/main/scala/chisel/util/LFSR.scala index 1befb8ca..f70630bf 100644 --- a/src/main/scala/chisel/util/LFSR.scala +++ b/src/main/scala/chisel/util/LFSR.scala @@ -3,7 +3,9 @@ /** LFSRs in all shapes and sizes. */ -package chisel +package chisel.util + +import chisel._ // scalastyle:off magic.number /** linear feedback shift register diff --git a/src/main/scala/chisel/util/Lookup.scala b/src/main/scala/chisel/util/Lookup.scala index 1fdfd6ae..d32d9aec 100644 --- a/src/main/scala/chisel/util/Lookup.scala +++ b/src/main/scala/chisel/util/Lookup.scala @@ -1,6 +1,8 @@ // See LICENSE for license details. -package chisel +package chisel.util + +import chisel._ object ListLookup { def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = { diff --git a/src/main/scala/chisel/util/Math.scala b/src/main/scala/chisel/util/Math.scala index 1bf667ce..69464d15 100644 --- a/src/main/scala/chisel/util/Math.scala +++ b/src/main/scala/chisel/util/Math.scala @@ -3,7 +3,9 @@ /** Scala-land math helper functions, like logs. */ -package chisel +package chisel.util + +import chisel._ /** Compute the log2 rounded up with min value of 1 */ object log2Up { diff --git a/src/main/scala/chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala index 97467240..cfff4485 100644 --- a/src/main/scala/chisel/util/Mux.scala +++ b/src/main/scala/chisel/util/Mux.scala @@ -3,7 +3,9 @@ /** Mux circuit generators. */ -package chisel +package chisel.util + +import chisel._ /** Builds a Mux tree out of the input signal vector using a one hot encoded select signal. Returns the output of the Mux tree. diff --git a/src/main/scala/chisel/util/OneHot.scala b/src/main/scala/chisel/util/OneHot.scala index 5d1de1a7..ef21c65d 100644 --- a/src/main/scala/chisel/util/OneHot.scala +++ b/src/main/scala/chisel/util/OneHot.scala @@ -3,7 +3,9 @@ /** Circuit generators for working with one-hot representations. */ -package chisel +package chisel.util + +import chisel._ /** Converts from One Hot Encoding to a UInt indicating which bit is active * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/ diff --git a/src/main/scala/chisel/util/Reg.scala b/src/main/scala/chisel/util/Reg.scala index 1808af76..1b40646d 100644 --- a/src/main/scala/chisel/util/Reg.scala +++ b/src/main/scala/chisel/util/Reg.scala @@ -3,7 +3,9 @@ /** Variations and helpers for registers. */ -package chisel +package chisel.util + +import chisel._ object RegNext { diff --git a/src/main/scala/chisel/util/TransitName.scala b/src/main/scala/chisel/util/TransitName.scala index 141b10bc..04e1995b 100644 --- a/src/main/scala/chisel/util/TransitName.scala +++ b/src/main/scala/chisel/util/TransitName.scala @@ -1,5 +1,6 @@ -package chisel +package chisel.util +import chisel._ import internal.HasId object TransitName { diff --git a/src/main/scala/chisel/util/Valid.scala b/src/main/scala/chisel/util/Valid.scala index cffed0a7..56ac9abb 100644 --- a/src/main/scala/chisel/util/Valid.scala +++ b/src/main/scala/chisel/util/Valid.scala @@ -3,7 +3,9 @@ /** Wrappers for valid interfaces and associated circuit generators using them. */ -package chisel +package chisel.util + +import chisel._ /** An I/O Bundle containing data and a signal determining if it is valid */ class ValidIO[+T <: Data](gen2: T) extends Bundle diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index eccf98e1..eb8617b2 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -5,6 +5,7 @@ package chiselTests import org.scalatest._ import chisel._ import chisel.testers.BasicTester +import chisel.util._ class FailingAssertTester() extends BasicTester { assert(Bool(false)) diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index 962a9db1..b77550c1 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -4,8 +4,10 @@ package chiselTests import java.io.File import org.scalatest._ + import chisel._ import chisel.testers.BasicTester +import chisel.util._ class BlackBoxInverter extends BlackBox { val io = new Bundle() { diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index 8f79f76d..53a6a67d 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -1,11 +1,13 @@ // See LICENSE for license details. package chiselTests -import chisel._ + import org.scalatest._ import org.scalatest.prop._ +import chisel._ import chisel.testers.BasicTester +import chisel.util._ class Complex[T <: Data](val re: T, val im: T) extends Bundle { override def cloneType: this.type = diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala index cbc80b86..963c1c92 100644 --- a/src/test/scala/chiselTests/Counter.scala +++ b/src/test/scala/chiselTests/Counter.scala @@ -1,10 +1,13 @@ // See LICENSE for license details. package chiselTests -import chisel._ + import org.scalatest._ import org.scalatest.prop._ + +import chisel._ import chisel.testers.BasicTester +import chisel.util._ class CountTester(max: Int) extends BasicTester { val cnt = Counter(max) diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index 1e6e7648..33980955 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -1,11 +1,14 @@ // See LICENSE for license details. package chiselTests -import chisel._ + import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ + +import chisel._ import chisel.testers.BasicTester +import chisel.util._ class Decoder(bitpats: List[String]) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala index 9fd47ab0..95160140 100644 --- a/src/test/scala/chiselTests/DeqIOSpec.scala +++ b/src/test/scala/chiselTests/DeqIOSpec.scala @@ -4,6 +4,7 @@ package chiselTests import chisel._ import chisel.testers.BasicTester +import chisel.util._ /** * Created by chick on 2/8/16. diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index 42024a3f..b3e69884 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -4,6 +4,7 @@ package chiselTests import chisel._ import chisel.testers.BasicTester +import chisel.util._ class LFSR16 extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index ff3bc7a5..152e6723 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -3,8 +3,10 @@ package chiselTests import org.scalatest._ + import chisel._ import chisel.testers.BasicTester +import chisel.util._ class LastAssignTester() extends BasicTester { val cnt = Counter(2) diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 6b0742ae..741e9896 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -3,6 +3,7 @@ package chiselTests import chisel._ +import chisel.util._ class Risc extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 53c57b5b..0ce228de 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -3,7 +3,9 @@ package chiselTests import scala.collection.mutable.Stack + import chisel._ +import chisel.util._ class ChiselStack(val depth: Int) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 918f9158..2049d8bb 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -2,10 +2,12 @@ package chiselTests -import chisel._ import org.scalatest._ import org.scalatest.prop._ + +import chisel._ import chisel.testers.BasicTester +import chisel.util._ class Tbl(w: Int, n: Int) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index e6b5bc1f..50290fab 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -4,6 +4,7 @@ package chiselTests import chisel._ import chisel.testers.BasicTester +import chisel.util._ /** Extend BasicTester with a simple circuit and finish method. TesterDriver will call the * finish method after the FinishTester's constructor has completed, which will alter the diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index e35c765e..35a0c8bc 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -2,10 +2,12 @@ package chiselTests -import chisel._ import org.scalatest._ import org.scalatest.prop._ + +import chisel._ import chisel.testers.BasicTester +import chisel.util._ class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala index 26e87360..a1282071 100644 --- a/src/test/scala/chiselTests/VectorPacketIO.scala +++ b/src/test/scala/chiselTests/VectorPacketIO.scala @@ -4,6 +4,7 @@ package chiselTests import chisel._ import chisel.testers.BasicTester +import chisel.util._ /** * This test used to fail when assignment statements were diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala index e11e48dd..0d621e6a 100644 --- a/src/test/scala/chiselTests/VendingMachine.scala +++ b/src/test/scala/chiselTests/VendingMachine.scala @@ -3,6 +3,7 @@ package chiselTests import chisel._ +import chisel.util._ class VendingMachine extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index a1bd7c31..1c9c3bc5 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -3,8 +3,10 @@ package chiselTests import org.scalatest._ + import chisel._ import chisel.testers.BasicTester +import chisel.util._ class WhenTester() extends BasicTester { val cnt = Counter(4) -- cgit v1.2.3 From 66301b9042530a5265c18c97a0dab9022a0efc50 Mon Sep 17 00:00:00 2001 From: ducky Date: Wed, 1 Jun 2016 12:17:25 -0700 Subject: Move chisel/... to chisel/core/..., make chisel/compatibility package/folder, move more things into utils --- src/main/scala/Chisel/BitPat.scala | 88 --------------------- src/main/scala/chisel/FileSystemUtilities.scala | 10 --- src/main/scala/chisel/ImplicitConversions.scala | 8 -- src/main/scala/chisel/Main.scala | 17 ----- src/main/scala/chisel/compatibility.scala | 14 ++-- .../chisel/compatibility/FileSystemUtilities.scala | 12 +++ src/main/scala/chisel/compatibility/Main.scala | 19 +++++ .../chisel/compatibility/throwException.scala | 14 ++++ src/main/scala/chisel/package.scala | 1 + src/main/scala/chisel/throwException.scala | 12 --- src/main/scala/chisel/util/BitPat.scala | 89 ++++++++++++++++++++++ .../scala/chisel/util/ImplicitConversions.scala | 10 +++ 12 files changed, 152 insertions(+), 142 deletions(-) delete mode 100644 src/main/scala/Chisel/BitPat.scala delete mode 100644 src/main/scala/chisel/FileSystemUtilities.scala delete mode 100644 src/main/scala/chisel/ImplicitConversions.scala delete mode 100644 src/main/scala/chisel/Main.scala create mode 100644 src/main/scala/chisel/compatibility/FileSystemUtilities.scala create mode 100644 src/main/scala/chisel/compatibility/Main.scala create mode 100644 src/main/scala/chisel/compatibility/throwException.scala delete mode 100644 src/main/scala/chisel/throwException.scala create mode 100644 src/main/scala/chisel/util/BitPat.scala create mode 100644 src/main/scala/chisel/util/ImplicitConversions.scala (limited to 'src') diff --git a/src/main/scala/Chisel/BitPat.scala b/src/main/scala/Chisel/BitPat.scala deleted file mode 100644 index a6833ed2..00000000 --- a/src/main/scala/Chisel/BitPat.scala +++ /dev/null @@ -1,88 +0,0 @@ -// See LICENSE for license details. - -package chisel - -import scala.language.experimental.macros - -import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform} - -object BitPat { - /** Parses a bit pattern string into (bits, mask, width). - * - * @return bits the literal value, with don't cares being 0 - * @return mask the mask bits, with don't cares being 0 and cares being 1 - * @return width the number of bits in the literal, including values and - * don't cares. - */ - private def parse(x: String): (BigInt, BigInt, Int) = { - // Notes: - // While Verilog Xs also handle octal and hex cases, there isn't a - // compelling argument and no one has asked for it. - // If ? parsing is to be exposed, the return API needs further scrutiny - // (especially with things like mask polarity). - require(x.head == 'b', "BitPats must be in binary and be prefixed with 'b'") - var bits = BigInt(0) - var mask = BigInt(0) - for (d <- x.tail) { - if (d != '_') { - require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d) - mask = (mask << 1) + (if (d == '?') 0 else 1) - bits = (bits << 1) + (if (d == '1') 1 else 0) - } - } - (bits, mask, x.length - 1) - } - - /** Creates a [[BitPat]] literal from a string. - * - * @param n the literal value as a string, in binary, prefixed with 'b' - * @note legal characters are '0', '1', and '?', as well as '_' as white - * space (which are ignored) - */ - def apply(n: String): BitPat = { - val (bits, mask, width) = parse(n) - new BitPat(bits, mask, width) - } - - /** Creates a [[BitPat]] of all don't cares of the specified bitwidth. */ - def dontCare(width: Int): BitPat = BitPat("b" + ("?" * width)) - - @deprecated("Use BitPat.dontCare", "chisel3") - def DC(width: Int): BitPat = dontCare(width) // scalastyle:ignore method.name - - /** Allows BitPats to be used where a UInt is expected. - * - * @note the BitPat must not have don't care bits (will error out otherwise) - */ - def bitPatToUInt(x: BitPat): UInt = { - require(x.mask == (BigInt(1) << x.getWidth) - 1) - UInt(x.value, x.getWidth) - } - - /** Allows UInts to be used where a BitPat is expected, useful for when an - * interface is defined with BitPats but not all cases need the partial - * matching capability. - * - * @note the UInt must be a literal - */ - def apply(x: UInt): BitPat = { - require(x.isLit) - BitPat("b" + x.litValue.toString(2)) - } -} - -// TODO: Break out of Core? (this doesn't involve FIRRTL generation) -/** Bit patterns are literals with masks, used to represent values with don't - * cares. Equality comparisons will ignore don't care bits (for example, - * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)). - */ -sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) { - def getWidth: Int = width - def === (that: UInt): Bool = macro SourceInfoTransform.thatArg - def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg - def != (that: UInt): Bool = macro SourceInfoTransform.thatArg - - def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask)) - def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that) - def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that -} diff --git a/src/main/scala/chisel/FileSystemUtilities.scala b/src/main/scala/chisel/FileSystemUtilities.scala deleted file mode 100644 index f100eaf6..00000000 --- a/src/main/scala/chisel/FileSystemUtilities.scala +++ /dev/null @@ -1,10 +0,0 @@ -// See LICENSE for license details. - -package chisel - -@deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0") -trait FileSystemUtilities { - def createOutputFile(name: String): java.io.FileWriter = { - new java.io.FileWriter(Driver.targetDir + "/" + name) - } -} diff --git a/src/main/scala/chisel/ImplicitConversions.scala b/src/main/scala/chisel/ImplicitConversions.scala deleted file mode 100644 index f786d4f1..00000000 --- a/src/main/scala/chisel/ImplicitConversions.scala +++ /dev/null @@ -1,8 +0,0 @@ -// See LICENSE for license details. - -package chisel - -object ImplicitConversions { - implicit def intToUInt(x: Int): UInt = UInt(x) - implicit def booleanToBool(x: Boolean): Bool = Bool(x) -} diff --git a/src/main/scala/chisel/Main.scala b/src/main/scala/chisel/Main.scala deleted file mode 100644 index 79e5c9ca..00000000 --- a/src/main/scala/chisel/Main.scala +++ /dev/null @@ -1,17 +0,0 @@ -// See LICENSE for license details. - -package chisel - -import java.io.File - -@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain { - def apply[T <: Module](args: Array[String], gen: () => T): Unit = - Predef.assert(false, "No more chiselMain in Chisel3") - - def run[T <: Module] (args: Array[String], gen: () => T): Unit = { - val circuit = Driver.elaborate(gen) - Driver.parseArgs(args) - val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir") - Driver.dumpFirrtl(circuit, Option(output_file)) - } -} diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala index 9cdef80d..6e72cdd3 100644 --- a/src/main/scala/chisel/compatibility.scala +++ b/src/main/scala/chisel/compatibility.scala @@ -23,9 +23,6 @@ package object Chisel { val assert = chisel.assert - val BitPat = chisel.BitPat - type BitPat = chisel.BitPat - type Element = chisel.Element type Bits = chisel.Bits val Bits = chisel.Bits @@ -59,10 +56,10 @@ package object Chisel { type BackendCompilationUtilities = chisel.BackendCompilationUtilities val Driver = chisel.Driver - type FileSystemUtilities = chisel.FileSystemUtilities - val ImplicitConversions = chisel.ImplicitConversions - val chiselMain = chisel.chiselMain - val throwException = chisel.throwException + type FileSystemUtilities = chisel.compatibility.FileSystemUtilities + val ImplicitConversions = chisel.util.ImplicitConversions + val chiselMain = chisel.compatibility.chiselMain + val throwException = chisel.compatibility.throwException object testers { @@ -77,6 +74,9 @@ package object Chisel { val log2Floor = chisel.util.log2Floor val isPow2 = chisel.util.isPow2 + val BitPat = chisel.util.BitPat + type BitPat = chisel.util.BitPat + type ArbiterIO[T <: Data] = chisel.util.ArbiterIO[T] type LockingArbiterLike[T <: Data] = chisel.util.LockingArbiterLike[T] type LockingRRArbiter[T <: Data] = chisel.util.LockingRRArbiter[T] diff --git a/src/main/scala/chisel/compatibility/FileSystemUtilities.scala b/src/main/scala/chisel/compatibility/FileSystemUtilities.scala new file mode 100644 index 00000000..d12e627d --- /dev/null +++ b/src/main/scala/chisel/compatibility/FileSystemUtilities.scala @@ -0,0 +1,12 @@ +// See LICENSE for license details. + +package chisel.compatibility + +import chisel._ + +@deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0") +trait FileSystemUtilities { + def createOutputFile(name: String): java.io.FileWriter = { + new java.io.FileWriter(Driver.targetDir + "/" + name) + } +} diff --git a/src/main/scala/chisel/compatibility/Main.scala b/src/main/scala/chisel/compatibility/Main.scala new file mode 100644 index 00000000..9072bfcf --- /dev/null +++ b/src/main/scala/chisel/compatibility/Main.scala @@ -0,0 +1,19 @@ +// See LICENSE for license details. + +package chisel.compatibility + +import java.io.File + +import chisel._ + +@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain { + def apply[T <: Module](args: Array[String], gen: () => T): Unit = + Predef.assert(false, "No more chiselMain in Chisel3") + + def run[T <: Module] (args: Array[String], gen: () => T): Unit = { + val circuit = Driver.elaborate(gen) + Driver.parseArgs(args) + val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir") + Driver.dumpFirrtl(circuit, Option(output_file)) + } +} diff --git a/src/main/scala/chisel/compatibility/throwException.scala b/src/main/scala/chisel/compatibility/throwException.scala new file mode 100644 index 00000000..3b9fd06e --- /dev/null +++ b/src/main/scala/chisel/compatibility/throwException.scala @@ -0,0 +1,14 @@ +// See LICENSE for license details. + +package chisel.compatibility + +import chisel._ + +@deprecated("throwException doesn't exist in Chisel3", "3.0.0") +@throws(classOf[Exception]) +object throwException { + def apply(s: String, t: Throwable = null) = { + val xcpt = new Exception(s, t) + throw xcpt + } +} diff --git a/src/main/scala/chisel/package.scala b/src/main/scala/chisel/package.scala index 1abbc74f..b6036c75 100644 --- a/src/main/scala/chisel/package.scala +++ b/src/main/scala/chisel/package.scala @@ -3,6 +3,7 @@ package object chisel { import internal.firrtl.Width import internal.sourceinfo.{SourceInfo, SourceInfoTransform} + import util.BitPat implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { def U: UInt = UInt(x, Width()) diff --git a/src/main/scala/chisel/throwException.scala b/src/main/scala/chisel/throwException.scala deleted file mode 100644 index fdd62c7e..00000000 --- a/src/main/scala/chisel/throwException.scala +++ /dev/null @@ -1,12 +0,0 @@ -// See LICENSE for license details. - -package chisel - -@deprecated("throwException doesn't exist in Chisel3", "3.0.0") -@throws(classOf[Exception]) -object throwException { - def apply(s: String, t: Throwable = null) = { - val xcpt = new Exception(s, t) - throw xcpt - } -} diff --git a/src/main/scala/chisel/util/BitPat.scala b/src/main/scala/chisel/util/BitPat.scala new file mode 100644 index 00000000..13bbe1b0 --- /dev/null +++ b/src/main/scala/chisel/util/BitPat.scala @@ -0,0 +1,89 @@ +// See LICENSE for license details. + +package chisel.util + +import scala.language.experimental.macros + +import chisel._ +import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform} + +object BitPat { + /** Parses a bit pattern string into (bits, mask, width). + * + * @return bits the literal value, with don't cares being 0 + * @return mask the mask bits, with don't cares being 0 and cares being 1 + * @return width the number of bits in the literal, including values and + * don't cares. + */ + private def parse(x: String): (BigInt, BigInt, Int) = { + // Notes: + // While Verilog Xs also handle octal and hex cases, there isn't a + // compelling argument and no one has asked for it. + // If ? parsing is to be exposed, the return API needs further scrutiny + // (especially with things like mask polarity). + require(x.head == 'b', "BitPats must be in binary and be prefixed with 'b'") + var bits = BigInt(0) + var mask = BigInt(0) + for (d <- x.tail) { + if (d != '_') { + require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d) + mask = (mask << 1) + (if (d == '?') 0 else 1) + bits = (bits << 1) + (if (d == '1') 1 else 0) + } + } + (bits, mask, x.length - 1) + } + + /** Creates a [[BitPat]] literal from a string. + * + * @param n the literal value as a string, in binary, prefixed with 'b' + * @note legal characters are '0', '1', and '?', as well as '_' as white + * space (which are ignored) + */ + def apply(n: String): BitPat = { + val (bits, mask, width) = parse(n) + new BitPat(bits, mask, width) + } + + /** Creates a [[BitPat]] of all don't cares of the specified bitwidth. */ + def dontCare(width: Int): BitPat = BitPat("b" + ("?" * width)) + + @deprecated("Use BitPat.dontCare", "chisel3") + def DC(width: Int): BitPat = dontCare(width) // scalastyle:ignore method.name + + /** Allows BitPats to be used where a UInt is expected. + * + * @note the BitPat must not have don't care bits (will error out otherwise) + */ + def bitPatToUInt(x: BitPat): UInt = { + require(x.mask == (BigInt(1) << x.getWidth) - 1) + UInt(x.value, x.getWidth) + } + + /** Allows UInts to be used where a BitPat is expected, useful for when an + * interface is defined with BitPats but not all cases need the partial + * matching capability. + * + * @note the UInt must be a literal + */ + def apply(x: UInt): BitPat = { + require(x.isLit) + BitPat("b" + x.litValue.toString(2)) + } +} + +// TODO: Break out of Core? (this doesn't involve FIRRTL generation) +/** Bit patterns are literals with masks, used to represent values with don't + * cares. Equality comparisons will ignore don't care bits (for example, + * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)). + */ +sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) { + def getWidth: Int = width + def === (that: UInt): Bool = macro SourceInfoTransform.thatArg + def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg + def != (that: UInt): Bool = macro SourceInfoTransform.thatArg + + def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask)) + def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that) + def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that +} diff --git a/src/main/scala/chisel/util/ImplicitConversions.scala b/src/main/scala/chisel/util/ImplicitConversions.scala new file mode 100644 index 00000000..846c0cbd --- /dev/null +++ b/src/main/scala/chisel/util/ImplicitConversions.scala @@ -0,0 +1,10 @@ +// See LICENSE for license details. + +package chisel.util + +import chisel._ + +object ImplicitConversions { + implicit def intToUInt(x: Int): UInt = UInt(x) + implicit def booleanToBool(x: Boolean): Bool = Bool(x) +} -- cgit v1.2.3 From 69c984607e87cb62c82c99056b2664f11b968267 Mon Sep 17 00:00:00 2001 From: ducky Date: Wed, 1 Jun 2016 12:46:05 -0700 Subject: Package split chisel core --- src/main/scala/chisel/compatibility.scala | 96 +++++++++++++++---------------- src/main/scala/chisel/package.scala | 50 ++++++++++++++++ src/main/scala/chisel/util/Bitwise.scala | 1 + src/main/scala/chisel/util/Cat.scala | 1 + src/main/scala/chisel/util/Mux.scala | 1 + 5 files changed, 101 insertions(+), 48 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala index 6e72cdd3..54cf033d 100644 --- a/src/main/scala/chisel/compatibility.scala +++ b/src/main/scala/chisel/compatibility.scala @@ -4,54 +4,54 @@ // moving to the more standard package naming convention chisel (lowercase c). package object Chisel { - type Direction = chisel.Direction - val INPUT = chisel.INPUT - val OUTPUT = chisel.OUTPUT - val NO_DIR = chisel.NO_DIR - val debug = chisel.debug - type Flipped = chisel.Flipped - type Data = chisel.Data - val Wire = chisel.Wire - val Clock = chisel.Clock - type Clock = chisel.Clock - - type Aggregate = chisel.Aggregate - val Vec = chisel.Vec - type Vec[T <: Data] = chisel.Vec[T] - type VecLike[T <: Data] = chisel.VecLike[T] - type Bundle = chisel.Bundle - - val assert = chisel.assert - - type Element = chisel.Element - type Bits = chisel.Bits - val Bits = chisel.Bits - type Num[T <: Data] = chisel.Num[T] - type UInt = chisel.UInt - val UInt = chisel.UInt - type SInt = chisel.SInt - val SInt = chisel.SInt - type Bool = chisel.Bool - val Bool = chisel.Bool - val Mux = chisel.Mux - - type BlackBox = chisel.BlackBox - - val Mem = chisel.Mem - type MemBase[T <: Data] = chisel.MemBase[T] - type Mem[T <: Data] = chisel.Mem[T] - val SeqMem = chisel.SeqMem - type SeqMem[T <: Data] = chisel.SeqMem[T] - - val Module = chisel.Module - type Module = chisel.Module - - val printf = chisel.printf - - val Reg = chisel.Reg - - val when = chisel.when - type WhenContext = chisel.WhenContext + type Direction = chisel.core.Direction + val INPUT = chisel.core.INPUT + val OUTPUT = chisel.core.OUTPUT + val NO_DIR = chisel.core.NO_DIR + val debug = chisel.core.debug + type Flipped = chisel.core.Flipped + type Data = chisel.core.Data + val Wire = chisel.core.Wire + val Clock = chisel.core.Clock + type Clock = chisel.core.Clock + + type Aggregate = chisel.core.Aggregate + val Vec = chisel.core.Vec + type Vec[T <: Data] = chisel.core.Vec[T] + type VecLike[T <: Data] = chisel.core.VecLike[T] + type Bundle = chisel.core.Bundle + + val assert = chisel.core.assert + + type Element = chisel.core.Element + type Bits = chisel.core.Bits + val Bits = chisel.core.Bits + type Num[T <: Data] = chisel.core.Num[T] + type UInt = chisel.core.UInt + val UInt = chisel.core.UInt + type SInt = chisel.core.SInt + val SInt = chisel.core.SInt + type Bool = chisel.core.Bool + val Bool = chisel.core.Bool + val Mux = chisel.core.Mux + + type BlackBox = chisel.core.BlackBox + + val Mem = chisel.core.Mem + type MemBase[T <: Data] = chisel.core.MemBase[T] + type Mem[T <: Data] = chisel.core.Mem[T] + val SeqMem = chisel.core.SeqMem + type SeqMem[T <: Data] = chisel.core.SeqMem[T] + + val Module = chisel.core.Module + type Module = chisel.core.Module + + val printf = chisel.core.printf + + val Reg = chisel.core.Reg + + val when = chisel.core.when + type WhenContext = chisel.core.WhenContext type BackendCompilationUtilities = chisel.BackendCompilationUtilities diff --git a/src/main/scala/chisel/package.scala b/src/main/scala/chisel/package.scala index b6036c75..f7ed6b13 100644 --- a/src/main/scala/chisel/package.scala +++ b/src/main/scala/chisel/package.scala @@ -5,6 +5,56 @@ package object chisel { import internal.sourceinfo.{SourceInfo, SourceInfoTransform} import util.BitPat + + type Direction = chisel.core.Direction + val INPUT = chisel.core.INPUT + val OUTPUT = chisel.core.OUTPUT + val NO_DIR = chisel.core.NO_DIR + type Flipped = chisel.core.Flipped + type Data = chisel.core.Data + val Wire = chisel.core.Wire + val Clock = chisel.core.Clock + type Clock = chisel.core.Clock + + type Aggregate = chisel.core.Aggregate + val Vec = chisel.core.Vec + type Vec[T <: Data] = chisel.core.Vec[T] + type VecLike[T <: Data] = chisel.core.VecLike[T] + type Bundle = chisel.core.Bundle + + val assert = chisel.core.assert + + type Element = chisel.core.Element + type Bits = chisel.core.Bits + val Bits = chisel.core.Bits + type Num[T <: Data] = chisel.core.Num[T] + type UInt = chisel.core.UInt + val UInt = chisel.core.UInt + type SInt = chisel.core.SInt + val SInt = chisel.core.SInt + type Bool = chisel.core.Bool + val Bool = chisel.core.Bool + val Mux = chisel.core.Mux + + type BlackBox = chisel.core.BlackBox + + val Mem = chisel.core.Mem + type MemBase[T <: Data] = chisel.core.MemBase[T] + type Mem[T <: Data] = chisel.core.Mem[T] + val SeqMem = chisel.core.SeqMem + type SeqMem[T <: Data] = chisel.core.SeqMem[T] + + val Module = chisel.core.Module + type Module = chisel.core.Module + + val printf = chisel.core.printf + + val Reg = chisel.core.Reg + + val when = chisel.core.when + type WhenContext = chisel.core.WhenContext + + implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { def U: UInt = UInt(x, Width()) def S: SInt = SInt(x, Width()) diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala index 94413fc7..d7d62ea3 100644 --- a/src/main/scala/chisel/util/Bitwise.scala +++ b/src/main/scala/chisel/util/Bitwise.scala @@ -6,6 +6,7 @@ package chisel.util import chisel._ +import chisel.core.SeqUtils object FillInterleaved { diff --git a/src/main/scala/chisel/util/Cat.scala b/src/main/scala/chisel/util/Cat.scala index 5b3c613e..b47da706 100644 --- a/src/main/scala/chisel/util/Cat.scala +++ b/src/main/scala/chisel/util/Cat.scala @@ -3,6 +3,7 @@ package chisel.util import chisel._ +import chisel.core.SeqUtils object Cat { /** Combine data elements together diff --git a/src/main/scala/chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala index cfff4485..6f074a7e 100644 --- a/src/main/scala/chisel/util/Mux.scala +++ b/src/main/scala/chisel/util/Mux.scala @@ -6,6 +6,7 @@ package chisel.util import chisel._ +import chisel.core.SeqUtils /** Builds a Mux tree out of the input signal vector using a one hot encoded select signal. Returns the output of the Mux tree. -- cgit v1.2.3 From 68447044e8eba5c8f525639130f1a347677ff543 Mon Sep 17 00:00:00 2001 From: ducky Date: Wed, 1 Jun 2016 13:00:40 -0700 Subject: Move deprecated debug into compatibility --- src/main/scala/chisel/compatibility.scala | 4 ++-- src/main/scala/chisel/compatibility/debug.scala | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) create mode 100644 src/main/scala/chisel/compatibility/debug.scala (limited to 'src') diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala index 54cf033d..56088562 100644 --- a/src/main/scala/chisel/compatibility.scala +++ b/src/main/scala/chisel/compatibility.scala @@ -8,7 +8,7 @@ package object Chisel { val INPUT = chisel.core.INPUT val OUTPUT = chisel.core.OUTPUT val NO_DIR = chisel.core.NO_DIR - val debug = chisel.core.debug + type Flipped = chisel.core.Flipped type Data = chisel.core.Data val Wire = chisel.core.Wire @@ -60,7 +60,7 @@ package object Chisel { val ImplicitConversions = chisel.util.ImplicitConversions val chiselMain = chisel.compatibility.chiselMain val throwException = chisel.compatibility.throwException - + val debug = chisel.compatibility.debug object testers { type BasicTester = chisel.testers.BasicTester diff --git a/src/main/scala/chisel/compatibility/debug.scala b/src/main/scala/chisel/compatibility/debug.scala new file mode 100644 index 00000000..8850c76b --- /dev/null +++ b/src/main/scala/chisel/compatibility/debug.scala @@ -0,0 +1,8 @@ +package chisel.compatibility + +import chisel.core._ + +@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3") +object debug { // scalastyle:ignore object.name + def apply (arg: Data): Data = arg +} -- cgit v1.2.3 From d408d73a171535bd7c2ba9d0037c194022b8a62f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 20 Jun 2016 11:08:46 -0700 Subject: Rename chisel3 package. --- src/main/scala/chisel/Driver.scala | 132 --------------- src/main/scala/chisel/compatibility.scala | 150 ----------------- .../chisel/compatibility/FileSystemUtilities.scala | 12 -- src/main/scala/chisel/compatibility/Main.scala | 19 --- src/main/scala/chisel/compatibility/debug.scala | 8 - .../chisel/compatibility/throwException.scala | 14 -- .../scala/chisel/internal/firrtl/Emitter.scala | 112 ------------- src/main/scala/chisel/package.scala | 82 --------- src/main/scala/chisel/testers/BasicTester.scala | 38 ----- src/main/scala/chisel/testers/TesterDriver.scala | 69 -------- src/main/scala/chisel/util/Arbiter.scala | 119 ------------- src/main/scala/chisel/util/BitPat.scala | 89 ---------- src/main/scala/chisel/util/Bitwise.scala | 74 --------- src/main/scala/chisel/util/Cat.scala | 21 --- src/main/scala/chisel/util/CircuitMath.scala | 28 ---- src/main/scala/chisel/util/Conditional.scala | 73 -------- src/main/scala/chisel/util/Counter.scala | 46 ----- src/main/scala/chisel/util/Decoupled.scala | 185 --------------------- src/main/scala/chisel/util/Enum.scala | 23 --- .../scala/chisel/util/ImplicitConversions.scala | 10 -- src/main/scala/chisel/util/LFSR.scala | 24 --- src/main/scala/chisel/util/Lookup.scala | 19 --- src/main/scala/chisel/util/Math.scala | 44 ----- src/main/scala/chisel/util/Mux.scala | 64 ------- src/main/scala/chisel/util/OneHot.scala | 64 ------- src/main/scala/chisel/util/Reg.scala | 57 ------- src/main/scala/chisel/util/TransitName.scala | 22 --- src/main/scala/chisel/util/Valid.scala | 61 ------- src/main/scala/chisel3/Driver.scala | 132 +++++++++++++++ src/main/scala/chisel3/compatibility.scala | 150 +++++++++++++++++ .../compatibility/FileSystemUtilities.scala | 12 ++ src/main/scala/chisel3/compatibility/Main.scala | 19 +++ src/main/scala/chisel3/compatibility/debug.scala | 8 + .../chisel3/compatibility/throwException.scala | 14 ++ .../scala/chisel3/internal/firrtl/Emitter.scala | 112 +++++++++++++ src/main/scala/chisel3/package.scala | 82 +++++++++ src/main/scala/chisel3/testers/BasicTester.scala | 38 +++++ src/main/scala/chisel3/testers/TesterDriver.scala | 69 ++++++++ src/main/scala/chisel3/util/Arbiter.scala | 119 +++++++++++++ src/main/scala/chisel3/util/BitPat.scala | 89 ++++++++++ src/main/scala/chisel3/util/Bitwise.scala | 74 +++++++++ src/main/scala/chisel3/util/Cat.scala | 21 +++ src/main/scala/chisel3/util/CircuitMath.scala | 28 ++++ src/main/scala/chisel3/util/Conditional.scala | 73 ++++++++ src/main/scala/chisel3/util/Counter.scala | 46 +++++ src/main/scala/chisel3/util/Decoupled.scala | 185 +++++++++++++++++++++ src/main/scala/chisel3/util/Enum.scala | 23 +++ .../scala/chisel3/util/ImplicitConversions.scala | 10 ++ src/main/scala/chisel3/util/LFSR.scala | 24 +++ src/main/scala/chisel3/util/Lookup.scala | 19 +++ src/main/scala/chisel3/util/Math.scala | 44 +++++ src/main/scala/chisel3/util/Mux.scala | 64 +++++++ src/main/scala/chisel3/util/OneHot.scala | 64 +++++++ src/main/scala/chisel3/util/Reg.scala | 57 +++++++ src/main/scala/chisel3/util/TransitName.scala | 22 +++ src/main/scala/chisel3/util/Valid.scala | 61 +++++++ 56 files changed, 1659 insertions(+), 1659 deletions(-) delete mode 100644 src/main/scala/chisel/Driver.scala delete mode 100644 src/main/scala/chisel/compatibility.scala delete mode 100644 src/main/scala/chisel/compatibility/FileSystemUtilities.scala delete mode 100644 src/main/scala/chisel/compatibility/Main.scala delete mode 100644 src/main/scala/chisel/compatibility/debug.scala delete mode 100644 src/main/scala/chisel/compatibility/throwException.scala delete mode 100644 src/main/scala/chisel/internal/firrtl/Emitter.scala delete mode 100644 src/main/scala/chisel/package.scala delete mode 100644 src/main/scala/chisel/testers/BasicTester.scala delete mode 100644 src/main/scala/chisel/testers/TesterDriver.scala delete mode 100644 src/main/scala/chisel/util/Arbiter.scala delete mode 100644 src/main/scala/chisel/util/BitPat.scala delete mode 100644 src/main/scala/chisel/util/Bitwise.scala delete mode 100644 src/main/scala/chisel/util/Cat.scala delete mode 100644 src/main/scala/chisel/util/CircuitMath.scala delete mode 100644 src/main/scala/chisel/util/Conditional.scala delete mode 100644 src/main/scala/chisel/util/Counter.scala delete mode 100644 src/main/scala/chisel/util/Decoupled.scala delete mode 100644 src/main/scala/chisel/util/Enum.scala delete mode 100644 src/main/scala/chisel/util/ImplicitConversions.scala delete mode 100644 src/main/scala/chisel/util/LFSR.scala delete mode 100644 src/main/scala/chisel/util/Lookup.scala delete mode 100644 src/main/scala/chisel/util/Math.scala delete mode 100644 src/main/scala/chisel/util/Mux.scala delete mode 100644 src/main/scala/chisel/util/OneHot.scala delete mode 100644 src/main/scala/chisel/util/Reg.scala delete mode 100644 src/main/scala/chisel/util/TransitName.scala delete mode 100644 src/main/scala/chisel/util/Valid.scala create mode 100644 src/main/scala/chisel3/Driver.scala create mode 100644 src/main/scala/chisel3/compatibility.scala create mode 100644 src/main/scala/chisel3/compatibility/FileSystemUtilities.scala create mode 100644 src/main/scala/chisel3/compatibility/Main.scala create mode 100644 src/main/scala/chisel3/compatibility/debug.scala create mode 100644 src/main/scala/chisel3/compatibility/throwException.scala create mode 100644 src/main/scala/chisel3/internal/firrtl/Emitter.scala create mode 100644 src/main/scala/chisel3/package.scala create mode 100644 src/main/scala/chisel3/testers/BasicTester.scala create mode 100644 src/main/scala/chisel3/testers/TesterDriver.scala create mode 100644 src/main/scala/chisel3/util/Arbiter.scala create mode 100644 src/main/scala/chisel3/util/BitPat.scala create mode 100644 src/main/scala/chisel3/util/Bitwise.scala create mode 100644 src/main/scala/chisel3/util/Cat.scala create mode 100644 src/main/scala/chisel3/util/CircuitMath.scala create mode 100644 src/main/scala/chisel3/util/Conditional.scala create mode 100644 src/main/scala/chisel3/util/Counter.scala create mode 100644 src/main/scala/chisel3/util/Decoupled.scala create mode 100644 src/main/scala/chisel3/util/Enum.scala create mode 100644 src/main/scala/chisel3/util/ImplicitConversions.scala create mode 100644 src/main/scala/chisel3/util/LFSR.scala create mode 100644 src/main/scala/chisel3/util/Lookup.scala create mode 100644 src/main/scala/chisel3/util/Math.scala create mode 100644 src/main/scala/chisel3/util/Mux.scala create mode 100644 src/main/scala/chisel3/util/OneHot.scala create mode 100644 src/main/scala/chisel3/util/Reg.scala create mode 100644 src/main/scala/chisel3/util/TransitName.scala create mode 100644 src/main/scala/chisel3/util/Valid.scala (limited to 'src') diff --git a/src/main/scala/chisel/Driver.scala b/src/main/scala/chisel/Driver.scala deleted file mode 100644 index ba2b1389..00000000 --- a/src/main/scala/chisel/Driver.scala +++ /dev/null @@ -1,132 +0,0 @@ -// See LICENSE for license details. - -package chisel - -import scala.sys.process._ -import java.io._ - -import internal._ -import internal.firrtl._ - -trait BackendCompilationUtilities { - /** Create a temporary directory with the prefix name. Exists here because it doesn't in Java 6. - */ - def createTempDirectory(prefix: String): File = { - val temp = File.createTempFile(prefix, "") - if (!temp.delete()) { - throw new IOException(s"Unable to delete temp file '$temp'") - } - if (!temp.mkdir()) { - throw new IOException(s"Unable to create temp directory '$temp'") - } - temp - } - - def makeHarness(template: String => String, post: String)(f: File): File = { - val prefix = f.toString.split("/").last - val vf = new File(f.toString + post) - val w = new FileWriter(vf) - w.write(template(prefix)) - w.close() - vf - } - - def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder = { - Process( - Seq("firrtl", - "-i", s"$prefix.fir", - "-o", s"$prefix.v", - "-X", "verilog"), - dir) - } - - /** Generates a Verilator invocation to convert Verilog sources to C++ - * simulation sources. - * - * The Verilator prefix will be V$dutFile, and running this will generate - * C++ sources and headers as well as a makefile to compile them. - * - * @param dutFile name of the DUT .v without the .v extension - * @param name of the top-level module in the design - * @param dir output directory - * @param vSources list of additional Verilog sources to compile - * @param cppHarness C++ testharness to compile/link against - */ - def verilogToCpp( - dutFile: String, - topModule: String, - dir: File, - vSources: Seq[File], - cppHarness: File - ): ProcessBuilder = { - val command = Seq("verilator", - "--cc", s"$dutFile.v") ++ - vSources.map(file => Seq("-v", file.toString)).flatten ++ - Seq("--assert", - "-Wno-fatal", - "-Wno-WIDTH", - "-Wno-STMTDLY", - "--trace", - "-O2", - "--top-module", topModule, - "+define+TOP_TYPE=V" + dutFile, - s"+define+PRINTF_COND=!$topModule.reset", - "-CFLAGS", - s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""", - "-Mdir", dir.toString, - "--exe", cppHarness.toString) - System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex - command - } - - def cppToExe(prefix: String, dir: File): ProcessBuilder = - Seq("make", "-C", dir.toString, "-j", "-f", s"V${prefix}.mk", s"V${prefix}") - - def executeExpectingFailure( - prefix: String, - dir: File, - assertionMsg: String = "Assertion failed"): Boolean = { - var triggered = false - val e = Process(s"./V${prefix}", dir) ! - ProcessLogger(line => { - triggered = triggered || line.contains(assertionMsg) - System.out.println(line) // scalastyle:ignore regex - }) - triggered - } - - def executeExpectingSuccess(prefix: String, dir: File): Boolean = { - !executeExpectingFailure(prefix, dir) - } -} - -object Driver extends BackendCompilationUtilities { - - /** Elaborates the Module specified in the gen function into a Circuit - * - * @param gen a function that creates a Module hierarchy - * @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR) - */ - def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen())) - - def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen)) - - def dumpFirrtl(ir: Circuit, optName: Option[File]): File = { - val f = optName.getOrElse(new File(ir.name + ".fir")) - val w = new FileWriter(f) - w.write(Emitter.emit(ir)) - w.close() - f - } - - private var target_dir: Option[String] = None - def parseArgs(args: Array[String]): Unit = { - for (i <- 0 until args.size) { - if (args(i) == "--targetDir") { - target_dir = Some(args(i + 1)) - } - } - } - - def targetDir(): String = { target_dir getOrElse new File(".").getCanonicalPath } -} diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala deleted file mode 100644 index 56088562..00000000 --- a/src/main/scala/chisel/compatibility.scala +++ /dev/null @@ -1,150 +0,0 @@ -// See LICENSE for license details. - -// Allows legacy users to continue using Chisel (capital C) package name while -// moving to the more standard package naming convention chisel (lowercase c). - -package object Chisel { - type Direction = chisel.core.Direction - val INPUT = chisel.core.INPUT - val OUTPUT = chisel.core.OUTPUT - val NO_DIR = chisel.core.NO_DIR - - type Flipped = chisel.core.Flipped - type Data = chisel.core.Data - val Wire = chisel.core.Wire - val Clock = chisel.core.Clock - type Clock = chisel.core.Clock - - type Aggregate = chisel.core.Aggregate - val Vec = chisel.core.Vec - type Vec[T <: Data] = chisel.core.Vec[T] - type VecLike[T <: Data] = chisel.core.VecLike[T] - type Bundle = chisel.core.Bundle - - val assert = chisel.core.assert - - type Element = chisel.core.Element - type Bits = chisel.core.Bits - val Bits = chisel.core.Bits - type Num[T <: Data] = chisel.core.Num[T] - type UInt = chisel.core.UInt - val UInt = chisel.core.UInt - type SInt = chisel.core.SInt - val SInt = chisel.core.SInt - type Bool = chisel.core.Bool - val Bool = chisel.core.Bool - val Mux = chisel.core.Mux - - type BlackBox = chisel.core.BlackBox - - val Mem = chisel.core.Mem - type MemBase[T <: Data] = chisel.core.MemBase[T] - type Mem[T <: Data] = chisel.core.Mem[T] - val SeqMem = chisel.core.SeqMem - type SeqMem[T <: Data] = chisel.core.SeqMem[T] - - val Module = chisel.core.Module - type Module = chisel.core.Module - - val printf = chisel.core.printf - - val Reg = chisel.core.Reg - - val when = chisel.core.when - type WhenContext = chisel.core.WhenContext - - - type BackendCompilationUtilities = chisel.BackendCompilationUtilities - val Driver = chisel.Driver - type FileSystemUtilities = chisel.compatibility.FileSystemUtilities - val ImplicitConversions = chisel.util.ImplicitConversions - val chiselMain = chisel.compatibility.chiselMain - val throwException = chisel.compatibility.throwException - val debug = chisel.compatibility.debug - - object testers { - type BasicTester = chisel.testers.BasicTester - val TesterDriver = chisel.testers.TesterDriver - } - - - val log2Up = chisel.util.log2Up - val log2Ceil = chisel.util.log2Ceil - val log2Down = chisel.util.log2Down - val log2Floor = chisel.util.log2Floor - val isPow2 = chisel.util.isPow2 - - val BitPat = chisel.util.BitPat - type BitPat = chisel.util.BitPat - - type ArbiterIO[T <: Data] = chisel.util.ArbiterIO[T] - type LockingArbiterLike[T <: Data] = chisel.util.LockingArbiterLike[T] - type LockingRRArbiter[T <: Data] = chisel.util.LockingRRArbiter[T] - type LockingArbiter[T <: Data] = chisel.util.LockingArbiter[T] - type RRArbiter[T <: Data] = chisel.util.RRArbiter[T] - type Arbiter[T <: Data] = chisel.util.Arbiter[T] - - val FillInterleaved = chisel.util.FillInterleaved - val PopCount = chisel.util.PopCount - val Fill = chisel.util.Fill - val Reverse = chisel.util.Reverse - - val Cat = chisel.util.Cat - - val Log2 = chisel.util.Log2 - - val unless = chisel.util.unless - type SwitchContext[T <: Bits] = chisel.util.SwitchContext[T] - val is = chisel.util.is - val switch = chisel.util.switch - - type Counter = chisel.util.Counter - val Counter = chisel.util.Counter - - type DecoupledIO[+T <: Data] = chisel.util.DecoupledIO[T] - val Decoupled = chisel.util.Decoupled - type EnqIO[T <: Data] = chisel.util.EnqIO[T] - type DeqIO[T <: Data] = chisel.util.DeqIO[T] - type DecoupledIOC[+T <: Data] = chisel.util.DecoupledIOC[T] - type QueueIO[T <: Data] = chisel.util.QueueIO[T] - type Queue[T <: Data] = chisel.util.Queue[T] - val Queue = chisel.util.Queue - - val Enum = chisel.util.Enum - - val LFSR16 = chisel.util.LFSR16 - - val ListLookup = chisel.util.ListLookup - val Lookup = chisel.util.Lookup - - val Mux1H = chisel.util.Mux1H - val PriorityMux = chisel.util.PriorityMux - val MuxLookup = chisel.util.MuxLookup - val MuxCase = chisel.util.MuxCase - - val OHToUInt = chisel.util.OHToUInt - val PriorityEncoder = chisel.util.PriorityEncoder - val UIntToOH = chisel.util.UIntToOH - val PriorityEncoderOH = chisel.util.PriorityEncoderOH - - val RegNext = chisel.util.RegNext - val RegInit = chisel.util.RegInit - val RegEnable = chisel.util.RegEnable - val ShiftRegister = chisel.util.ShiftRegister - - type ValidIO[+T <: Data] = chisel.util.ValidIO[T] - val Valid = chisel.util.Valid - val Pipe = chisel.util.Pipe - type Pipe[T <: Data] = chisel.util.Pipe[T] - - - import chisel.internal.firrtl.Width - implicit def fromBigIntToLiteral(x: BigInt): chisel.fromBigIntToLiteral = - new chisel.fromBigIntToLiteral(x) - implicit def fromIntToLiteral(x: Int): chisel.fromIntToLiteral= - new chisel.fromIntToLiteral(x) - implicit def fromStringToLiteral(x: String): chisel.fromStringToLiteral= - new chisel.fromStringToLiteral(x) - implicit def fromBooleanToLiteral(x: Boolean): chisel.fromBooleanToLiteral= - new chisel.fromBooleanToLiteral(x) -} diff --git a/src/main/scala/chisel/compatibility/FileSystemUtilities.scala b/src/main/scala/chisel/compatibility/FileSystemUtilities.scala deleted file mode 100644 index d12e627d..00000000 --- a/src/main/scala/chisel/compatibility/FileSystemUtilities.scala +++ /dev/null @@ -1,12 +0,0 @@ -// See LICENSE for license details. - -package chisel.compatibility - -import chisel._ - -@deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0") -trait FileSystemUtilities { - def createOutputFile(name: String): java.io.FileWriter = { - new java.io.FileWriter(Driver.targetDir + "/" + name) - } -} diff --git a/src/main/scala/chisel/compatibility/Main.scala b/src/main/scala/chisel/compatibility/Main.scala deleted file mode 100644 index 9072bfcf..00000000 --- a/src/main/scala/chisel/compatibility/Main.scala +++ /dev/null @@ -1,19 +0,0 @@ -// See LICENSE for license details. - -package chisel.compatibility - -import java.io.File - -import chisel._ - -@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain { - def apply[T <: Module](args: Array[String], gen: () => T): Unit = - Predef.assert(false, "No more chiselMain in Chisel3") - - def run[T <: Module] (args: Array[String], gen: () => T): Unit = { - val circuit = Driver.elaborate(gen) - Driver.parseArgs(args) - val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir") - Driver.dumpFirrtl(circuit, Option(output_file)) - } -} diff --git a/src/main/scala/chisel/compatibility/debug.scala b/src/main/scala/chisel/compatibility/debug.scala deleted file mode 100644 index 8850c76b..00000000 --- a/src/main/scala/chisel/compatibility/debug.scala +++ /dev/null @@ -1,8 +0,0 @@ -package chisel.compatibility - -import chisel.core._ - -@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3") -object debug { // scalastyle:ignore object.name - def apply (arg: Data): Data = arg -} diff --git a/src/main/scala/chisel/compatibility/throwException.scala b/src/main/scala/chisel/compatibility/throwException.scala deleted file mode 100644 index 3b9fd06e..00000000 --- a/src/main/scala/chisel/compatibility/throwException.scala +++ /dev/null @@ -1,14 +0,0 @@ -// See LICENSE for license details. - -package chisel.compatibility - -import chisel._ - -@deprecated("throwException doesn't exist in Chisel3", "3.0.0") -@throws(classOf[Exception]) -object throwException { - def apply(s: String, t: Throwable = null) = { - val xcpt = new Exception(s, t) - throw xcpt - } -} diff --git a/src/main/scala/chisel/internal/firrtl/Emitter.scala b/src/main/scala/chisel/internal/firrtl/Emitter.scala deleted file mode 100644 index e48eb226..00000000 --- a/src/main/scala/chisel/internal/firrtl/Emitter.scala +++ /dev/null @@ -1,112 +0,0 @@ -// See LICENSE for license details. - -package chisel.internal.firrtl -import chisel._ -import chisel.internal.sourceinfo.{NoSourceInfo, SourceLine} - -private[chisel] object Emitter { - def emit(circuit: Circuit): String = new Emitter(circuit).toString -} - -private class Emitter(circuit: Circuit) { - override def toString: String = res.toString - - private def emitPort(e: Port): String = - s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}" - private def emit(e: Command, ctx: Component): String = { - val firrtlLine = e match { - case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})" - case e: DefWire => s"wire ${e.name} : ${e.id.toType}" - case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}" - case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" - case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]" - case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]" - case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" - case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" - case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" - case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})" - case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})""" - case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid" - case e: DefInstance => { - val modName = moduleMap.get(e.id.name).get - s"inst ${e.name} of $modName" - } - - case w: WhenBegin => - indent() - s"when ${w.pred.fullName(ctx)} :" - case _: WhenEnd => - unindent() - s"skip" - } - e.sourceInfo match { - case SourceLine(filename, line, col) => s"${firrtlLine} @[${filename} ${line}:${col}] " - case _: NoSourceInfo => firrtlLine - } - } - - // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already. - private val defnMap = collection.mutable.HashMap[String, String]() - // Map of Component name to FIRRTL id. - private val moduleMap = collection.mutable.HashMap[String, String]() - - /** Generates the FIRRTL module definition with a specified name. - */ - private def moduleDefn(m: Component, name: String): String = { - val body = new StringBuilder - m.id match { - case _: BlackBox => body ++= newline + s"extmodule $name : " - case _: Module => body ++= newline + s"module $name : " - } - withIndent { - for (p <- m.ports) - body ++= newline + emitPort(p) - body ++= newline - - m.id match { - case _: BlackBox => - // TODO: BlackBoxes should be empty, but funkiness in Module() means - // it's not for now. Eventually, this should assert out. - case _: Module => for (cmd <- m.commands) { - body ++= newline + emit(cmd, m) - } - } - body ++= newline - } - body.toString() - } - - /** Returns the FIRRTL declaration and body of a module, or nothing if it's a - * duplicate of something already emitted (on the basis of simple string - * matching). - */ - private def emit(m: Component): String = { - // Generate the body. - val moduleName = m.id.getClass.getName.split('.').last - val defn = moduleDefn(m, moduleName) - - defnMap get defn match { - case Some(deduplicatedName) => - moduleMap(m.name) = deduplicatedName - "" - case None => - require(!(moduleMap contains m.name), - "emitting module with same name but different contents") - - moduleMap(m.name) = m.name - defnMap(defn) = m.name - - moduleDefn(m, m.name) - } - } - - private var indentLevel = 0 - private def newline = "\n" + (" " * indentLevel) - private def indent(): Unit = indentLevel += 1 - private def unindent() { require(indentLevel > 0); indentLevel -= 1 } - private def withIndent(f: => Unit) { indent(); f; unindent() } - - private val res = new StringBuilder(s"circuit ${circuit.name} : ") - withIndent { circuit.components.foreach(c => res ++= emit(c)) } - res ++= newline -} diff --git a/src/main/scala/chisel/package.scala b/src/main/scala/chisel/package.scala deleted file mode 100644 index f7ed6b13..00000000 --- a/src/main/scala/chisel/package.scala +++ /dev/null @@ -1,82 +0,0 @@ -package object chisel { - import scala.language.experimental.macros - - import internal.firrtl.Width - import internal.sourceinfo.{SourceInfo, SourceInfoTransform} - import util.BitPat - - - type Direction = chisel.core.Direction - val INPUT = chisel.core.INPUT - val OUTPUT = chisel.core.OUTPUT - val NO_DIR = chisel.core.NO_DIR - type Flipped = chisel.core.Flipped - type Data = chisel.core.Data - val Wire = chisel.core.Wire - val Clock = chisel.core.Clock - type Clock = chisel.core.Clock - - type Aggregate = chisel.core.Aggregate - val Vec = chisel.core.Vec - type Vec[T <: Data] = chisel.core.Vec[T] - type VecLike[T <: Data] = chisel.core.VecLike[T] - type Bundle = chisel.core.Bundle - - val assert = chisel.core.assert - - type Element = chisel.core.Element - type Bits = chisel.core.Bits - val Bits = chisel.core.Bits - type Num[T <: Data] = chisel.core.Num[T] - type UInt = chisel.core.UInt - val UInt = chisel.core.UInt - type SInt = chisel.core.SInt - val SInt = chisel.core.SInt - type Bool = chisel.core.Bool - val Bool = chisel.core.Bool - val Mux = chisel.core.Mux - - type BlackBox = chisel.core.BlackBox - - val Mem = chisel.core.Mem - type MemBase[T <: Data] = chisel.core.MemBase[T] - type Mem[T <: Data] = chisel.core.Mem[T] - val SeqMem = chisel.core.SeqMem - type SeqMem[T <: Data] = chisel.core.SeqMem[T] - - val Module = chisel.core.Module - type Module = chisel.core.Module - - val printf = chisel.core.printf - - val Reg = chisel.core.Reg - - val when = chisel.core.when - type WhenContext = chisel.core.WhenContext - - - implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { - def U: UInt = UInt(x, Width()) - def S: SInt = SInt(x, Width()) - } - implicit class fromIntToLiteral(val x: Int) extends AnyVal { - def U: UInt = UInt(BigInt(x), Width()) - def S: SInt = SInt(BigInt(x), Width()) - } - implicit class fromStringToLiteral(val x: String) extends AnyVal { - def U: UInt = UInt(x) - } - implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { - def B: Bool = Bool(x) - } - - implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal { - final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg - final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg - final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg - - def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x - def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x - def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x - } -} diff --git a/src/main/scala/chisel/testers/BasicTester.scala b/src/main/scala/chisel/testers/BasicTester.scala deleted file mode 100644 index 36ff7c52..00000000 --- a/src/main/scala/chisel/testers/BasicTester.scala +++ /dev/null @@ -1,38 +0,0 @@ -// See LICENSE for license details. - -package chisel.testers -import chisel._ - -import scala.language.experimental.macros - -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.SourceInfo - -class BasicTester extends Module { - // The testbench has no IOs, rather it should communicate using printf, assert, and stop. - val io = new Bundle() - - def popCount(n: Long): Int = n.toBinaryString.count(_=='1') - - /** Ends the test reporting success. - * - * Does not fire when in reset (defined as the encapsulating Module's - * reset). If your definition of reset is not the encapsulating Module's - * reset, you will need to gate this externally. - */ - def stop()(implicit sourceInfo: SourceInfo) { - // TODO: rewrite this using library-style SourceInfo passing. - when (!reset) { - pushCommand(Stop(sourceInfo, Node(clock), 0)) - } - } - - /** The finish method provides a hook that subclasses of BasicTester can use to - * alter a circuit after their constructor has been called. - * For example, a specialized tester subclassing BasicTester could override finish in order to - * add flow control logic for a decoupled io port of a device under test - */ - def finish(): Unit = {} -} diff --git a/src/main/scala/chisel/testers/TesterDriver.scala b/src/main/scala/chisel/testers/TesterDriver.scala deleted file mode 100644 index 5c0275e0..00000000 --- a/src/main/scala/chisel/testers/TesterDriver.scala +++ /dev/null @@ -1,69 +0,0 @@ -// See LICENSE for license details. - -package chisel.testers - -import chisel._ -import scala.io.Source -import scala.sys.process._ -import java.io._ - -object TesterDriver extends BackendCompilationUtilities { - /** Copy the contents of a resource to a destination file. - */ - def copyResourceToFile(name: String, file: File) { - val in = getClass().getResourceAsStream(name) - if (in == null) { - throw new FileNotFoundException(s"Resource '$name'") - } - val out = new FileOutputStream(file) - Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write) - out.close() - } - - /** For use with modules that should successfully be elaborated by the - * frontend, and which can be turned into executables with assertions. */ - def execute(t: () => BasicTester, additionalVResources: Seq[String] = Seq()): Boolean = { - // Invoke the chisel compiler to get the circuit's IR - val circuit = Driver.elaborate(finishWrapper(t)) - - // Set up a bunch of file handlers based on a random temp filename, - // plus the quirks of Verilator's naming conventions - val target = circuit.name - - val path = createTempDirectory(target) - val fname = new File(path, target) - - // For now, dump the IR out to a file - Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir"))) - - // Copy CPP harness and other Verilog sources from resources into files - val cppHarness = new File(path, "top.cpp") - copyResourceToFile("/top.cpp", cppHarness) - val additionalVFiles = additionalVResources.map((name: String) => { - val mangledResourceName = name.replace("/", "_") - val out = new File(path, mangledResourceName) - copyResourceToFile(name, out) - out - }) - - // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe - if ((firrtlToVerilog(target, path) #&& - verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& - cppToExe(target, path)).! == 0) { - executeExpectingSuccess(target, path) - } else { - false - } - } - /** - * Calls the finish method of an BasicTester or a class that extends it. - * The finish method is a hook for code that augments the circuit built in the constructor. - */ - def finishWrapper(test: () => BasicTester): () => BasicTester = { - () => { - val tester = test() - tester.finish() - tester - } - } -} diff --git a/src/main/scala/chisel/util/Arbiter.scala b/src/main/scala/chisel/util/Arbiter.scala deleted file mode 100644 index 3723f2a9..00000000 --- a/src/main/scala/chisel/util/Arbiter.scala +++ /dev/null @@ -1,119 +0,0 @@ -// See LICENSE for license details. - -/** Arbiters in all shapes and sizes. - */ - -package chisel.util - -import chisel._ - -/** An I/O bundle for the Arbiter */ -class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { - val in = Vec(n, Decoupled(gen)).flip - val out = Decoupled(gen) - val chosen = UInt(OUTPUT, log2Up(n)) -} - -/** Arbiter Control determining which producer has access */ -private object ArbiterCtrl -{ - def apply(request: Seq[Bool]): Seq[Bool] = request.length match { - case 0 => Seq() - case 1 => Seq(Bool(true)) - case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_) - } -} - -abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module { - def grant: Seq[Bool] - def choice: UInt - val io = new ArbiterIO(gen, n) - - io.chosen := choice - io.out.valid := io.in(io.chosen).valid - io.out.bits := io.in(io.chosen).bits - - if (count > 1) { - val lockCount = Counter(count) - val lockIdx = Reg(UInt()) - val locked = lockCount.value =/= UInt(0) - val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true)) - - when (io.out.fire() && wantsLock) { - lockIdx := io.chosen - lockCount.inc() - } - - when (locked) { io.chosen := lockIdx } - for ((in, (g, i)) <- io.in zip grant.zipWithIndex) - in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready - } else { - for ((in, g) <- io.in zip grant) - in.ready := g && io.out.ready - } -} - -class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) - extends LockingArbiterLike[T](gen, n, count, needsLock) { - lazy val lastGrant = RegEnable(io.chosen, io.out.fire()) - lazy val grantMask = (0 until n).map(UInt(_) > lastGrant) - lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g } - - override def grant: Seq[Bool] = { - val ctrl = ArbiterCtrl((0 until n).map(i => validMask(i)) ++ io.in.map(_.valid)) - (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n)) - } - - override lazy val choice = Wire(init=UInt(n-1)) - for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } - for (i <- n-1 to 1 by -1) - when (validMask(i)) { choice := UInt(i) } -} - -class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) - extends LockingArbiterLike[T](gen, n, count, needsLock) { - def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid)) - - override lazy val choice = Wire(init=UInt(n-1)) - for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } -} - -/** Hardware module that is used to sequence n producers into 1 consumer. - Producers are chosen in round robin order. - - Example usage: - val arb = new RRArbiter(2, UInt()) - arb.io.in(0) <> producer0.io.out - arb.io.in(1) <> producer1.io.out - consumer.io.in <> arb.io.out - */ -class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) - -/** Hardware module that is used to sequence n producers into 1 consumer. - Priority is given to lower producer - - Example usage: - val arb = Module(new Arbiter(2, UInt())) - arb.io.in(0) <> producer0.io.out - arb.io.in(1) <> producer1.io.out - consumer.io.in <> arb.io.out - */ -class Arbiter[T <: Data](gen: T, n: Int) extends Module { - val io = new ArbiterIO(gen, n) - - io.chosen := UInt(n-1) - io.out.bits := io.in(n-1).bits - for (i <- n-2 to 0 by -1) { - when (io.in(i).valid) { - io.chosen := UInt(i) - io.out.bits := io.in(i).bits - } - } - - val grant = ArbiterCtrl(io.in.map(_.valid)) - for ((in, g) <- io.in zip grant) - in.ready := g && io.out.ready - io.out.valid := !grant.last || io.in.last.valid -} diff --git a/src/main/scala/chisel/util/BitPat.scala b/src/main/scala/chisel/util/BitPat.scala deleted file mode 100644 index 13bbe1b0..00000000 --- a/src/main/scala/chisel/util/BitPat.scala +++ /dev/null @@ -1,89 +0,0 @@ -// See LICENSE for license details. - -package chisel.util - -import scala.language.experimental.macros - -import chisel._ -import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform} - -object BitPat { - /** Parses a bit pattern string into (bits, mask, width). - * - * @return bits the literal value, with don't cares being 0 - * @return mask the mask bits, with don't cares being 0 and cares being 1 - * @return width the number of bits in the literal, including values and - * don't cares. - */ - private def parse(x: String): (BigInt, BigInt, Int) = { - // Notes: - // While Verilog Xs also handle octal and hex cases, there isn't a - // compelling argument and no one has asked for it. - // If ? parsing is to be exposed, the return API needs further scrutiny - // (especially with things like mask polarity). - require(x.head == 'b', "BitPats must be in binary and be prefixed with 'b'") - var bits = BigInt(0) - var mask = BigInt(0) - for (d <- x.tail) { - if (d != '_') { - require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d) - mask = (mask << 1) + (if (d == '?') 0 else 1) - bits = (bits << 1) + (if (d == '1') 1 else 0) - } - } - (bits, mask, x.length - 1) - } - - /** Creates a [[BitPat]] literal from a string. - * - * @param n the literal value as a string, in binary, prefixed with 'b' - * @note legal characters are '0', '1', and '?', as well as '_' as white - * space (which are ignored) - */ - def apply(n: String): BitPat = { - val (bits, mask, width) = parse(n) - new BitPat(bits, mask, width) - } - - /** Creates a [[BitPat]] of all don't cares of the specified bitwidth. */ - def dontCare(width: Int): BitPat = BitPat("b" + ("?" * width)) - - @deprecated("Use BitPat.dontCare", "chisel3") - def DC(width: Int): BitPat = dontCare(width) // scalastyle:ignore method.name - - /** Allows BitPats to be used where a UInt is expected. - * - * @note the BitPat must not have don't care bits (will error out otherwise) - */ - def bitPatToUInt(x: BitPat): UInt = { - require(x.mask == (BigInt(1) << x.getWidth) - 1) - UInt(x.value, x.getWidth) - } - - /** Allows UInts to be used where a BitPat is expected, useful for when an - * interface is defined with BitPats but not all cases need the partial - * matching capability. - * - * @note the UInt must be a literal - */ - def apply(x: UInt): BitPat = { - require(x.isLit) - BitPat("b" + x.litValue.toString(2)) - } -} - -// TODO: Break out of Core? (this doesn't involve FIRRTL generation) -/** Bit patterns are literals with masks, used to represent values with don't - * cares. Equality comparisons will ignore don't care bits (for example, - * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)). - */ -sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) { - def getWidth: Int = width - def === (that: UInt): Bool = macro SourceInfoTransform.thatArg - def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg - def != (that: UInt): Bool = macro SourceInfoTransform.thatArg - - def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask)) - def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that) - def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that -} diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala deleted file mode 100644 index d7d62ea3..00000000 --- a/src/main/scala/chisel/util/Bitwise.scala +++ /dev/null @@ -1,74 +0,0 @@ -// See LICENSE for license details. - -/** Miscellaneous circuit generators operating on bits. - */ - -package chisel.util - -import chisel._ -import chisel.core.SeqUtils - -object FillInterleaved -{ - def apply(n: Int, in: UInt): UInt = apply(n, in.toBools) - def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits -} - -/** Returns the number of bits set (i.e value is 1) in the input signal. - */ -object PopCount -{ - def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq) - def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_))) -} - -/** Fill fans out a UInt to multiple copies */ -object Fill { - /** Fan out x n times */ - def apply(n: Int, x: UInt): UInt = { - n match { - case 0 => UInt(width=0) - case 1 => x - case y if n > 1 => - val p2 = Array.ofDim[UInt](log2Up(n + 1)) - p2(0) = x - for (i <- 1 until p2.length) - p2(i) = Cat(p2(i-1), p2(i-1)) - Cat((0 until log2Up(y + 1)).filter(i => (y & (1 << i)) != 0).map(p2(_))) - case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.") - } - } - /** Fan out x n times */ - def apply(n: Int, x: Bool): UInt = - if (n > 1) { - UInt(0,n) - x - } else { - apply(n, x: UInt) - } -} - -/** Litte/big bit endian convertion: reverse the order of the bits in a UInt. -*/ -object Reverse -{ - private def doit(in: UInt, length: Int): UInt = { - if (length == 1) { - in - } else if (isPow2(length) && length >= 8 && length <= 64) { - // This esoterica improves simulation performance - var res = in - var shift = length >> 1 - var mask = UInt((BigInt(1) << length) - 1, length) - do { - mask = mask ^ (mask(length-shift-1,0) << shift) - res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask) - shift = shift >> 1 - } while (shift > 0) - res - } else { - val half = (1 << log2Up(length))/2 - Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half)) - } - } - def apply(in: UInt): UInt = doit(in, in.getWidth) -} diff --git a/src/main/scala/chisel/util/Cat.scala b/src/main/scala/chisel/util/Cat.scala deleted file mode 100644 index b47da706..00000000 --- a/src/main/scala/chisel/util/Cat.scala +++ /dev/null @@ -1,21 +0,0 @@ -// See LICENSE for license details. - -package chisel.util - -import chisel._ -import chisel.core.SeqUtils - -object Cat { - /** Combine data elements together - * @param a Data to combine with - * @param r any number of other Data elements to be combined in order - * @return A UInt which is all of the bits combined together - */ - def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList) - - /** Combine data elements together - * @param r any number of other Data elements to be combined in order - * @return A UInt which is all of the bits combined together - */ - def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse) -} diff --git a/src/main/scala/chisel/util/CircuitMath.scala b/src/main/scala/chisel/util/CircuitMath.scala deleted file mode 100644 index c3b94fdb..00000000 --- a/src/main/scala/chisel/util/CircuitMath.scala +++ /dev/null @@ -1,28 +0,0 @@ -// See LICENSE for license details. - -/** Circuit-land math operations. - */ - -package chisel.util - -import chisel._ - -/** Compute Log2 with truncation of a UInt in hardware using a Mux Tree - * An alternative interpretation is it computes the minimum number of bits needed to represent x - * @example - * {{{ data_out := Log2(data_in) }}} - * @note Truncation is used so Log2(UInt(12412)) = 13*/ -object Log2 { - /** Compute the Log2 on the least significant n bits of x */ - def apply(x: Bits, width: Int): UInt = { - if (width < 2) { - UInt(0) - } else if (width == 2) { - x(1) - } else { - Mux(x(width-1), UInt(width-1), apply(x, width-1)) - } - } - - def apply(x: Bits): UInt = apply(x, x.getWidth) -} diff --git a/src/main/scala/chisel/util/Conditional.scala b/src/main/scala/chisel/util/Conditional.scala deleted file mode 100644 index 01c12799..00000000 --- a/src/main/scala/chisel/util/Conditional.scala +++ /dev/null @@ -1,73 +0,0 @@ -// See LICENSE for license details. - -/** Conditional blocks. - */ - -package chisel.util - -import scala.language.reflectiveCalls -import scala.language.experimental.macros -import scala.reflect.runtime.universe._ -import scala.reflect.macros.blackbox._ - -import chisel._ - -/** This is identical to [[Chisel.when when]] with the condition inverted */ -object unless { // scalastyle:ignore object.name - def apply(c: Bool)(block: => Unit) { - when (!c) { block } - } -} - -class SwitchContext[T <: Bits](cond: T) { - def is(v: Iterable[T])(block: => Unit) { - if (!v.isEmpty) when (v.map(_.asUInt === cond.asUInt).reduce(_||_)) { block } - } - def is(v: T)(block: => Unit) { is(Seq(v))(block) } - def is(v: T, vr: T*)(block: => Unit) { is(v :: vr.toList)(block) } -} - -/** An object for separate cases in [[Chisel.switch switch]] - * It is equivalent to a [[Chisel.when$ when]] block comparing to the condition - * Use outside of a switch statement is illegal */ -object is { // scalastyle:ignore object.name - // Begin deprecation of non-type-parameterized is statements. - def apply(v: Iterable[Bits])(block: => Unit) { - require(false, "The 'is' keyword may not be used outside of a switch.") - } - - def apply(v: Bits)(block: => Unit) { - require(false, "The 'is' keyword may not be used outside of a switch.") - } - - def apply(v: Bits, vr: Bits*)(block: => Unit) { - require(false, "The 'is' keyword may not be used outside of a switch.") - } -} - -/** Conditional logic to form a switch block - * @example - * {{{ ... // default values here - * switch ( myState ) { - * is( state1 ) { - * ... // some logic here - * } - * is( state2 ) { - * ... // some logic here - * } - * } }}}*/ -object switch { // scalastyle:ignore object.name - def apply[T <: Bits](cond: T)(x: => Unit): Unit = macro impl - def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._ - val sc = c.universe.internal.reificationSupport.freshTermName("sc") - def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match { - // TODO: remove when Chisel compatibility package is removed - case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") - case q"chisel.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") - case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.") - } - val q"..$body" = x - val ises = body.flatMap(extractIsStatement(_)) - q"""{ val $sc = new SwitchContext($cond); ..$ises }""" - } -} diff --git a/src/main/scala/chisel/util/Counter.scala b/src/main/scala/chisel/util/Counter.scala deleted file mode 100644 index 1c0b0203..00000000 --- a/src/main/scala/chisel/util/Counter.scala +++ /dev/null @@ -1,46 +0,0 @@ -// See LICENSE for license details. - -package chisel.util - -import chisel._ - -/** A counter module - * @param n number of counts before the counter resets (or one more than the - * maximum output value of the counter), need not be a power of two - */ -class Counter(val n: Int) { - require(n >= 0) - val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0) - /** Increment the counter, returning whether the counter currently is at the - * maximum and will wrap. The incremented value is registered and will be - * visible on the next cycle. - */ - def inc(): Bool = { - if (n > 1) { - val wrap = value === UInt(n-1) - value := value + UInt(1) - if (!isPow2(n)) { - when (wrap) { value := UInt(0) } - } - wrap - } else { - Bool(true) - } - } -} - -/** Counter Object - * Example Usage: - * {{{ val countOn = Bool(true) // increment counter every clock cycle - * val myCounter = Counter(countOn, n) - * when ( myCounter.value === UInt(3) ) { ... } }}}*/ -object Counter -{ - def apply(n: Int): Counter = new Counter(n) - def apply(cond: Bool, n: Int): (UInt, Bool) = { - val c = new Counter(n) - var wrap: Bool = null - when (cond) { wrap = c.inc() } - (c.value, cond && wrap) - } -} diff --git a/src/main/scala/chisel/util/Decoupled.scala b/src/main/scala/chisel/util/Decoupled.scala deleted file mode 100644 index 89b0e39d..00000000 --- a/src/main/scala/chisel/util/Decoupled.scala +++ /dev/null @@ -1,185 +0,0 @@ -// See LICENSE for license details. - -/** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them. - */ - -package chisel.util - -import chisel._ - -/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/ -class DecoupledIO[+T <: Data](gen: T) extends Bundle -{ - val ready = Bool(INPUT) - val valid = Bool(OUTPUT) - val bits = gen.cloneType.asOutput - def fire(dummy: Int = 0): Bool = ready && valid - override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type] -} - -/** Adds a ready-valid handshaking protocol to any interface. - * The standard used is that the consumer uses the flipped interface. - */ -object Decoupled { - def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen) -} - -/** An I/O bundle for enqueuing data with valid/ready handshaking - * Initialization must be handled, if necessary, by the parent circuit - */ -class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen) -{ - /** push dat onto the output bits of this interface to let the consumer know it has happened. - * @param dat the values to assign to bits. - * @return dat. - */ - def enq(dat: T): T = { valid := Bool(true); bits := dat; dat } - - /** Initialize this Bundle. Valid is set to false, and all bits are set to zero. - * NOTE: This method of initialization is still being discussed and could change in the - * future. - */ - def init(): Unit = { - valid := Bool(false) - for (io <- bits.flatten) - io := UInt(0) - } - override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; } -} - -/** An I/O bundle for dequeuing data with valid/ready handshaking. - * Initialization must be handled, if necessary, by the parent circuit - */ -class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped -{ - /** Assert ready on this port and return the associated data bits. - * This is typically used when valid has been asserted by the producer side. - * @param b ignored - * @return the data for this device, - */ - def deq(b: Boolean = false): T = { ready := Bool(true); bits } - - /** Initialize this Bundle. - * NOTE: This method of initialization is still being discussed and could change in the - * future. - */ - def init(): Unit = { - ready := Bool(false) - } - override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; } -} - -/** An I/O bundle for dequeuing data with valid/ready handshaking */ -class DecoupledIOC[+T <: Data](gen: T) extends Bundle -{ - val ready = Bool(INPUT) - val valid = Bool(OUTPUT) - val bits = gen.cloneType.asOutput -} - -/** An I/O Bundle for Queues - * @param gen The type of data to queue - * @param entries The max number of entries in the queue */ -class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle -{ - /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */ - val enq = Decoupled(gen.cloneType).flip() - /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/ - val deq = Decoupled(gen.cloneType) - /** The current amount of data in the queue */ - val count = UInt(OUTPUT, log2Up(entries + 1)) -} - -/** A hardware module implementing a Queue - * @param gen The type of data to queue - * @param entries The max number of entries in the queue - * @param pipe True if a single entry queue can run at full throughput (like a pipeline). The ''ready'' signals are - * combinationally coupled. - * @param flow True if the inputs can be consumed on the same cycle (the inputs "flow" through the queue immediately). - * The ''valid'' signals are coupled. - * - * Example usage: - * {{{ val q = new Queue(UInt(), 16) - * q.io.enq <> producer.io.out - * consumer.io.in <> q.io.deq }}} - */ -class Queue[T <: Data](gen: T, val entries: Int, - pipe: Boolean = false, - flow: Boolean = false, - override_reset: Option[Bool] = None) -extends Module(override_reset=override_reset) { - def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) = - this(gen, entries, pipe, flow, Some(_reset)) - - val io = new QueueIO(gen, entries) - - val ram = Mem(entries, gen) - val enq_ptr = Counter(entries) - val deq_ptr = Counter(entries) - val maybe_full = Reg(init=Bool(false)) - - val ptr_match = enq_ptr.value === deq_ptr.value - val empty = ptr_match && !maybe_full - val full = ptr_match && maybe_full - val do_enq = Wire(init=io.enq.fire()) - val do_deq = Wire(init=io.deq.fire()) - - when (do_enq) { - ram(enq_ptr.value) := io.enq.bits - enq_ptr.inc() - } - when (do_deq) { - deq_ptr.inc() - } - when (do_enq != do_deq) { - maybe_full := do_enq - } - - io.deq.valid := !empty - io.enq.ready := !full - io.deq.bits := ram(deq_ptr.value) - - if (flow) { - when (io.enq.valid) { io.deq.valid := Bool(true) } - when (empty) { - io.deq.bits := io.enq.bits - do_deq := Bool(false) - when (io.deq.ready) { do_enq := Bool(false) } - } - } - - if (pipe) { - when (io.deq.ready) { io.enq.ready := Bool(true) } - } - - val ptr_diff = enq_ptr.value - deq_ptr.value - if (isPow2(entries)) { - io.count := Cat(maybe_full && ptr_match, ptr_diff) - } else { - io.count := Mux(ptr_match, - Mux(maybe_full, - UInt(entries), UInt(0)), - Mux(deq_ptr.value > enq_ptr.value, - UInt(entries) + ptr_diff, ptr_diff)) - } -} - -/** Generic hardware queue. Required parameter entries controls - the depth of the queues. The width of the queue is determined - from the inputs. - - Example usage: - {{{ val q = Queue(Decoupled(UInt()), 16) - q.io.enq <> producer.io.out - consumer.io.in <> q.io.deq }}} - */ -object Queue -{ - def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T] = { - val q = Module(new Queue(enq.bits.cloneType, entries, pipe)) - q.io.enq.valid := enq.valid // not using <> so that override is allowed - q.io.enq.bits := enq.bits - enq.ready := q.io.enq.ready - TransitName(q.io.deq, q) - } -} diff --git a/src/main/scala/chisel/util/Enum.scala b/src/main/scala/chisel/util/Enum.scala deleted file mode 100644 index 8babcd23..00000000 --- a/src/main/scala/chisel/util/Enum.scala +++ /dev/null @@ -1,23 +0,0 @@ -// See LICENSE for license details. - -/** Enum generators, allowing circuit constants to have more meaningful names. - */ - -package chisel.util - -import chisel._ - -object Enum { - /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */ - private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] = - (0 until n).map(x => nodeType.fromInt(x, log2Up(n))) - - /** create n enum values of given type */ - def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList - - /** create enum values of given type and names */ - def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap - - /** create enum values of given type and names */ - def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap -} diff --git a/src/main/scala/chisel/util/ImplicitConversions.scala b/src/main/scala/chisel/util/ImplicitConversions.scala deleted file mode 100644 index 846c0cbd..00000000 --- a/src/main/scala/chisel/util/ImplicitConversions.scala +++ /dev/null @@ -1,10 +0,0 @@ -// See LICENSE for license details. - -package chisel.util - -import chisel._ - -object ImplicitConversions { - implicit def intToUInt(x: Int): UInt = UInt(x) - implicit def booleanToBool(x: Boolean): Bool = Bool(x) -} diff --git a/src/main/scala/chisel/util/LFSR.scala b/src/main/scala/chisel/util/LFSR.scala deleted file mode 100644 index f70630bf..00000000 --- a/src/main/scala/chisel/util/LFSR.scala +++ /dev/null @@ -1,24 +0,0 @@ -// See LICENSE for license details. - -/** LFSRs in all shapes and sizes. - */ - -package chisel.util - -import chisel._ - -// scalastyle:off magic.number -/** linear feedback shift register - */ -object LFSR16 -{ - def apply(increment: Bool = Bool(true)): UInt = - { - val width = 16 - val lfsr = Reg(init=UInt(1, width)) - when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } - lfsr - } -} -// scalastyle:on magic.number - diff --git a/src/main/scala/chisel/util/Lookup.scala b/src/main/scala/chisel/util/Lookup.scala deleted file mode 100644 index d32d9aec..00000000 --- a/src/main/scala/chisel/util/Lookup.scala +++ /dev/null @@ -1,19 +0,0 @@ -// See LICENSE for license details. - -package chisel.util - -import chisel._ - -object ListLookup { - def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = { - val map = mapping.map(m => (m._1 === addr, m._2)) - default.zipWithIndex map { case (d, i) => - map.foldRight(d)((m, n) => Mux(m._1, m._2(i), n)) - } - } -} - -object Lookup { - def apply[T <: Bits](addr: UInt, default: T, mapping: Seq[(BitPat, T)]): T = - ListLookup(addr, List(default), mapping.map(m => (m._1, List(m._2))).toArray).head -} diff --git a/src/main/scala/chisel/util/Math.scala b/src/main/scala/chisel/util/Math.scala deleted file mode 100644 index 69464d15..00000000 --- a/src/main/scala/chisel/util/Math.scala +++ /dev/null @@ -1,44 +0,0 @@ -// See LICENSE for license details. - -/** Scala-land math helper functions, like logs. - */ - -package chisel.util - -import chisel._ - -/** Compute the log2 rounded up with min value of 1 */ -object log2Up { - def apply(in: BigInt): Int = { - require(in >= 0) - 1 max (in-1).bitLength - } - def apply(in: Int): Int = apply(BigInt(in)) -} - -/** Compute the log2 rounded up */ -object log2Ceil { - def apply(in: BigInt): Int = { - require(in > 0) - (in-1).bitLength - } - def apply(in: Int): Int = apply(BigInt(in)) -} - -/** Compute the log2 rounded down with min value of 1 */ -object log2Down { - def apply(in: BigInt): Int = log2Up(in) - (if (isPow2(in)) 0 else 1) - def apply(in: Int): Int = apply(BigInt(in)) -} - -/** Compute the log2 rounded down */ -object log2Floor { - def apply(in: BigInt): Int = log2Ceil(in) - (if (isPow2(in)) 0 else 1) - def apply(in: Int): Int = apply(BigInt(in)) -} - -/** Check if an Integer is a power of 2 */ -object isPow2 { - def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0) - def apply(in: Int): Boolean = apply(BigInt(in)) -} diff --git a/src/main/scala/chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala deleted file mode 100644 index 6f074a7e..00000000 --- a/src/main/scala/chisel/util/Mux.scala +++ /dev/null @@ -1,64 +0,0 @@ -// See LICENSE for license details. - -/** Mux circuit generators. - */ - -package chisel.util - -import chisel._ -import chisel.core.SeqUtils - -/** Builds a Mux tree out of the input signal vector using a one hot encoded - select signal. Returns the output of the Mux tree. - */ -object Mux1H -{ - def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = - apply(sel zip in) - def apply[T <: Data](in: Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in) - def apply[T <: Data](sel: UInt, in: Seq[T]): T = - apply((0 until in.size).map(sel(_)), in) - def apply(sel: UInt, in: UInt): Bool = (sel & in).orR -} - -/** Builds a Mux tree under the assumption that multiple select signals - can be enabled. Priority is given to the first select signal. - - Returns the output of the Mux tree. - */ -object PriorityMux -{ - def apply[T <: Data](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in) - def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in) - def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in) -} - -/** MuxLookup creates a cascade of n Muxs to search for a key value */ -object MuxLookup { - /** @param key a key to search for - * @param default a default value if nothing is found - * @param mapping a sequence to search of keys and values - * @return the value found or the default if not - */ - def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = { - var res = default - for ((k, v) <- mapping.reverse) - res = Mux(k === key, v, res) - res - } - -} - -/** MuxCase returns the first value that is enabled in a map of values */ -object MuxCase { - /** @param default the default value if none are enabled - * @param mapping a set of data values with associated enables - * @return the first value in mapping that is enabled */ - def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = { - var res = default - for ((t, v) <- mapping.reverse){ - res = Mux(t, v, res) - } - res - } -} diff --git a/src/main/scala/chisel/util/OneHot.scala b/src/main/scala/chisel/util/OneHot.scala deleted file mode 100644 index ef21c65d..00000000 --- a/src/main/scala/chisel/util/OneHot.scala +++ /dev/null @@ -1,64 +0,0 @@ -// See LICENSE for license details. - -/** Circuit generators for working with one-hot representations. - */ - -package chisel.util - -import chisel._ - -/** Converts from One Hot Encoding to a UInt indicating which bit is active - * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/ -object OHToUInt { - def apply(in: Seq[Bool]): UInt = apply(Vec(in)) - def apply(in: Vec[Bool]): UInt = apply(in.toBits, in.size) - def apply(in: Bits): UInt = apply(in, in.getWidth) - - def apply(in: Bits, width: Int): UInt = { - if (width <= 2) { - Log2(in, width) - } else { - val mid = 1 << (log2Up(width)-1) - val hi = in(width-1, mid) - val lo = in(mid-1, 0) - Cat(hi.orR, apply(hi | lo, mid)) - } - } -} - -/** @return the bit position of the trailing 1 in the input vector - * with the assumption that multiple bits of the input bit vector can be set - * @example {{{ data_out := PriorityEncoder(data_in) }}} - */ -object PriorityEncoder { - def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_))) - def apply(in: Bits): UInt = apply(in.toBools) -} - -/** Returns the one hot encoding of the input UInt. - */ -object UIntToOH -{ - def apply(in: UInt, width: Int = -1): UInt = - if (width == -1) { - UInt(1) << in - } else { - (UInt(1) << in(log2Up(width)-1,0))(width-1,0) - } -} - -/** Returns a bit vector in which only the least-significant 1 bit in - the input vector, if any, is set. - */ -object PriorityEncoderOH -{ - private def encode(in: Seq[Bool]): UInt = { - val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size)) - PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size)) - } - def apply(in: Seq[Bool]): Seq[Bool] = { - val enc = encode(in) - Seq.tabulate(in.size)(enc(_)) - } - def apply(in: Bits): UInt = encode((0 until in.getWidth).map(i => in(i))) -} diff --git a/src/main/scala/chisel/util/Reg.scala b/src/main/scala/chisel/util/Reg.scala deleted file mode 100644 index 1b40646d..00000000 --- a/src/main/scala/chisel/util/Reg.scala +++ /dev/null @@ -1,57 +0,0 @@ -// See LICENSE for license details. - -/** Variations and helpers for registers. - */ - -package chisel.util - -import chisel._ - -object RegNext { - - def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T]) - - def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init) - -} - -object RegInit { - - def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init) - -} - -/** A register with an Enable signal */ -object RegEnable -{ - def apply[T <: Data](updateData: T, enable: Bool): T = { - val r = Reg(updateData) - when (enable) { r := updateData } - r - } - def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = { - val r = RegInit(resetData) - when (enable) { r := updateData } - r - } -} - -/** Returns the n-cycle delayed version of the input signal. - */ -object ShiftRegister -{ - /** @param in input to delay - * @param n number of cycles to delay - * @param en enable the shift */ - def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = - { - // The order of tests reflects the expected use cases. - if (n == 1) { - RegEnable(in, en) - } else if (n != 0) { - RegNext(apply(in, n-1, en)) - } else { - in - } - } -} diff --git a/src/main/scala/chisel/util/TransitName.scala b/src/main/scala/chisel/util/TransitName.scala deleted file mode 100644 index 04e1995b..00000000 --- a/src/main/scala/chisel/util/TransitName.scala +++ /dev/null @@ -1,22 +0,0 @@ -package chisel.util - -import chisel._ -import internal.HasId - -object TransitName { - // The purpose of this is to allow a library to 'move' a name call to a more - // appropriate place. - // For example, a library factory function may create a module and return - // the io. The only user-exposed field is that given IO, which can't use - // any name supplied by the user. This can add a hook so that the supplied - // name then names the Module. - // See Queue companion object for working example - def apply[T<:HasId](from: T, to: HasId): T = { - from.addPostnameHook((given_name: String) => {to.suggestName(given_name)}) - from - } - def withSuffix[T<:HasId](suffix: String)(from: T, to: HasId): T = { - from.addPostnameHook((given_name: String) => {to.suggestName(given_name+suffix)}) - from - } -} diff --git a/src/main/scala/chisel/util/Valid.scala b/src/main/scala/chisel/util/Valid.scala deleted file mode 100644 index 56ac9abb..00000000 --- a/src/main/scala/chisel/util/Valid.scala +++ /dev/null @@ -1,61 +0,0 @@ -// See LICENSE for license details. - -/** Wrappers for valid interfaces and associated circuit generators using them. - */ - -package chisel.util - -import chisel._ - -/** An I/O Bundle containing data and a signal determining if it is valid */ -class ValidIO[+T <: Data](gen2: T) extends Bundle -{ - val valid = Bool(OUTPUT) - val bits = gen2.cloneType.asOutput - def fire(dummy: Int = 0): Bool = valid - override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type] -} - -/** Adds a valid protocol to any interface. The standard used is - that the consumer uses the flipped interface. -*/ -object Valid { - def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen) -} - -/** A hardware module that delays data coming down the pipeline - by the number of cycles set by the latency parameter. Functionality - is similar to ShiftRegister but this exposes a Pipe interface. - - Example usage: - val pipe = new Pipe(UInt()) - pipe.io.enq <> produce.io.out - consumer.io.in <> pipe.io.deq - */ -object Pipe -{ - def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = { - if (latency == 0) { - val out = Wire(Valid(enqBits)) - out.valid <> enqValid - out.bits <> enqBits - out - } else { - val v = Reg(Bool(), next=enqValid, init=Bool(false)) - val b = RegEnable(enqBits, enqValid) - apply(v, b, latency-1) - } - } - def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1) - def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency) -} - -class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module -{ - val io = new Bundle { - val enq = Valid(gen).flip - val deq = Valid(gen) - } - - io.deq <> Pipe(io.enq, latency) -} diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala new file mode 100644 index 00000000..ba2b1389 --- /dev/null +++ b/src/main/scala/chisel3/Driver.scala @@ -0,0 +1,132 @@ +// See LICENSE for license details. + +package chisel + +import scala.sys.process._ +import java.io._ + +import internal._ +import internal.firrtl._ + +trait BackendCompilationUtilities { + /** Create a temporary directory with the prefix name. Exists here because it doesn't in Java 6. + */ + def createTempDirectory(prefix: String): File = { + val temp = File.createTempFile(prefix, "") + if (!temp.delete()) { + throw new IOException(s"Unable to delete temp file '$temp'") + } + if (!temp.mkdir()) { + throw new IOException(s"Unable to create temp directory '$temp'") + } + temp + } + + def makeHarness(template: String => String, post: String)(f: File): File = { + val prefix = f.toString.split("/").last + val vf = new File(f.toString + post) + val w = new FileWriter(vf) + w.write(template(prefix)) + w.close() + vf + } + + def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder = { + Process( + Seq("firrtl", + "-i", s"$prefix.fir", + "-o", s"$prefix.v", + "-X", "verilog"), + dir) + } + + /** Generates a Verilator invocation to convert Verilog sources to C++ + * simulation sources. + * + * The Verilator prefix will be V$dutFile, and running this will generate + * C++ sources and headers as well as a makefile to compile them. + * + * @param dutFile name of the DUT .v without the .v extension + * @param name of the top-level module in the design + * @param dir output directory + * @param vSources list of additional Verilog sources to compile + * @param cppHarness C++ testharness to compile/link against + */ + def verilogToCpp( + dutFile: String, + topModule: String, + dir: File, + vSources: Seq[File], + cppHarness: File + ): ProcessBuilder = { + val command = Seq("verilator", + "--cc", s"$dutFile.v") ++ + vSources.map(file => Seq("-v", file.toString)).flatten ++ + Seq("--assert", + "-Wno-fatal", + "-Wno-WIDTH", + "-Wno-STMTDLY", + "--trace", + "-O2", + "--top-module", topModule, + "+define+TOP_TYPE=V" + dutFile, + s"+define+PRINTF_COND=!$topModule.reset", + "-CFLAGS", + s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""", + "-Mdir", dir.toString, + "--exe", cppHarness.toString) + System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex + command + } + + def cppToExe(prefix: String, dir: File): ProcessBuilder = + Seq("make", "-C", dir.toString, "-j", "-f", s"V${prefix}.mk", s"V${prefix}") + + def executeExpectingFailure( + prefix: String, + dir: File, + assertionMsg: String = "Assertion failed"): Boolean = { + var triggered = false + val e = Process(s"./V${prefix}", dir) ! + ProcessLogger(line => { + triggered = triggered || line.contains(assertionMsg) + System.out.println(line) // scalastyle:ignore regex + }) + triggered + } + + def executeExpectingSuccess(prefix: String, dir: File): Boolean = { + !executeExpectingFailure(prefix, dir) + } +} + +object Driver extends BackendCompilationUtilities { + + /** Elaborates the Module specified in the gen function into a Circuit + * + * @param gen a function that creates a Module hierarchy + * @return the resulting Chisel IR in the form of a Circuit (TODO: Should be FIRRTL IR) + */ + def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen())) + + def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen)) + + def dumpFirrtl(ir: Circuit, optName: Option[File]): File = { + val f = optName.getOrElse(new File(ir.name + ".fir")) + val w = new FileWriter(f) + w.write(Emitter.emit(ir)) + w.close() + f + } + + private var target_dir: Option[String] = None + def parseArgs(args: Array[String]): Unit = { + for (i <- 0 until args.size) { + if (args(i) == "--targetDir") { + target_dir = Some(args(i + 1)) + } + } + } + + def targetDir(): String = { target_dir getOrElse new File(".").getCanonicalPath } +} diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala new file mode 100644 index 00000000..56088562 --- /dev/null +++ b/src/main/scala/chisel3/compatibility.scala @@ -0,0 +1,150 @@ +// See LICENSE for license details. + +// Allows legacy users to continue using Chisel (capital C) package name while +// moving to the more standard package naming convention chisel (lowercase c). + +package object Chisel { + type Direction = chisel.core.Direction + val INPUT = chisel.core.INPUT + val OUTPUT = chisel.core.OUTPUT + val NO_DIR = chisel.core.NO_DIR + + type Flipped = chisel.core.Flipped + type Data = chisel.core.Data + val Wire = chisel.core.Wire + val Clock = chisel.core.Clock + type Clock = chisel.core.Clock + + type Aggregate = chisel.core.Aggregate + val Vec = chisel.core.Vec + type Vec[T <: Data] = chisel.core.Vec[T] + type VecLike[T <: Data] = chisel.core.VecLike[T] + type Bundle = chisel.core.Bundle + + val assert = chisel.core.assert + + type Element = chisel.core.Element + type Bits = chisel.core.Bits + val Bits = chisel.core.Bits + type Num[T <: Data] = chisel.core.Num[T] + type UInt = chisel.core.UInt + val UInt = chisel.core.UInt + type SInt = chisel.core.SInt + val SInt = chisel.core.SInt + type Bool = chisel.core.Bool + val Bool = chisel.core.Bool + val Mux = chisel.core.Mux + + type BlackBox = chisel.core.BlackBox + + val Mem = chisel.core.Mem + type MemBase[T <: Data] = chisel.core.MemBase[T] + type Mem[T <: Data] = chisel.core.Mem[T] + val SeqMem = chisel.core.SeqMem + type SeqMem[T <: Data] = chisel.core.SeqMem[T] + + val Module = chisel.core.Module + type Module = chisel.core.Module + + val printf = chisel.core.printf + + val Reg = chisel.core.Reg + + val when = chisel.core.when + type WhenContext = chisel.core.WhenContext + + + type BackendCompilationUtilities = chisel.BackendCompilationUtilities + val Driver = chisel.Driver + type FileSystemUtilities = chisel.compatibility.FileSystemUtilities + val ImplicitConversions = chisel.util.ImplicitConversions + val chiselMain = chisel.compatibility.chiselMain + val throwException = chisel.compatibility.throwException + val debug = chisel.compatibility.debug + + object testers { + type BasicTester = chisel.testers.BasicTester + val TesterDriver = chisel.testers.TesterDriver + } + + + val log2Up = chisel.util.log2Up + val log2Ceil = chisel.util.log2Ceil + val log2Down = chisel.util.log2Down + val log2Floor = chisel.util.log2Floor + val isPow2 = chisel.util.isPow2 + + val BitPat = chisel.util.BitPat + type BitPat = chisel.util.BitPat + + type ArbiterIO[T <: Data] = chisel.util.ArbiterIO[T] + type LockingArbiterLike[T <: Data] = chisel.util.LockingArbiterLike[T] + type LockingRRArbiter[T <: Data] = chisel.util.LockingRRArbiter[T] + type LockingArbiter[T <: Data] = chisel.util.LockingArbiter[T] + type RRArbiter[T <: Data] = chisel.util.RRArbiter[T] + type Arbiter[T <: Data] = chisel.util.Arbiter[T] + + val FillInterleaved = chisel.util.FillInterleaved + val PopCount = chisel.util.PopCount + val Fill = chisel.util.Fill + val Reverse = chisel.util.Reverse + + val Cat = chisel.util.Cat + + val Log2 = chisel.util.Log2 + + val unless = chisel.util.unless + type SwitchContext[T <: Bits] = chisel.util.SwitchContext[T] + val is = chisel.util.is + val switch = chisel.util.switch + + type Counter = chisel.util.Counter + val Counter = chisel.util.Counter + + type DecoupledIO[+T <: Data] = chisel.util.DecoupledIO[T] + val Decoupled = chisel.util.Decoupled + type EnqIO[T <: Data] = chisel.util.EnqIO[T] + type DeqIO[T <: Data] = chisel.util.DeqIO[T] + type DecoupledIOC[+T <: Data] = chisel.util.DecoupledIOC[T] + type QueueIO[T <: Data] = chisel.util.QueueIO[T] + type Queue[T <: Data] = chisel.util.Queue[T] + val Queue = chisel.util.Queue + + val Enum = chisel.util.Enum + + val LFSR16 = chisel.util.LFSR16 + + val ListLookup = chisel.util.ListLookup + val Lookup = chisel.util.Lookup + + val Mux1H = chisel.util.Mux1H + val PriorityMux = chisel.util.PriorityMux + val MuxLookup = chisel.util.MuxLookup + val MuxCase = chisel.util.MuxCase + + val OHToUInt = chisel.util.OHToUInt + val PriorityEncoder = chisel.util.PriorityEncoder + val UIntToOH = chisel.util.UIntToOH + val PriorityEncoderOH = chisel.util.PriorityEncoderOH + + val RegNext = chisel.util.RegNext + val RegInit = chisel.util.RegInit + val RegEnable = chisel.util.RegEnable + val ShiftRegister = chisel.util.ShiftRegister + + type ValidIO[+T <: Data] = chisel.util.ValidIO[T] + val Valid = chisel.util.Valid + val Pipe = chisel.util.Pipe + type Pipe[T <: Data] = chisel.util.Pipe[T] + + + import chisel.internal.firrtl.Width + implicit def fromBigIntToLiteral(x: BigInt): chisel.fromBigIntToLiteral = + new chisel.fromBigIntToLiteral(x) + implicit def fromIntToLiteral(x: Int): chisel.fromIntToLiteral= + new chisel.fromIntToLiteral(x) + implicit def fromStringToLiteral(x: String): chisel.fromStringToLiteral= + new chisel.fromStringToLiteral(x) + implicit def fromBooleanToLiteral(x: Boolean): chisel.fromBooleanToLiteral= + new chisel.fromBooleanToLiteral(x) +} diff --git a/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala new file mode 100644 index 00000000..d12e627d --- /dev/null +++ b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala @@ -0,0 +1,12 @@ +// See LICENSE for license details. + +package chisel.compatibility + +import chisel._ + +@deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0") +trait FileSystemUtilities { + def createOutputFile(name: String): java.io.FileWriter = { + new java.io.FileWriter(Driver.targetDir + "/" + name) + } +} diff --git a/src/main/scala/chisel3/compatibility/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala new file mode 100644 index 00000000..9072bfcf --- /dev/null +++ b/src/main/scala/chisel3/compatibility/Main.scala @@ -0,0 +1,19 @@ +// See LICENSE for license details. + +package chisel.compatibility + +import java.io.File + +import chisel._ + +@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain { + def apply[T <: Module](args: Array[String], gen: () => T): Unit = + Predef.assert(false, "No more chiselMain in Chisel3") + + def run[T <: Module] (args: Array[String], gen: () => T): Unit = { + val circuit = Driver.elaborate(gen) + Driver.parseArgs(args) + val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir") + Driver.dumpFirrtl(circuit, Option(output_file)) + } +} diff --git a/src/main/scala/chisel3/compatibility/debug.scala b/src/main/scala/chisel3/compatibility/debug.scala new file mode 100644 index 00000000..8850c76b --- /dev/null +++ b/src/main/scala/chisel3/compatibility/debug.scala @@ -0,0 +1,8 @@ +package chisel.compatibility + +import chisel.core._ + +@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3") +object debug { // scalastyle:ignore object.name + def apply (arg: Data): Data = arg +} diff --git a/src/main/scala/chisel3/compatibility/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala new file mode 100644 index 00000000..3b9fd06e --- /dev/null +++ b/src/main/scala/chisel3/compatibility/throwException.scala @@ -0,0 +1,14 @@ +// See LICENSE for license details. + +package chisel.compatibility + +import chisel._ + +@deprecated("throwException doesn't exist in Chisel3", "3.0.0") +@throws(classOf[Exception]) +object throwException { + def apply(s: String, t: Throwable = null) = { + val xcpt = new Exception(s, t) + throw xcpt + } +} diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala new file mode 100644 index 00000000..e48eb226 --- /dev/null +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -0,0 +1,112 @@ +// See LICENSE for license details. + +package chisel.internal.firrtl +import chisel._ +import chisel.internal.sourceinfo.{NoSourceInfo, SourceLine} + +private[chisel] object Emitter { + def emit(circuit: Circuit): String = new Emitter(circuit).toString +} + +private class Emitter(circuit: Circuit) { + override def toString: String = res.toString + + private def emitPort(e: Port): String = + s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}" + private def emit(e: Command, ctx: Component): String = { + val firrtlLine = e match { + case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})" + case e: DefWire => s"wire ${e.name} : ${e.id.toType}" + case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}" + case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" + case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]" + case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]" + case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" + case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" + case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" + case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})" + case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})""" + case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid" + case e: DefInstance => { + val modName = moduleMap.get(e.id.name).get + s"inst ${e.name} of $modName" + } + + case w: WhenBegin => + indent() + s"when ${w.pred.fullName(ctx)} :" + case _: WhenEnd => + unindent() + s"skip" + } + e.sourceInfo match { + case SourceLine(filename, line, col) => s"${firrtlLine} @[${filename} ${line}:${col}] " + case _: NoSourceInfo => firrtlLine + } + } + + // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already. + private val defnMap = collection.mutable.HashMap[String, String]() + // Map of Component name to FIRRTL id. + private val moduleMap = collection.mutable.HashMap[String, String]() + + /** Generates the FIRRTL module definition with a specified name. + */ + private def moduleDefn(m: Component, name: String): String = { + val body = new StringBuilder + m.id match { + case _: BlackBox => body ++= newline + s"extmodule $name : " + case _: Module => body ++= newline + s"module $name : " + } + withIndent { + for (p <- m.ports) + body ++= newline + emitPort(p) + body ++= newline + + m.id match { + case _: BlackBox => + // TODO: BlackBoxes should be empty, but funkiness in Module() means + // it's not for now. Eventually, this should assert out. + case _: Module => for (cmd <- m.commands) { + body ++= newline + emit(cmd, m) + } + } + body ++= newline + } + body.toString() + } + + /** Returns the FIRRTL declaration and body of a module, or nothing if it's a + * duplicate of something already emitted (on the basis of simple string + * matching). + */ + private def emit(m: Component): String = { + // Generate the body. + val moduleName = m.id.getClass.getName.split('.').last + val defn = moduleDefn(m, moduleName) + + defnMap get defn match { + case Some(deduplicatedName) => + moduleMap(m.name) = deduplicatedName + "" + case None => + require(!(moduleMap contains m.name), + "emitting module with same name but different contents") + + moduleMap(m.name) = m.name + defnMap(defn) = m.name + + moduleDefn(m, m.name) + } + } + + private var indentLevel = 0 + private def newline = "\n" + (" " * indentLevel) + private def indent(): Unit = indentLevel += 1 + private def unindent() { require(indentLevel > 0); indentLevel -= 1 } + private def withIndent(f: => Unit) { indent(); f; unindent() } + + private val res = new StringBuilder(s"circuit ${circuit.name} : ") + withIndent { circuit.components.foreach(c => res ++= emit(c)) } + res ++= newline +} diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala new file mode 100644 index 00000000..f7ed6b13 --- /dev/null +++ b/src/main/scala/chisel3/package.scala @@ -0,0 +1,82 @@ +package object chisel { + import scala.language.experimental.macros + + import internal.firrtl.Width + import internal.sourceinfo.{SourceInfo, SourceInfoTransform} + import util.BitPat + + + type Direction = chisel.core.Direction + val INPUT = chisel.core.INPUT + val OUTPUT = chisel.core.OUTPUT + val NO_DIR = chisel.core.NO_DIR + type Flipped = chisel.core.Flipped + type Data = chisel.core.Data + val Wire = chisel.core.Wire + val Clock = chisel.core.Clock + type Clock = chisel.core.Clock + + type Aggregate = chisel.core.Aggregate + val Vec = chisel.core.Vec + type Vec[T <: Data] = chisel.core.Vec[T] + type VecLike[T <: Data] = chisel.core.VecLike[T] + type Bundle = chisel.core.Bundle + + val assert = chisel.core.assert + + type Element = chisel.core.Element + type Bits = chisel.core.Bits + val Bits = chisel.core.Bits + type Num[T <: Data] = chisel.core.Num[T] + type UInt = chisel.core.UInt + val UInt = chisel.core.UInt + type SInt = chisel.core.SInt + val SInt = chisel.core.SInt + type Bool = chisel.core.Bool + val Bool = chisel.core.Bool + val Mux = chisel.core.Mux + + type BlackBox = chisel.core.BlackBox + + val Mem = chisel.core.Mem + type MemBase[T <: Data] = chisel.core.MemBase[T] + type Mem[T <: Data] = chisel.core.Mem[T] + val SeqMem = chisel.core.SeqMem + type SeqMem[T <: Data] = chisel.core.SeqMem[T] + + val Module = chisel.core.Module + type Module = chisel.core.Module + + val printf = chisel.core.printf + + val Reg = chisel.core.Reg + + val when = chisel.core.when + type WhenContext = chisel.core.WhenContext + + + implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { + def U: UInt = UInt(x, Width()) + def S: SInt = SInt(x, Width()) + } + implicit class fromIntToLiteral(val x: Int) extends AnyVal { + def U: UInt = UInt(BigInt(x), Width()) + def S: SInt = SInt(BigInt(x), Width()) + } + implicit class fromStringToLiteral(val x: String) extends AnyVal { + def U: UInt = UInt(x) + } + implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { + def B: Bool = Bool(x) + } + + implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal { + final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg + final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg + final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg + + def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x + def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x + def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x + } +} diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala new file mode 100644 index 00000000..36ff7c52 --- /dev/null +++ b/src/main/scala/chisel3/testers/BasicTester.scala @@ -0,0 +1,38 @@ +// See LICENSE for license details. + +package chisel.testers +import chisel._ + +import scala.language.experimental.macros + +import internal._ +import internal.Builder.pushCommand +import internal.firrtl._ +import internal.sourceinfo.SourceInfo + +class BasicTester extends Module { + // The testbench has no IOs, rather it should communicate using printf, assert, and stop. + val io = new Bundle() + + def popCount(n: Long): Int = n.toBinaryString.count(_=='1') + + /** Ends the test reporting success. + * + * Does not fire when in reset (defined as the encapsulating Module's + * reset). If your definition of reset is not the encapsulating Module's + * reset, you will need to gate this externally. + */ + def stop()(implicit sourceInfo: SourceInfo) { + // TODO: rewrite this using library-style SourceInfo passing. + when (!reset) { + pushCommand(Stop(sourceInfo, Node(clock), 0)) + } + } + + /** The finish method provides a hook that subclasses of BasicTester can use to + * alter a circuit after their constructor has been called. + * For example, a specialized tester subclassing BasicTester could override finish in order to + * add flow control logic for a decoupled io port of a device under test + */ + def finish(): Unit = {} +} diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala new file mode 100644 index 00000000..5c0275e0 --- /dev/null +++ b/src/main/scala/chisel3/testers/TesterDriver.scala @@ -0,0 +1,69 @@ +// See LICENSE for license details. + +package chisel.testers + +import chisel._ +import scala.io.Source +import scala.sys.process._ +import java.io._ + +object TesterDriver extends BackendCompilationUtilities { + /** Copy the contents of a resource to a destination file. + */ + def copyResourceToFile(name: String, file: File) { + val in = getClass().getResourceAsStream(name) + if (in == null) { + throw new FileNotFoundException(s"Resource '$name'") + } + val out = new FileOutputStream(file) + Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write) + out.close() + } + + /** For use with modules that should successfully be elaborated by the + * frontend, and which can be turned into executables with assertions. */ + def execute(t: () => BasicTester, additionalVResources: Seq[String] = Seq()): Boolean = { + // Invoke the chisel compiler to get the circuit's IR + val circuit = Driver.elaborate(finishWrapper(t)) + + // Set up a bunch of file handlers based on a random temp filename, + // plus the quirks of Verilator's naming conventions + val target = circuit.name + + val path = createTempDirectory(target) + val fname = new File(path, target) + + // For now, dump the IR out to a file + Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir"))) + + // Copy CPP harness and other Verilog sources from resources into files + val cppHarness = new File(path, "top.cpp") + copyResourceToFile("/top.cpp", cppHarness) + val additionalVFiles = additionalVResources.map((name: String) => { + val mangledResourceName = name.replace("/", "_") + val out = new File(path, mangledResourceName) + copyResourceToFile(name, out) + out + }) + + // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe + if ((firrtlToVerilog(target, path) #&& + verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& + cppToExe(target, path)).! == 0) { + executeExpectingSuccess(target, path) + } else { + false + } + } + /** + * Calls the finish method of an BasicTester or a class that extends it. + * The finish method is a hook for code that augments the circuit built in the constructor. + */ + def finishWrapper(test: () => BasicTester): () => BasicTester = { + () => { + val tester = test() + tester.finish() + tester + } + } +} diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala new file mode 100644 index 00000000..3723f2a9 --- /dev/null +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -0,0 +1,119 @@ +// See LICENSE for license details. + +/** Arbiters in all shapes and sizes. + */ + +package chisel.util + +import chisel._ + +/** An I/O bundle for the Arbiter */ +class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { + val in = Vec(n, Decoupled(gen)).flip + val out = Decoupled(gen) + val chosen = UInt(OUTPUT, log2Up(n)) +} + +/** Arbiter Control determining which producer has access */ +private object ArbiterCtrl +{ + def apply(request: Seq[Bool]): Seq[Bool] = request.length match { + case 0 => Seq() + case 1 => Seq(Bool(true)) + case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_) + } +} + +abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool]) extends Module { + def grant: Seq[Bool] + def choice: UInt + val io = new ArbiterIO(gen, n) + + io.chosen := choice + io.out.valid := io.in(io.chosen).valid + io.out.bits := io.in(io.chosen).bits + + if (count > 1) { + val lockCount = Counter(count) + val lockIdx = Reg(UInt()) + val locked = lockCount.value =/= UInt(0) + val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true)) + + when (io.out.fire() && wantsLock) { + lockIdx := io.chosen + lockCount.inc() + } + + when (locked) { io.chosen := lockIdx } + for ((in, (g, i)) <- io.in zip grant.zipWithIndex) + in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready + } else { + for ((in, g) <- io.in zip grant) + in.ready := g && io.out.ready + } +} + +class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) + extends LockingArbiterLike[T](gen, n, count, needsLock) { + lazy val lastGrant = RegEnable(io.chosen, io.out.fire()) + lazy val grantMask = (0 until n).map(UInt(_) > lastGrant) + lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g } + + override def grant: Seq[Bool] = { + val ctrl = ArbiterCtrl((0 until n).map(i => validMask(i)) ++ io.in.map(_.valid)) + (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n)) + } + + override lazy val choice = Wire(init=UInt(n-1)) + for (i <- n-2 to 0 by -1) + when (io.in(i).valid) { choice := UInt(i) } + for (i <- n-1 to 1 by -1) + when (validMask(i)) { choice := UInt(i) } +} + +class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) + extends LockingArbiterLike[T](gen, n, count, needsLock) { + def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid)) + + override lazy val choice = Wire(init=UInt(n-1)) + for (i <- n-2 to 0 by -1) + when (io.in(i).valid) { choice := UInt(i) } +} + +/** Hardware module that is used to sequence n producers into 1 consumer. + Producers are chosen in round robin order. + + Example usage: + val arb = new RRArbiter(2, UInt()) + arb.io.in(0) <> producer0.io.out + arb.io.in(1) <> producer1.io.out + consumer.io.in <> arb.io.out + */ +class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1) + +/** Hardware module that is used to sequence n producers into 1 consumer. + Priority is given to lower producer + + Example usage: + val arb = Module(new Arbiter(2, UInt())) + arb.io.in(0) <> producer0.io.out + arb.io.in(1) <> producer1.io.out + consumer.io.in <> arb.io.out + */ +class Arbiter[T <: Data](gen: T, n: Int) extends Module { + val io = new ArbiterIO(gen, n) + + io.chosen := UInt(n-1) + io.out.bits := io.in(n-1).bits + for (i <- n-2 to 0 by -1) { + when (io.in(i).valid) { + io.chosen := UInt(i) + io.out.bits := io.in(i).bits + } + } + + val grant = ArbiterCtrl(io.in.map(_.valid)) + for ((in, g) <- io.in zip grant) + in.ready := g && io.out.ready + io.out.valid := !grant.last || io.in.last.valid +} diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala new file mode 100644 index 00000000..13bbe1b0 --- /dev/null +++ b/src/main/scala/chisel3/util/BitPat.scala @@ -0,0 +1,89 @@ +// See LICENSE for license details. + +package chisel.util + +import scala.language.experimental.macros + +import chisel._ +import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform} + +object BitPat { + /** Parses a bit pattern string into (bits, mask, width). + * + * @return bits the literal value, with don't cares being 0 + * @return mask the mask bits, with don't cares being 0 and cares being 1 + * @return width the number of bits in the literal, including values and + * don't cares. + */ + private def parse(x: String): (BigInt, BigInt, Int) = { + // Notes: + // While Verilog Xs also handle octal and hex cases, there isn't a + // compelling argument and no one has asked for it. + // If ? parsing is to be exposed, the return API needs further scrutiny + // (especially with things like mask polarity). + require(x.head == 'b', "BitPats must be in binary and be prefixed with 'b'") + var bits = BigInt(0) + var mask = BigInt(0) + for (d <- x.tail) { + if (d != '_') { + require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d) + mask = (mask << 1) + (if (d == '?') 0 else 1) + bits = (bits << 1) + (if (d == '1') 1 else 0) + } + } + (bits, mask, x.length - 1) + } + + /** Creates a [[BitPat]] literal from a string. + * + * @param n the literal value as a string, in binary, prefixed with 'b' + * @note legal characters are '0', '1', and '?', as well as '_' as white + * space (which are ignored) + */ + def apply(n: String): BitPat = { + val (bits, mask, width) = parse(n) + new BitPat(bits, mask, width) + } + + /** Creates a [[BitPat]] of all don't cares of the specified bitwidth. */ + def dontCare(width: Int): BitPat = BitPat("b" + ("?" * width)) + + @deprecated("Use BitPat.dontCare", "chisel3") + def DC(width: Int): BitPat = dontCare(width) // scalastyle:ignore method.name + + /** Allows BitPats to be used where a UInt is expected. + * + * @note the BitPat must not have don't care bits (will error out otherwise) + */ + def bitPatToUInt(x: BitPat): UInt = { + require(x.mask == (BigInt(1) << x.getWidth) - 1) + UInt(x.value, x.getWidth) + } + + /** Allows UInts to be used where a BitPat is expected, useful for when an + * interface is defined with BitPats but not all cases need the partial + * matching capability. + * + * @note the UInt must be a literal + */ + def apply(x: UInt): BitPat = { + require(x.isLit) + BitPat("b" + x.litValue.toString(2)) + } +} + +// TODO: Break out of Core? (this doesn't involve FIRRTL generation) +/** Bit patterns are literals with masks, used to represent values with don't + * cares. Equality comparisons will ignore don't care bits (for example, + * BitPat(0b10?1) === UInt(0b1001) and UInt(0b1011)). + */ +sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) { + def getWidth: Int = width + def === (that: UInt): Bool = macro SourceInfoTransform.thatArg + def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg + def != (that: UInt): Bool = macro SourceInfoTransform.thatArg + + def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask)) + def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that) + def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that +} diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala new file mode 100644 index 00000000..d7d62ea3 --- /dev/null +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -0,0 +1,74 @@ +// See LICENSE for license details. + +/** Miscellaneous circuit generators operating on bits. + */ + +package chisel.util + +import chisel._ +import chisel.core.SeqUtils + +object FillInterleaved +{ + def apply(n: Int, in: UInt): UInt = apply(n, in.toBools) + def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits +} + +/** Returns the number of bits set (i.e value is 1) in the input signal. + */ +object PopCount +{ + def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq) + def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_))) +} + +/** Fill fans out a UInt to multiple copies */ +object Fill { + /** Fan out x n times */ + def apply(n: Int, x: UInt): UInt = { + n match { + case 0 => UInt(width=0) + case 1 => x + case y if n > 1 => + val p2 = Array.ofDim[UInt](log2Up(n + 1)) + p2(0) = x + for (i <- 1 until p2.length) + p2(i) = Cat(p2(i-1), p2(i-1)) + Cat((0 until log2Up(y + 1)).filter(i => (y & (1 << i)) != 0).map(p2(_))) + case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.") + } + } + /** Fan out x n times */ + def apply(n: Int, x: Bool): UInt = + if (n > 1) { + UInt(0,n) - x + } else { + apply(n, x: UInt) + } +} + +/** Litte/big bit endian convertion: reverse the order of the bits in a UInt. +*/ +object Reverse +{ + private def doit(in: UInt, length: Int): UInt = { + if (length == 1) { + in + } else if (isPow2(length) && length >= 8 && length <= 64) { + // This esoterica improves simulation performance + var res = in + var shift = length >> 1 + var mask = UInt((BigInt(1) << length) - 1, length) + do { + mask = mask ^ (mask(length-shift-1,0) << shift) + res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask) + shift = shift >> 1 + } while (shift > 0) + res + } else { + val half = (1 << log2Up(length))/2 + Cat(doit(in(half-1,0), half), doit(in(length-1,half), length-half)) + } + } + def apply(in: UInt): UInt = doit(in, in.getWidth) +} diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala new file mode 100644 index 00000000..b47da706 --- /dev/null +++ b/src/main/scala/chisel3/util/Cat.scala @@ -0,0 +1,21 @@ +// See LICENSE for license details. + +package chisel.util + +import chisel._ +import chisel.core.SeqUtils + +object Cat { + /** Combine data elements together + * @param a Data to combine with + * @param r any number of other Data elements to be combined in order + * @return A UInt which is all of the bits combined together + */ + def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList) + + /** Combine data elements together + * @param r any number of other Data elements to be combined in order + * @return A UInt which is all of the bits combined together + */ + def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse) +} diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala new file mode 100644 index 00000000..c3b94fdb --- /dev/null +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -0,0 +1,28 @@ +// See LICENSE for license details. + +/** Circuit-land math operations. + */ + +package chisel.util + +import chisel._ + +/** Compute Log2 with truncation of a UInt in hardware using a Mux Tree + * An alternative interpretation is it computes the minimum number of bits needed to represent x + * @example + * {{{ data_out := Log2(data_in) }}} + * @note Truncation is used so Log2(UInt(12412)) = 13*/ +object Log2 { + /** Compute the Log2 on the least significant n bits of x */ + def apply(x: Bits, width: Int): UInt = { + if (width < 2) { + UInt(0) + } else if (width == 2) { + x(1) + } else { + Mux(x(width-1), UInt(width-1), apply(x, width-1)) + } + } + + def apply(x: Bits): UInt = apply(x, x.getWidth) +} diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala new file mode 100644 index 00000000..01c12799 --- /dev/null +++ b/src/main/scala/chisel3/util/Conditional.scala @@ -0,0 +1,73 @@ +// See LICENSE for license details. + +/** Conditional blocks. + */ + +package chisel.util + +import scala.language.reflectiveCalls +import scala.language.experimental.macros +import scala.reflect.runtime.universe._ +import scala.reflect.macros.blackbox._ + +import chisel._ + +/** This is identical to [[Chisel.when when]] with the condition inverted */ +object unless { // scalastyle:ignore object.name + def apply(c: Bool)(block: => Unit) { + when (!c) { block } + } +} + +class SwitchContext[T <: Bits](cond: T) { + def is(v: Iterable[T])(block: => Unit) { + if (!v.isEmpty) when (v.map(_.asUInt === cond.asUInt).reduce(_||_)) { block } + } + def is(v: T)(block: => Unit) { is(Seq(v))(block) } + def is(v: T, vr: T*)(block: => Unit) { is(v :: vr.toList)(block) } +} + +/** An object for separate cases in [[Chisel.switch switch]] + * It is equivalent to a [[Chisel.when$ when]] block comparing to the condition + * Use outside of a switch statement is illegal */ +object is { // scalastyle:ignore object.name + // Begin deprecation of non-type-parameterized is statements. + def apply(v: Iterable[Bits])(block: => Unit) { + require(false, "The 'is' keyword may not be used outside of a switch.") + } + + def apply(v: Bits)(block: => Unit) { + require(false, "The 'is' keyword may not be used outside of a switch.") + } + + def apply(v: Bits, vr: Bits*)(block: => Unit) { + require(false, "The 'is' keyword may not be used outside of a switch.") + } +} + +/** Conditional logic to form a switch block + * @example + * {{{ ... // default values here + * switch ( myState ) { + * is( state1 ) { + * ... // some logic here + * } + * is( state2 ) { + * ... // some logic here + * } + * } }}}*/ +object switch { // scalastyle:ignore object.name + def apply[T <: Bits](cond: T)(x: => Unit): Unit = macro impl + def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._ + val sc = c.universe.internal.reificationSupport.freshTermName("sc") + def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match { + // TODO: remove when Chisel compatibility package is removed + case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") + case q"chisel.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") + case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.") + } + val q"..$body" = x + val ises = body.flatMap(extractIsStatement(_)) + q"""{ val $sc = new SwitchContext($cond); ..$ises }""" + } +} diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala new file mode 100644 index 00000000..1c0b0203 --- /dev/null +++ b/src/main/scala/chisel3/util/Counter.scala @@ -0,0 +1,46 @@ +// See LICENSE for license details. + +package chisel.util + +import chisel._ + +/** A counter module + * @param n number of counts before the counter resets (or one more than the + * maximum output value of the counter), need not be a power of two + */ +class Counter(val n: Int) { + require(n >= 0) + val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0) + /** Increment the counter, returning whether the counter currently is at the + * maximum and will wrap. The incremented value is registered and will be + * visible on the next cycle. + */ + def inc(): Bool = { + if (n > 1) { + val wrap = value === UInt(n-1) + value := value + UInt(1) + if (!isPow2(n)) { + when (wrap) { value := UInt(0) } + } + wrap + } else { + Bool(true) + } + } +} + +/** Counter Object + * Example Usage: + * {{{ val countOn = Bool(true) // increment counter every clock cycle + * val myCounter = Counter(countOn, n) + * when ( myCounter.value === UInt(3) ) { ... } }}}*/ +object Counter +{ + def apply(n: Int): Counter = new Counter(n) + def apply(cond: Bool, n: Int): (UInt, Bool) = { + val c = new Counter(n) + var wrap: Bool = null + when (cond) { wrap = c.inc() } + (c.value, cond && wrap) + } +} diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala new file mode 100644 index 00000000..89b0e39d --- /dev/null +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -0,0 +1,185 @@ +// See LICENSE for license details. + +/** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them. + */ + +package chisel.util + +import chisel._ + +/** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/ +class DecoupledIO[+T <: Data](gen: T) extends Bundle +{ + val ready = Bool(INPUT) + val valid = Bool(OUTPUT) + val bits = gen.cloneType.asOutput + def fire(dummy: Int = 0): Bool = ready && valid + override def cloneType: this.type = new DecoupledIO(gen).asInstanceOf[this.type] +} + +/** Adds a ready-valid handshaking protocol to any interface. + * The standard used is that the consumer uses the flipped interface. + */ +object Decoupled { + def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen) +} + +/** An I/O bundle for enqueuing data with valid/ready handshaking + * Initialization must be handled, if necessary, by the parent circuit + */ +class EnqIO[T <: Data](gen: T) extends DecoupledIO(gen) +{ + /** push dat onto the output bits of this interface to let the consumer know it has happened. + * @param dat the values to assign to bits. + * @return dat. + */ + def enq(dat: T): T = { valid := Bool(true); bits := dat; dat } + + /** Initialize this Bundle. Valid is set to false, and all bits are set to zero. + * NOTE: This method of initialization is still being discussed and could change in the + * future. + */ + def init(): Unit = { + valid := Bool(false) + for (io <- bits.flatten) + io := UInt(0) + } + override def cloneType: this.type = { new EnqIO(gen).asInstanceOf[this.type]; } +} + +/** An I/O bundle for dequeuing data with valid/ready handshaking. + * Initialization must be handled, if necessary, by the parent circuit + */ +class DeqIO[T <: Data](gen: T) extends DecoupledIO(gen) with Flipped +{ + /** Assert ready on this port and return the associated data bits. + * This is typically used when valid has been asserted by the producer side. + * @param b ignored + * @return the data for this device, + */ + def deq(b: Boolean = false): T = { ready := Bool(true); bits } + + /** Initialize this Bundle. + * NOTE: This method of initialization is still being discussed and could change in the + * future. + */ + def init(): Unit = { + ready := Bool(false) + } + override def cloneType: this.type = { new DeqIO(gen).asInstanceOf[this.type]; } +} + +/** An I/O bundle for dequeuing data with valid/ready handshaking */ +class DecoupledIOC[+T <: Data](gen: T) extends Bundle +{ + val ready = Bool(INPUT) + val valid = Bool(OUTPUT) + val bits = gen.cloneType.asOutput +} + +/** An I/O Bundle for Queues + * @param gen The type of data to queue + * @param entries The max number of entries in the queue */ +class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle +{ + /** I/O to enqueue data, is [[Chisel.DecoupledIO]] flipped */ + val enq = Decoupled(gen.cloneType).flip() + /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/ + val deq = Decoupled(gen.cloneType) + /** The current amount of data in the queue */ + val count = UInt(OUTPUT, log2Up(entries + 1)) +} + +/** A hardware module implementing a Queue + * @param gen The type of data to queue + * @param entries The max number of entries in the queue + * @param pipe True if a single entry queue can run at full throughput (like a pipeline). The ''ready'' signals are + * combinationally coupled. + * @param flow True if the inputs can be consumed on the same cycle (the inputs "flow" through the queue immediately). + * The ''valid'' signals are coupled. + * + * Example usage: + * {{{ val q = new Queue(UInt(), 16) + * q.io.enq <> producer.io.out + * consumer.io.in <> q.io.deq }}} + */ +class Queue[T <: Data](gen: T, val entries: Int, + pipe: Boolean = false, + flow: Boolean = false, + override_reset: Option[Bool] = None) +extends Module(override_reset=override_reset) { + def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) = + this(gen, entries, pipe, flow, Some(_reset)) + + val io = new QueueIO(gen, entries) + + val ram = Mem(entries, gen) + val enq_ptr = Counter(entries) + val deq_ptr = Counter(entries) + val maybe_full = Reg(init=Bool(false)) + + val ptr_match = enq_ptr.value === deq_ptr.value + val empty = ptr_match && !maybe_full + val full = ptr_match && maybe_full + val do_enq = Wire(init=io.enq.fire()) + val do_deq = Wire(init=io.deq.fire()) + + when (do_enq) { + ram(enq_ptr.value) := io.enq.bits + enq_ptr.inc() + } + when (do_deq) { + deq_ptr.inc() + } + when (do_enq != do_deq) { + maybe_full := do_enq + } + + io.deq.valid := !empty + io.enq.ready := !full + io.deq.bits := ram(deq_ptr.value) + + if (flow) { + when (io.enq.valid) { io.deq.valid := Bool(true) } + when (empty) { + io.deq.bits := io.enq.bits + do_deq := Bool(false) + when (io.deq.ready) { do_enq := Bool(false) } + } + } + + if (pipe) { + when (io.deq.ready) { io.enq.ready := Bool(true) } + } + + val ptr_diff = enq_ptr.value - deq_ptr.value + if (isPow2(entries)) { + io.count := Cat(maybe_full && ptr_match, ptr_diff) + } else { + io.count := Mux(ptr_match, + Mux(maybe_full, + UInt(entries), UInt(0)), + Mux(deq_ptr.value > enq_ptr.value, + UInt(entries) + ptr_diff, ptr_diff)) + } +} + +/** Generic hardware queue. Required parameter entries controls + the depth of the queues. The width of the queue is determined + from the inputs. + + Example usage: + {{{ val q = Queue(Decoupled(UInt()), 16) + q.io.enq <> producer.io.out + consumer.io.in <> q.io.deq }}} + */ +object Queue +{ + def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false): DecoupledIO[T] = { + val q = Module(new Queue(enq.bits.cloneType, entries, pipe)) + q.io.enq.valid := enq.valid // not using <> so that override is allowed + q.io.enq.bits := enq.bits + enq.ready := q.io.enq.ready + TransitName(q.io.deq, q) + } +} diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala new file mode 100644 index 00000000..8babcd23 --- /dev/null +++ b/src/main/scala/chisel3/util/Enum.scala @@ -0,0 +1,23 @@ +// See LICENSE for license details. + +/** Enum generators, allowing circuit constants to have more meaningful names. + */ + +package chisel.util + +import chisel._ + +object Enum { + /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */ + private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] = + (0 until n).map(x => nodeType.fromInt(x, log2Up(n))) + + /** create n enum values of given type */ + def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList + + /** create enum values of given type and names */ + def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap + + /** create enum values of given type and names */ + def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap +} diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala new file mode 100644 index 00000000..846c0cbd --- /dev/null +++ b/src/main/scala/chisel3/util/ImplicitConversions.scala @@ -0,0 +1,10 @@ +// See LICENSE for license details. + +package chisel.util + +import chisel._ + +object ImplicitConversions { + implicit def intToUInt(x: Int): UInt = UInt(x) + implicit def booleanToBool(x: Boolean): Bool = Bool(x) +} diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala new file mode 100644 index 00000000..f70630bf --- /dev/null +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -0,0 +1,24 @@ +// See LICENSE for license details. + +/** LFSRs in all shapes and sizes. + */ + +package chisel.util + +import chisel._ + +// scalastyle:off magic.number +/** linear feedback shift register + */ +object LFSR16 +{ + def apply(increment: Bool = Bool(true)): UInt = + { + val width = 16 + val lfsr = Reg(init=UInt(1, width)) + when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } + lfsr + } +} +// scalastyle:on magic.number + diff --git a/src/main/scala/chisel3/util/Lookup.scala b/src/main/scala/chisel3/util/Lookup.scala new file mode 100644 index 00000000..d32d9aec --- /dev/null +++ b/src/main/scala/chisel3/util/Lookup.scala @@ -0,0 +1,19 @@ +// See LICENSE for license details. + +package chisel.util + +import chisel._ + +object ListLookup { + def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = { + val map = mapping.map(m => (m._1 === addr, m._2)) + default.zipWithIndex map { case (d, i) => + map.foldRight(d)((m, n) => Mux(m._1, m._2(i), n)) + } + } +} + +object Lookup { + def apply[T <: Bits](addr: UInt, default: T, mapping: Seq[(BitPat, T)]): T = + ListLookup(addr, List(default), mapping.map(m => (m._1, List(m._2))).toArray).head +} diff --git a/src/main/scala/chisel3/util/Math.scala b/src/main/scala/chisel3/util/Math.scala new file mode 100644 index 00000000..69464d15 --- /dev/null +++ b/src/main/scala/chisel3/util/Math.scala @@ -0,0 +1,44 @@ +// See LICENSE for license details. + +/** Scala-land math helper functions, like logs. + */ + +package chisel.util + +import chisel._ + +/** Compute the log2 rounded up with min value of 1 */ +object log2Up { + def apply(in: BigInt): Int = { + require(in >= 0) + 1 max (in-1).bitLength + } + def apply(in: Int): Int = apply(BigInt(in)) +} + +/** Compute the log2 rounded up */ +object log2Ceil { + def apply(in: BigInt): Int = { + require(in > 0) + (in-1).bitLength + } + def apply(in: Int): Int = apply(BigInt(in)) +} + +/** Compute the log2 rounded down with min value of 1 */ +object log2Down { + def apply(in: BigInt): Int = log2Up(in) - (if (isPow2(in)) 0 else 1) + def apply(in: Int): Int = apply(BigInt(in)) +} + +/** Compute the log2 rounded down */ +object log2Floor { + def apply(in: BigInt): Int = log2Ceil(in) - (if (isPow2(in)) 0 else 1) + def apply(in: Int): Int = apply(BigInt(in)) +} + +/** Check if an Integer is a power of 2 */ +object isPow2 { + def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0) + def apply(in: Int): Boolean = apply(BigInt(in)) +} diff --git a/src/main/scala/chisel3/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala new file mode 100644 index 00000000..6f074a7e --- /dev/null +++ b/src/main/scala/chisel3/util/Mux.scala @@ -0,0 +1,64 @@ +// See LICENSE for license details. + +/** Mux circuit generators. + */ + +package chisel.util + +import chisel._ +import chisel.core.SeqUtils + +/** Builds a Mux tree out of the input signal vector using a one hot encoded + select signal. Returns the output of the Mux tree. + */ +object Mux1H +{ + def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = + apply(sel zip in) + def apply[T <: Data](in: Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in) + def apply[T <: Data](sel: UInt, in: Seq[T]): T = + apply((0 until in.size).map(sel(_)), in) + def apply(sel: UInt, in: UInt): Bool = (sel & in).orR +} + +/** Builds a Mux tree under the assumption that multiple select signals + can be enabled. Priority is given to the first select signal. + + Returns the output of the Mux tree. + */ +object PriorityMux +{ + def apply[T <: Data](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in) + def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in) + def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in) +} + +/** MuxLookup creates a cascade of n Muxs to search for a key value */ +object MuxLookup { + /** @param key a key to search for + * @param default a default value if nothing is found + * @param mapping a sequence to search of keys and values + * @return the value found or the default if not + */ + def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = { + var res = default + for ((k, v) <- mapping.reverse) + res = Mux(k === key, v, res) + res + } + +} + +/** MuxCase returns the first value that is enabled in a map of values */ +object MuxCase { + /** @param default the default value if none are enabled + * @param mapping a set of data values with associated enables + * @return the first value in mapping that is enabled */ + def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = { + var res = default + for ((t, v) <- mapping.reverse){ + res = Mux(t, v, res) + } + res + } +} diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala new file mode 100644 index 00000000..ef21c65d --- /dev/null +++ b/src/main/scala/chisel3/util/OneHot.scala @@ -0,0 +1,64 @@ +// See LICENSE for license details. + +/** Circuit generators for working with one-hot representations. + */ + +package chisel.util + +import chisel._ + +/** Converts from One Hot Encoding to a UInt indicating which bit is active + * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/ +object OHToUInt { + def apply(in: Seq[Bool]): UInt = apply(Vec(in)) + def apply(in: Vec[Bool]): UInt = apply(in.toBits, in.size) + def apply(in: Bits): UInt = apply(in, in.getWidth) + + def apply(in: Bits, width: Int): UInt = { + if (width <= 2) { + Log2(in, width) + } else { + val mid = 1 << (log2Up(width)-1) + val hi = in(width-1, mid) + val lo = in(mid-1, 0) + Cat(hi.orR, apply(hi | lo, mid)) + } + } +} + +/** @return the bit position of the trailing 1 in the input vector + * with the assumption that multiple bits of the input bit vector can be set + * @example {{{ data_out := PriorityEncoder(data_in) }}} + */ +object PriorityEncoder { + def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_))) + def apply(in: Bits): UInt = apply(in.toBools) +} + +/** Returns the one hot encoding of the input UInt. + */ +object UIntToOH +{ + def apply(in: UInt, width: Int = -1): UInt = + if (width == -1) { + UInt(1) << in + } else { + (UInt(1) << in(log2Up(width)-1,0))(width-1,0) + } +} + +/** Returns a bit vector in which only the least-significant 1 bit in + the input vector, if any, is set. + */ +object PriorityEncoderOH +{ + private def encode(in: Seq[Bool]): UInt = { + val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size)) + PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size)) + } + def apply(in: Seq[Bool]): Seq[Bool] = { + val enc = encode(in) + Seq.tabulate(in.size)(enc(_)) + } + def apply(in: Bits): UInt = encode((0 until in.getWidth).map(i => in(i))) +} diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala new file mode 100644 index 00000000..1b40646d --- /dev/null +++ b/src/main/scala/chisel3/util/Reg.scala @@ -0,0 +1,57 @@ +// See LICENSE for license details. + +/** Variations and helpers for registers. + */ + +package chisel.util + +import chisel._ + +object RegNext { + + def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T]) + + def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init) + +} + +object RegInit { + + def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init) + +} + +/** A register with an Enable signal */ +object RegEnable +{ + def apply[T <: Data](updateData: T, enable: Bool): T = { + val r = Reg(updateData) + when (enable) { r := updateData } + r + } + def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = { + val r = RegInit(resetData) + when (enable) { r := updateData } + r + } +} + +/** Returns the n-cycle delayed version of the input signal. + */ +object ShiftRegister +{ + /** @param in input to delay + * @param n number of cycles to delay + * @param en enable the shift */ + def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = + { + // The order of tests reflects the expected use cases. + if (n == 1) { + RegEnable(in, en) + } else if (n != 0) { + RegNext(apply(in, n-1, en)) + } else { + in + } + } +} diff --git a/src/main/scala/chisel3/util/TransitName.scala b/src/main/scala/chisel3/util/TransitName.scala new file mode 100644 index 00000000..04e1995b --- /dev/null +++ b/src/main/scala/chisel3/util/TransitName.scala @@ -0,0 +1,22 @@ +package chisel.util + +import chisel._ +import internal.HasId + +object TransitName { + // The purpose of this is to allow a library to 'move' a name call to a more + // appropriate place. + // For example, a library factory function may create a module and return + // the io. The only user-exposed field is that given IO, which can't use + // any name supplied by the user. This can add a hook so that the supplied + // name then names the Module. + // See Queue companion object for working example + def apply[T<:HasId](from: T, to: HasId): T = { + from.addPostnameHook((given_name: String) => {to.suggestName(given_name)}) + from + } + def withSuffix[T<:HasId](suffix: String)(from: T, to: HasId): T = { + from.addPostnameHook((given_name: String) => {to.suggestName(given_name+suffix)}) + from + } +} diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala new file mode 100644 index 00000000..56ac9abb --- /dev/null +++ b/src/main/scala/chisel3/util/Valid.scala @@ -0,0 +1,61 @@ +// See LICENSE for license details. + +/** Wrappers for valid interfaces and associated circuit generators using them. + */ + +package chisel.util + +import chisel._ + +/** An I/O Bundle containing data and a signal determining if it is valid */ +class ValidIO[+T <: Data](gen2: T) extends Bundle +{ + val valid = Bool(OUTPUT) + val bits = gen2.cloneType.asOutput + def fire(dummy: Int = 0): Bool = valid + override def cloneType: this.type = new ValidIO(gen2).asInstanceOf[this.type] +} + +/** Adds a valid protocol to any interface. The standard used is + that the consumer uses the flipped interface. +*/ +object Valid { + def apply[T <: Data](gen: T): ValidIO[T] = new ValidIO(gen) +} + +/** A hardware module that delays data coming down the pipeline + by the number of cycles set by the latency parameter. Functionality + is similar to ShiftRegister but this exposes a Pipe interface. + + Example usage: + val pipe = new Pipe(UInt()) + pipe.io.enq <> produce.io.out + consumer.io.in <> pipe.io.deq + */ +object Pipe +{ + def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = { + if (latency == 0) { + val out = Wire(Valid(enqBits)) + out.valid <> enqValid + out.bits <> enqBits + out + } else { + val v = Reg(Bool(), next=enqValid, init=Bool(false)) + val b = RegEnable(enqBits, enqValid) + apply(v, b, latency-1) + } + } + def apply[T <: Data](enqValid: Bool, enqBits: T): ValidIO[T] = apply(enqValid, enqBits, 1) + def apply[T <: Data](enq: ValidIO[T], latency: Int = 1): ValidIO[T] = apply(enq.valid, enq.bits, latency) +} + +class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module +{ + val io = new Bundle { + val enq = Valid(gen).flip + val deq = Valid(gen) + } + + io.deq <> Pipe(io.enq, latency) +} -- cgit v1.2.3 From 3026dd214f3db3308eaf8f876d0fc03f75c577d3 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 20 Jun 2016 11:38:26 -0700 Subject: Rename "package", "import", and explicit references to "chisel3". --- src/main/scala/chisel3/Driver.scala | 2 +- src/main/scala/chisel3/compatibility.scala | 278 ++++++++++----------- .../compatibility/FileSystemUtilities.scala | 4 +- src/main/scala/chisel3/compatibility/Main.scala | 4 +- src/main/scala/chisel3/compatibility/debug.scala | 4 +- .../chisel3/compatibility/throwException.scala | 4 +- .../scala/chisel3/internal/firrtl/Emitter.scala | 8 +- src/main/scala/chisel3/package.scala | 96 +++---- src/main/scala/chisel3/testers/BasicTester.scala | 4 +- src/main/scala/chisel3/testers/TesterDriver.scala | 4 +- src/main/scala/chisel3/util/Arbiter.scala | 4 +- src/main/scala/chisel3/util/BitPat.scala | 6 +- src/main/scala/chisel3/util/Bitwise.scala | 6 +- src/main/scala/chisel3/util/Cat.scala | 6 +- src/main/scala/chisel3/util/CircuitMath.scala | 4 +- src/main/scala/chisel3/util/Conditional.scala | 6 +- src/main/scala/chisel3/util/Counter.scala | 4 +- src/main/scala/chisel3/util/Decoupled.scala | 4 +- src/main/scala/chisel3/util/Enum.scala | 4 +- .../scala/chisel3/util/ImplicitConversions.scala | 4 +- src/main/scala/chisel3/util/LFSR.scala | 4 +- src/main/scala/chisel3/util/Lookup.scala | 4 +- src/main/scala/chisel3/util/Math.scala | 4 +- src/main/scala/chisel3/util/Mux.scala | 6 +- src/main/scala/chisel3/util/OneHot.scala | 4 +- src/main/scala/chisel3/util/Reg.scala | 4 +- src/main/scala/chisel3/util/TransitName.scala | 4 +- src/main/scala/chisel3/util/Valid.scala | 4 +- src/test/scala/chiselTests/Assert.scala | 6 +- src/test/scala/chiselTests/BitwiseOps.scala | 4 +- src/test/scala/chiselTests/BlackBox.scala | 6 +- src/test/scala/chiselTests/BundleWire.scala | 4 +- src/test/scala/chiselTests/ChiselSpec.scala | 4 +- src/test/scala/chiselTests/ComplexAssign.scala | 6 +- src/test/scala/chiselTests/Counter.scala | 6 +- src/test/scala/chiselTests/Decoder.scala | 6 +- src/test/scala/chiselTests/DeqIOSpec.scala | 6 +- src/test/scala/chiselTests/Direction.scala | 4 +- .../scala/chiselTests/EnableShiftRegister.scala | 4 +- src/test/scala/chiselTests/GCD.scala | 4 +- src/test/scala/chiselTests/Harness.scala | 4 +- src/test/scala/chiselTests/LFSR16.scala | 8 +- src/test/scala/chiselTests/MemorySearch.scala | 4 +- src/test/scala/chiselTests/Module.scala | 2 +- src/test/scala/chiselTests/MulLookup.scala | 4 +- src/test/scala/chiselTests/MultiAssign.scala | 6 +- src/test/scala/chiselTests/OptionBundle.scala | 4 +- src/test/scala/chiselTests/Padding.scala | 2 +- .../scala/chiselTests/ParameterizedModule.scala | 4 +- src/test/scala/chiselTests/Printf.scala | 4 +- src/test/scala/chiselTests/Reg.scala | 4 +- src/test/scala/chiselTests/Risc.scala | 4 +- src/test/scala/chiselTests/SIntOps.scala | 4 +- src/test/scala/chiselTests/Stack.scala | 4 +- src/test/scala/chiselTests/Stop.scala | 4 +- src/test/scala/chiselTests/Tbl.scala | 6 +- src/test/scala/chiselTests/TesterDriverSpec.scala | 6 +- src/test/scala/chiselTests/UIntOps.scala | 4 +- src/test/scala/chiselTests/Vec.scala | 6 +- src/test/scala/chiselTests/VectorPacketIO.scala | 6 +- src/test/scala/chiselTests/VendingMachine.scala | 4 +- src/test/scala/chiselTests/When.scala | 6 +- 62 files changed, 325 insertions(+), 325 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index ba2b1389..92e948cc 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -1,6 +1,6 @@ // See LICENSE for license details. -package chisel +package chisel3 import scala.sys.process._ import java.io._ diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 56088562..139e9431 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -1,150 +1,150 @@ // See LICENSE for license details. // Allows legacy users to continue using Chisel (capital C) package name while -// moving to the more standard package naming convention chisel (lowercase c). +// moving to the more standard package naming convention chisel3 (lowercase c). package object Chisel { - type Direction = chisel.core.Direction - val INPUT = chisel.core.INPUT - val OUTPUT = chisel.core.OUTPUT - val NO_DIR = chisel.core.NO_DIR - - type Flipped = chisel.core.Flipped - type Data = chisel.core.Data - val Wire = chisel.core.Wire - val Clock = chisel.core.Clock - type Clock = chisel.core.Clock - - type Aggregate = chisel.core.Aggregate - val Vec = chisel.core.Vec - type Vec[T <: Data] = chisel.core.Vec[T] - type VecLike[T <: Data] = chisel.core.VecLike[T] - type Bundle = chisel.core.Bundle - - val assert = chisel.core.assert - - type Element = chisel.core.Element - type Bits = chisel.core.Bits - val Bits = chisel.core.Bits - type Num[T <: Data] = chisel.core.Num[T] - type UInt = chisel.core.UInt - val UInt = chisel.core.UInt - type SInt = chisel.core.SInt - val SInt = chisel.core.SInt - type Bool = chisel.core.Bool - val Bool = chisel.core.Bool - val Mux = chisel.core.Mux - - type BlackBox = chisel.core.BlackBox - - val Mem = chisel.core.Mem - type MemBase[T <: Data] = chisel.core.MemBase[T] - type Mem[T <: Data] = chisel.core.Mem[T] - val SeqMem = chisel.core.SeqMem - type SeqMem[T <: Data] = chisel.core.SeqMem[T] - - val Module = chisel.core.Module - type Module = chisel.core.Module - - val printf = chisel.core.printf - - val Reg = chisel.core.Reg - - val when = chisel.core.when - type WhenContext = chisel.core.WhenContext - - - type BackendCompilationUtilities = chisel.BackendCompilationUtilities - val Driver = chisel.Driver - type FileSystemUtilities = chisel.compatibility.FileSystemUtilities - val ImplicitConversions = chisel.util.ImplicitConversions - val chiselMain = chisel.compatibility.chiselMain - val throwException = chisel.compatibility.throwException - val debug = chisel.compatibility.debug + type Direction = chisel3.core.Direction + val INPUT = chisel3.core.INPUT + val OUTPUT = chisel3.core.OUTPUT + val NO_DIR = chisel3.core.NO_DIR + + type Flipped = chisel3.core.Flipped + type Data = chisel3.core.Data + val Wire = chisel3.core.Wire + val Clock = chisel3.core.Clock + type Clock = chisel3.core.Clock + + type Aggregate = chisel3.core.Aggregate + val Vec = chisel3.core.Vec + type Vec[T <: Data] = chisel3.core.Vec[T] + type VecLike[T <: Data] = chisel3.core.VecLike[T] + type Bundle = chisel3.core.Bundle + + val assert = chisel3.core.assert + + type Element = chisel3.core.Element + type Bits = chisel3.core.Bits + val Bits = chisel3.core.Bits + type Num[T <: Data] = chisel3.core.Num[T] + type UInt = chisel3.core.UInt + val UInt = chisel3.core.UInt + type SInt = chisel3.core.SInt + val SInt = chisel3.core.SInt + type Bool = chisel3.core.Bool + val Bool = chisel3.core.Bool + val Mux = chisel3.core.Mux + + type BlackBox = chisel3.core.BlackBox + + val Mem = chisel3.core.Mem + type MemBase[T <: Data] = chisel3.core.MemBase[T] + type Mem[T <: Data] = chisel3.core.Mem[T] + val SeqMem = chisel3.core.SeqMem + type SeqMem[T <: Data] = chisel3.core.SeqMem[T] + + val Module = chisel3.core.Module + type Module = chisel3.core.Module + + val printf = chisel3.core.printf + + val Reg = chisel3.core.Reg + + val when = chisel3.core.when + type WhenContext = chisel3.core.WhenContext + + + type BackendCompilationUtilities = chisel3.BackendCompilationUtilities + val Driver = chisel3.Driver + type FileSystemUtilities = chisel3.compatibility.FileSystemUtilities + val ImplicitConversions = chisel3.util.ImplicitConversions + val chiselMain = chisel3.compatibility.chiselMain + val throwException = chisel3.compatibility.throwException + val debug = chisel3.compatibility.debug object testers { - type BasicTester = chisel.testers.BasicTester - val TesterDriver = chisel.testers.TesterDriver + type BasicTester = chisel3.testers.BasicTester + val TesterDriver = chisel3.testers.TesterDriver } - val log2Up = chisel.util.log2Up - val log2Ceil = chisel.util.log2Ceil - val log2Down = chisel.util.log2Down - val log2Floor = chisel.util.log2Floor - val isPow2 = chisel.util.isPow2 - - val BitPat = chisel.util.BitPat - type BitPat = chisel.util.BitPat - - type ArbiterIO[T <: Data] = chisel.util.ArbiterIO[T] - type LockingArbiterLike[T <: Data] = chisel.util.LockingArbiterLike[T] - type LockingRRArbiter[T <: Data] = chisel.util.LockingRRArbiter[T] - type LockingArbiter[T <: Data] = chisel.util.LockingArbiter[T] - type RRArbiter[T <: Data] = chisel.util.RRArbiter[T] - type Arbiter[T <: Data] = chisel.util.Arbiter[T] - - val FillInterleaved = chisel.util.FillInterleaved - val PopCount = chisel.util.PopCount - val Fill = chisel.util.Fill - val Reverse = chisel.util.Reverse - - val Cat = chisel.util.Cat - - val Log2 = chisel.util.Log2 - - val unless = chisel.util.unless - type SwitchContext[T <: Bits] = chisel.util.SwitchContext[T] - val is = chisel.util.is - val switch = chisel.util.switch - - type Counter = chisel.util.Counter - val Counter = chisel.util.Counter - - type DecoupledIO[+T <: Data] = chisel.util.DecoupledIO[T] - val Decoupled = chisel.util.Decoupled - type EnqIO[T <: Data] = chisel.util.EnqIO[T] - type DeqIO[T <: Data] = chisel.util.DeqIO[T] - type DecoupledIOC[+T <: Data] = chisel.util.DecoupledIOC[T] - type QueueIO[T <: Data] = chisel.util.QueueIO[T] - type Queue[T <: Data] = chisel.util.Queue[T] - val Queue = chisel.util.Queue - - val Enum = chisel.util.Enum - - val LFSR16 = chisel.util.LFSR16 - - val ListLookup = chisel.util.ListLookup - val Lookup = chisel.util.Lookup - - val Mux1H = chisel.util.Mux1H - val PriorityMux = chisel.util.PriorityMux - val MuxLookup = chisel.util.MuxLookup - val MuxCase = chisel.util.MuxCase - - val OHToUInt = chisel.util.OHToUInt - val PriorityEncoder = chisel.util.PriorityEncoder - val UIntToOH = chisel.util.UIntToOH - val PriorityEncoderOH = chisel.util.PriorityEncoderOH - - val RegNext = chisel.util.RegNext - val RegInit = chisel.util.RegInit - val RegEnable = chisel.util.RegEnable - val ShiftRegister = chisel.util.ShiftRegister - - type ValidIO[+T <: Data] = chisel.util.ValidIO[T] - val Valid = chisel.util.Valid - val Pipe = chisel.util.Pipe - type Pipe[T <: Data] = chisel.util.Pipe[T] - - - import chisel.internal.firrtl.Width - implicit def fromBigIntToLiteral(x: BigInt): chisel.fromBigIntToLiteral = - new chisel.fromBigIntToLiteral(x) - implicit def fromIntToLiteral(x: Int): chisel.fromIntToLiteral= - new chisel.fromIntToLiteral(x) - implicit def fromStringToLiteral(x: String): chisel.fromStringToLiteral= - new chisel.fromStringToLiteral(x) - implicit def fromBooleanToLiteral(x: Boolean): chisel.fromBooleanToLiteral= - new chisel.fromBooleanToLiteral(x) + val log2Up = chisel3.util.log2Up + val log2Ceil = chisel3.util.log2Ceil + val log2Down = chisel3.util.log2Down + val log2Floor = chisel3.util.log2Floor + val isPow2 = chisel3.util.isPow2 + + val BitPat = chisel3.util.BitPat + type BitPat = chisel3.util.BitPat + + type ArbiterIO[T <: Data] = chisel3.util.ArbiterIO[T] + type LockingArbiterLike[T <: Data] = chisel3.util.LockingArbiterLike[T] + type LockingRRArbiter[T <: Data] = chisel3.util.LockingRRArbiter[T] + type LockingArbiter[T <: Data] = chisel3.util.LockingArbiter[T] + type RRArbiter[T <: Data] = chisel3.util.RRArbiter[T] + type Arbiter[T <: Data] = chisel3.util.Arbiter[T] + + val FillInterleaved = chisel3.util.FillInterleaved + val PopCount = chisel3.util.PopCount + val Fill = chisel3.util.Fill + val Reverse = chisel3.util.Reverse + + val Cat = chisel3.util.Cat + + val Log2 = chisel3.util.Log2 + + val unless = chisel3.util.unless + type SwitchContext[T <: Bits] = chisel3.util.SwitchContext[T] + val is = chisel3.util.is + val switch = chisel3.util.switch + + type Counter = chisel3.util.Counter + val Counter = chisel3.util.Counter + + type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T] + val Decoupled = chisel3.util.Decoupled + type EnqIO[T <: Data] = chisel3.util.EnqIO[T] + type DeqIO[T <: Data] = chisel3.util.DeqIO[T] + type DecoupledIOC[+T <: Data] = chisel3.util.DecoupledIOC[T] + type QueueIO[T <: Data] = chisel3.util.QueueIO[T] + type Queue[T <: Data] = chisel3.util.Queue[T] + val Queue = chisel3.util.Queue + + val Enum = chisel3.util.Enum + + val LFSR16 = chisel3.util.LFSR16 + + val ListLookup = chisel3.util.ListLookup + val Lookup = chisel3.util.Lookup + + val Mux1H = chisel3.util.Mux1H + val PriorityMux = chisel3.util.PriorityMux + val MuxLookup = chisel3.util.MuxLookup + val MuxCase = chisel3.util.MuxCase + + val OHToUInt = chisel3.util.OHToUInt + val PriorityEncoder = chisel3.util.PriorityEncoder + val UIntToOH = chisel3.util.UIntToOH + val PriorityEncoderOH = chisel3.util.PriorityEncoderOH + + val RegNext = chisel3.util.RegNext + val RegInit = chisel3.util.RegInit + val RegEnable = chisel3.util.RegEnable + val ShiftRegister = chisel3.util.ShiftRegister + + type ValidIO[+T <: Data] = chisel3.util.ValidIO[T] + val Valid = chisel3.util.Valid + val Pipe = chisel3.util.Pipe + type Pipe[T <: Data] = chisel3.util.Pipe[T] + + + import chisel3.internal.firrtl.Width + implicit def fromBigIntToLiteral(x: BigInt): chisel3.fromBigIntToLiteral = + new chisel3.fromBigIntToLiteral(x) + implicit def fromIntToLiteral(x: Int): chisel3.fromIntToLiteral= + new chisel3.fromIntToLiteral(x) + implicit def fromStringToLiteral(x: String): chisel3.fromStringToLiteral= + new chisel3.fromStringToLiteral(x) + implicit def fromBooleanToLiteral(x: Boolean): chisel3.fromBooleanToLiteral= + new chisel3.fromBooleanToLiteral(x) } diff --git a/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala index d12e627d..cd47c731 100644 --- a/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala +++ b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. -package chisel.compatibility +package chisel3.compatibility -import chisel._ +import chisel3._ @deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0") trait FileSystemUtilities { diff --git a/src/main/scala/chisel3/compatibility/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala index 9072bfcf..a41599a3 100644 --- a/src/main/scala/chisel3/compatibility/Main.scala +++ b/src/main/scala/chisel3/compatibility/Main.scala @@ -1,10 +1,10 @@ // See LICENSE for license details. -package chisel.compatibility +package chisel3.compatibility import java.io.File -import chisel._ +import chisel3._ @deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain { def apply[T <: Module](args: Array[String], gen: () => T): Unit = diff --git a/src/main/scala/chisel3/compatibility/debug.scala b/src/main/scala/chisel3/compatibility/debug.scala index 8850c76b..c3966dae 100644 --- a/src/main/scala/chisel3/compatibility/debug.scala +++ b/src/main/scala/chisel3/compatibility/debug.scala @@ -1,6 +1,6 @@ -package chisel.compatibility +package chisel3.compatibility -import chisel.core._ +import chisel3.core._ @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3") object debug { // scalastyle:ignore object.name diff --git a/src/main/scala/chisel3/compatibility/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala index 3b9fd06e..3e8b33e6 100644 --- a/src/main/scala/chisel3/compatibility/throwException.scala +++ b/src/main/scala/chisel3/compatibility/throwException.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. -package chisel.compatibility +package chisel3.compatibility -import chisel._ +import chisel3._ @deprecated("throwException doesn't exist in Chisel3", "3.0.0") @throws(classOf[Exception]) diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index e48eb226..08646cf9 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -1,10 +1,10 @@ // See LICENSE for license details. -package chisel.internal.firrtl -import chisel._ -import chisel.internal.sourceinfo.{NoSourceInfo, SourceLine} +package chisel3.internal.firrtl +import chisel3._ +import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine} -private[chisel] object Emitter { +private[chisel3] object Emitter { def emit(circuit: Circuit): String = new Emitter(circuit).toString } diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index f7ed6b13..0b548683 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -1,4 +1,4 @@ -package object chisel { +package object chisel3 { import scala.language.experimental.macros import internal.firrtl.Width @@ -6,53 +6,53 @@ package object chisel { import util.BitPat - type Direction = chisel.core.Direction - val INPUT = chisel.core.INPUT - val OUTPUT = chisel.core.OUTPUT - val NO_DIR = chisel.core.NO_DIR - type Flipped = chisel.core.Flipped - type Data = chisel.core.Data - val Wire = chisel.core.Wire - val Clock = chisel.core.Clock - type Clock = chisel.core.Clock - - type Aggregate = chisel.core.Aggregate - val Vec = chisel.core.Vec - type Vec[T <: Data] = chisel.core.Vec[T] - type VecLike[T <: Data] = chisel.core.VecLike[T] - type Bundle = chisel.core.Bundle - - val assert = chisel.core.assert - - type Element = chisel.core.Element - type Bits = chisel.core.Bits - val Bits = chisel.core.Bits - type Num[T <: Data] = chisel.core.Num[T] - type UInt = chisel.core.UInt - val UInt = chisel.core.UInt - type SInt = chisel.core.SInt - val SInt = chisel.core.SInt - type Bool = chisel.core.Bool - val Bool = chisel.core.Bool - val Mux = chisel.core.Mux - - type BlackBox = chisel.core.BlackBox - - val Mem = chisel.core.Mem - type MemBase[T <: Data] = chisel.core.MemBase[T] - type Mem[T <: Data] = chisel.core.Mem[T] - val SeqMem = chisel.core.SeqMem - type SeqMem[T <: Data] = chisel.core.SeqMem[T] - - val Module = chisel.core.Module - type Module = chisel.core.Module - - val printf = chisel.core.printf - - val Reg = chisel.core.Reg - - val when = chisel.core.when - type WhenContext = chisel.core.WhenContext + type Direction = chisel3.core.Direction + val INPUT = chisel3.core.INPUT + val OUTPUT = chisel3.core.OUTPUT + val NO_DIR = chisel3.core.NO_DIR + type Flipped = chisel3.core.Flipped + type Data = chisel3.core.Data + val Wire = chisel3.core.Wire + val Clock = chisel3.core.Clock + type Clock = chisel3.core.Clock + + type Aggregate = chisel3.core.Aggregate + val Vec = chisel3.core.Vec + type Vec[T <: Data] = chisel3.core.Vec[T] + type VecLike[T <: Data] = chisel3.core.VecLike[T] + type Bundle = chisel3.core.Bundle + + val assert = chisel3.core.assert + + type Element = chisel3.core.Element + type Bits = chisel3.core.Bits + val Bits = chisel3.core.Bits + type Num[T <: Data] = chisel3.core.Num[T] + type UInt = chisel3.core.UInt + val UInt = chisel3.core.UInt + type SInt = chisel3.core.SInt + val SInt = chisel3.core.SInt + type Bool = chisel3.core.Bool + val Bool = chisel3.core.Bool + val Mux = chisel3.core.Mux + + type BlackBox = chisel3.core.BlackBox + + val Mem = chisel3.core.Mem + type MemBase[T <: Data] = chisel3.core.MemBase[T] + type Mem[T <: Data] = chisel3.core.Mem[T] + val SeqMem = chisel3.core.SeqMem + type SeqMem[T <: Data] = chisel3.core.SeqMem[T] + + val Module = chisel3.core.Module + type Module = chisel3.core.Module + + val printf = chisel3.core.printf + + val Reg = chisel3.core.Reg + + val when = chisel3.core.when + type WhenContext = chisel3.core.WhenContext implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal { diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala index 36ff7c52..f91536d5 100644 --- a/src/main/scala/chisel3/testers/BasicTester.scala +++ b/src/main/scala/chisel3/testers/BasicTester.scala @@ -1,7 +1,7 @@ // See LICENSE for license details. -package chisel.testers -import chisel._ +package chisel3.testers +import chisel3._ import scala.language.experimental.macros diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala index 5c0275e0..586fa780 100644 --- a/src/main/scala/chisel3/testers/TesterDriver.scala +++ b/src/main/scala/chisel3/testers/TesterDriver.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. -package chisel.testers +package chisel3.testers -import chisel._ +import chisel3._ import scala.io.Source import scala.sys.process._ import java.io._ diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index 3723f2a9..eb541977 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -3,9 +3,9 @@ /** Arbiters in all shapes and sizes. */ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ /** An I/O bundle for the Arbiter */ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle { diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala index 13bbe1b0..9eb5cf67 100644 --- a/src/main/scala/chisel3/util/BitPat.scala +++ b/src/main/scala/chisel3/util/BitPat.scala @@ -1,11 +1,11 @@ // See LICENSE for license details. -package chisel.util +package chisel3.util import scala.language.experimental.macros -import chisel._ -import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform} +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform} object BitPat { /** Parses a bit pattern string into (bits, mask, width). diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index d7d62ea3..ab1ff550 100644 --- a/src/main/scala/chisel3/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -3,10 +3,10 @@ /** Miscellaneous circuit generators operating on bits. */ -package chisel.util +package chisel3.util -import chisel._ -import chisel.core.SeqUtils +import chisel3._ +import chisel3.core.SeqUtils object FillInterleaved { diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala index b47da706..469bf9ab 100644 --- a/src/main/scala/chisel3/util/Cat.scala +++ b/src/main/scala/chisel3/util/Cat.scala @@ -1,9 +1,9 @@ // See LICENSE for license details. -package chisel.util +package chisel3.util -import chisel._ -import chisel.core.SeqUtils +import chisel3._ +import chisel3.core.SeqUtils object Cat { /** Combine data elements together diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala index c3b94fdb..1174c71c 100644 --- a/src/main/scala/chisel3/util/CircuitMath.scala +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -3,9 +3,9 @@ /** Circuit-land math operations. */ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ /** Compute Log2 with truncation of a UInt in hardware using a Mux Tree * An alternative interpretation is it computes the minimum number of bits needed to represent x diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala index 01c12799..6218feb0 100644 --- a/src/main/scala/chisel3/util/Conditional.scala +++ b/src/main/scala/chisel3/util/Conditional.scala @@ -3,14 +3,14 @@ /** Conditional blocks. */ -package chisel.util +package chisel3.util import scala.language.reflectiveCalls import scala.language.experimental.macros import scala.reflect.runtime.universe._ import scala.reflect.macros.blackbox._ -import chisel._ +import chisel3._ /** This is identical to [[Chisel.when when]] with the condition inverted */ object unless { // scalastyle:ignore object.name @@ -63,7 +63,7 @@ object switch { // scalastyle:ignore object.name def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match { // TODO: remove when Chisel compatibility package is removed case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") - case q"chisel.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") + case q"chisel3.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )") case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.") } val q"..$body" = x diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala index 1c0b0203..40615769 100644 --- a/src/main/scala/chisel3/util/Counter.scala +++ b/src/main/scala/chisel3/util/Counter.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ /** A counter module * @param n number of counts before the counter resets (or one more than the diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 89b0e39d..f37a5c31 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -3,9 +3,9 @@ /** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them. */ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ /** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/ class DecoupledIO[+T <: Data](gen: T) extends Bundle diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala index 8babcd23..4ecc243b 100644 --- a/src/main/scala/chisel3/util/Enum.scala +++ b/src/main/scala/chisel3/util/Enum.scala @@ -3,9 +3,9 @@ /** Enum generators, allowing circuit constants to have more meaningful names. */ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ object Enum { /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */ diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala index 846c0cbd..4d816a19 100644 --- a/src/main/scala/chisel3/util/ImplicitConversions.scala +++ b/src/main/scala/chisel3/util/ImplicitConversions.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ object ImplicitConversions { implicit def intToUInt(x: Int): UInt = UInt(x) diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala index f70630bf..a30c276f 100644 --- a/src/main/scala/chisel3/util/LFSR.scala +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -3,9 +3,9 @@ /** LFSRs in all shapes and sizes. */ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ // scalastyle:off magic.number /** linear feedback shift register diff --git a/src/main/scala/chisel3/util/Lookup.scala b/src/main/scala/chisel3/util/Lookup.scala index d32d9aec..9e909c0c 100644 --- a/src/main/scala/chisel3/util/Lookup.scala +++ b/src/main/scala/chisel3/util/Lookup.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ object ListLookup { def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = { diff --git a/src/main/scala/chisel3/util/Math.scala b/src/main/scala/chisel3/util/Math.scala index 69464d15..73665f0f 100644 --- a/src/main/scala/chisel3/util/Math.scala +++ b/src/main/scala/chisel3/util/Math.scala @@ -3,9 +3,9 @@ /** Scala-land math helper functions, like logs. */ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ /** Compute the log2 rounded up with min value of 1 */ object log2Up { diff --git a/src/main/scala/chisel3/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala index 6f074a7e..07a34f9b 100644 --- a/src/main/scala/chisel3/util/Mux.scala +++ b/src/main/scala/chisel3/util/Mux.scala @@ -3,10 +3,10 @@ /** Mux circuit generators. */ -package chisel.util +package chisel3.util -import chisel._ -import chisel.core.SeqUtils +import chisel3._ +import chisel3.core.SeqUtils /** Builds a Mux tree out of the input signal vector using a one hot encoded select signal. Returns the output of the Mux tree. diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala index ef21c65d..820c72d6 100644 --- a/src/main/scala/chisel3/util/OneHot.scala +++ b/src/main/scala/chisel3/util/OneHot.scala @@ -3,9 +3,9 @@ /** Circuit generators for working with one-hot representations. */ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ /** Converts from One Hot Encoding to a UInt indicating which bit is active * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/ diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index 1b40646d..81de4754 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -3,9 +3,9 @@ /** Variations and helpers for registers. */ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ object RegNext { diff --git a/src/main/scala/chisel3/util/TransitName.scala b/src/main/scala/chisel3/util/TransitName.scala index 04e1995b..f36f926f 100644 --- a/src/main/scala/chisel3/util/TransitName.scala +++ b/src/main/scala/chisel3/util/TransitName.scala @@ -1,6 +1,6 @@ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ import internal.HasId object TransitName { diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 56ac9abb..78187ff6 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -3,9 +3,9 @@ /** Wrappers for valid interfaces and associated circuit generators using them. */ -package chisel.util +package chisel3.util -import chisel._ +import chisel3._ /** An I/O Bundle containing data and a signal determining if it is valid */ class ValidIO[+T <: Data](gen2: T) extends Bundle diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index eb8617b2..3fed2bd4 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -3,9 +3,9 @@ package chiselTests import org.scalatest._ -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class FailingAssertTester() extends BasicTester { assert(Bool(false)) diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala index 0c1d4d74..08999a1b 100644 --- a/src/test/scala/chiselTests/BitwiseOps.scala +++ b/src/test/scala/chiselTests/BitwiseOps.scala @@ -2,10 +2,10 @@ package chiselTests -import chisel._ +import chisel3._ import org.scalatest._ import org.scalatest.prop._ -import chisel.testers.BasicTester +import chisel3.testers.BasicTester class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester { val mask = (1 << w) - 1 diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index b77550c1..fdc5970e 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -5,9 +5,9 @@ package chiselTests import java.io.File import org.scalatest._ -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class BlackBoxInverter extends BlackBox { val io = new Bundle() { diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index 36dbb365..e5e9fb1a 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -1,10 +1,10 @@ // See LICENSE for license details. package chiselTests -import chisel._ +import chisel3._ import org.scalatest._ import org.scalatest.prop._ -import chisel.testers.BasicTester +import chisel3.testers.BasicTester class Coord extends Bundle { val x = UInt(width = 32) diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index 9c66b0db..d335bdf6 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -6,8 +6,8 @@ import java.io.File import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ -import chisel._ -import chisel.testers._ +import chisel3._ +import chisel3.testers._ /** Common utility functions for Chisel unit tests. */ trait ChiselRunners extends Assertions { diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index 53a6a67d..304fbcf5 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -5,9 +5,9 @@ package chiselTests import org.scalatest._ import org.scalatest.prop._ -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class Complex[T <: Data](val re: T, val im: T) extends Bundle { override def cloneType: this.type = diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala index 963c1c92..69d8a44a 100644 --- a/src/test/scala/chiselTests/Counter.scala +++ b/src/test/scala/chiselTests/Counter.scala @@ -5,9 +5,9 @@ package chiselTests import org.scalatest._ import org.scalatest.prop._ -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class CountTester(max: Int) extends BasicTester { val cnt = Counter(max) diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index 33980955..5586561b 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -6,9 +6,9 @@ import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class Decoder(bitpats: List[String]) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala index 95160140..09891647 100644 --- a/src/test/scala/chiselTests/DeqIOSpec.scala +++ b/src/test/scala/chiselTests/DeqIOSpec.scala @@ -2,9 +2,9 @@ package chiselTests -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ /** * Created by chick on 2/8/16. diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 3ed543aa..8b84f844 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -2,10 +2,10 @@ package chiselTests -import chisel._ +import chisel3._ import org.scalatest._ import org.scalatest.prop._ -import chisel.testers.BasicTester +import chisel3.testers.BasicTester class DirectionHaver extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 30fc2486..7db20fc1 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. package chiselTests -import chisel._ -import chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class EnableShiftRegister extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala index 77452db6..60a70cc8 100644 --- a/src/test/scala/chiselTests/GCD.scala +++ b/src/test/scala/chiselTests/GCD.scala @@ -2,8 +2,8 @@ package chiselTests -import chisel._ -import chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester import org.scalatest._ import org.scalatest.prop._ diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala index 805e2de9..83f60391 100644 --- a/src/test/scala/chiselTests/Harness.scala +++ b/src/test/scala/chiselTests/Harness.scala @@ -2,13 +2,13 @@ package chiselTests -import chisel.testers.BasicTester +import chisel3.testers.BasicTester import org.scalatest._ import org.scalatest.prop._ import java.io.File class HarnessSpec extends ChiselPropSpec - with chisel.BackendCompilationUtilities { + with chisel3.BackendCompilationUtilities { def makeTrivialVerilog: (File => File) = makeHarness((prefix: String) => s""" module ${prefix}; diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index b3e69884..a1699441 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -2,9 +2,9 @@ package chiselTests -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class LFSR16 extends Module { val io = new Bundle { @@ -36,7 +36,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) { } */ -//TODO: Use chisel.util version instead? +//TODO: Use chisel3.util version instead? class LFSRSpec extends ChiselPropSpec { diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index b48d2881..679b894c 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -2,8 +2,8 @@ package chiselTests -import chisel._ -import chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class MemorySearch extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 64b00fab..23788b72 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -2,7 +2,7 @@ package chiselTests -import chisel._ +import chisel3._ class SimpleIO extends Bundle { val in = UInt(INPUT, 32) diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala index 5e223f91..831e323f 100644 --- a/src/test/scala/chiselTests/MulLookup.scala +++ b/src/test/scala/chiselTests/MulLookup.scala @@ -2,10 +2,10 @@ package chiselTests -import chisel._ +import chisel3._ import org.scalatest._ import org.scalatest.prop._ -import chisel.testers.BasicTester +import chisel3.testers.BasicTester class MulLookup(val w: Int) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 152e6723..c22a5e30 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -4,9 +4,9 @@ package chiselTests import org.scalatest._ -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class LastAssignTester() extends BasicTester { val cnt = Counter(2) diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala index ab3b6860..fa691b43 100644 --- a/src/test/scala/chiselTests/OptionBundle.scala +++ b/src/test/scala/chiselTests/OptionBundle.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import chisel._ -import chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class OptionBundle(hasIn: Boolean) extends Bundle { val in = if (hasIn) { diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala index 03496649..3fb0f955 100644 --- a/src/test/scala/chiselTests/Padding.scala +++ b/src/test/scala/chiselTests/Padding.scala @@ -2,7 +2,7 @@ package chiselTests -import chisel._ +import chisel3._ class Padder extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala index e2629224..4859759e 100644 --- a/src/test/scala/chiselTests/ParameterizedModule.scala +++ b/src/test/scala/chiselTests/ParameterizedModule.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import chisel._ -import chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class ParameterizedModule(invert: Boolean) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala index b5e1e66e..c872fde4 100644 --- a/src/test/scala/chiselTests/Printf.scala +++ b/src/test/scala/chiselTests/Printf.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import chisel._ -import chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class SinglePrintfTester() extends BasicTester { val x = UInt(254) diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 8954c3ef..fc2cbf9d 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import chisel._ -import chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class RegSpec extends ChiselFlatSpec { "A Reg" should "throw an exception if not given any parameters" in { diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 741e9896..f5e61115 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -2,8 +2,8 @@ package chiselTests -import chisel._ -import chisel.util._ +import chisel3._ +import chisel3.util._ class Risc extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index 07111af6..6cd013f1 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -2,8 +2,8 @@ package chiselTests -import chisel._ -import chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class SIntOps extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 0ce228de..cbd9f3e3 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -4,8 +4,8 @@ package chiselTests import scala.collection.mutable.Stack -import chisel._ -import chisel.util._ +import chisel3._ +import chisel3.util._ class ChiselStack(val depth: Int) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala index d57eb7c6..4afb077a 100644 --- a/src/test/scala/chiselTests/Stop.scala +++ b/src/test/scala/chiselTests/Stop.scala @@ -3,8 +3,8 @@ package chiselTests import org.scalatest._ -import chisel._ -import chisel.testers.BasicTester +import chisel3._ +import chisel3.testers.BasicTester class StopTester() extends BasicTester { stop() diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 2049d8bb..d84cd85e 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -5,9 +5,9 @@ package chiselTests import org.scalatest._ import org.scalatest.prop._ -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class Tbl(w: Int, n: Int) extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index 50290fab..2f3e9368 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -2,9 +2,9 @@ package chiselTests -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ /** Extend BasicTester with a simple circuit and finish method. TesterDriver will call the * finish method after the FinishTester's constructor has completed, which will alter the diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala index 8b2a31fd..c5069fc4 100644 --- a/src/test/scala/chiselTests/UIntOps.scala +++ b/src/test/scala/chiselTests/UIntOps.scala @@ -2,9 +2,9 @@ package chiselTests -import chisel._ +import chisel3._ import org.scalatest._ -import chisel.testers.BasicTester +import chisel3.testers.BasicTester class UIntOps extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 35a0c8bc..7dd80a13 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -5,9 +5,9 @@ package chiselTests import org.scalatest._ import org.scalatest.prop._ -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala index a1282071..07779faa 100644 --- a/src/test/scala/chiselTests/VectorPacketIO.scala +++ b/src/test/scala/chiselTests/VectorPacketIO.scala @@ -2,9 +2,9 @@ package chiselTests -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ /** * This test used to fail when assignment statements were diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala index 0d621e6a..f03cb881 100644 --- a/src/test/scala/chiselTests/VendingMachine.scala +++ b/src/test/scala/chiselTests/VendingMachine.scala @@ -2,8 +2,8 @@ package chiselTests -import chisel._ -import chisel.util._ +import chisel3._ +import chisel3.util._ class VendingMachine extends Module { val io = new Bundle { diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index 1c9c3bc5..5f3d3e61 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -4,9 +4,9 @@ package chiselTests import org.scalatest._ -import chisel._ -import chisel.testers.BasicTester -import chisel.util._ +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class WhenTester() extends BasicTester { val cnt = Counter(4) -- cgit v1.2.3 From 077aa80ea61b8517ef13f72d1fa3bec2aaa3063b Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 20 Jun 2016 13:44:08 -0700 Subject: make sure MuxCase and MuxLookup can take all subclasses of Data (#222) --- src/main/scala/chisel/util/Mux.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala index 6f074a7e..04b174e9 100644 --- a/src/main/scala/chisel/util/Mux.scala +++ b/src/main/scala/chisel/util/Mux.scala @@ -40,7 +40,7 @@ object MuxLookup { * @param mapping a sequence to search of keys and values * @return the value found or the default if not */ - def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = { + def apply[S <: UInt, T <: Data] (key: S, default: T, mapping: Seq[(S, T)]): T = { var res = default for ((k, v) <- mapping.reverse) res = Mux(k === key, v, res) @@ -54,7 +54,7 @@ object MuxCase { /** @param default the default value if none are enabled * @param mapping a set of data values with associated enables * @return the first value in mapping that is enabled */ - def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = { + def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = { var res = default for ((t, v) <- mapping.reverse){ res = Mux(t, v, res) -- cgit v1.2.3 From 2e9b41cafe9158f20ecb03ae9eabecb82e557829 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 23 Jun 2016 12:14:34 -0700 Subject: Expose FIRRTL stop construct --- src/main/scala/chisel/compatibility.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala index 56088562..af5daef7 100644 --- a/src/main/scala/chisel/compatibility.scala +++ b/src/main/scala/chisel/compatibility.scala @@ -22,6 +22,7 @@ package object Chisel { type Bundle = chisel.core.Bundle val assert = chisel.core.assert + val stop = chisel.core.stop type Element = chisel.core.Element type Bits = chisel.core.Bits -- cgit v1.2.3 From 3eb51f8484ad21d8a39da1ab7b036f1bb3bbe102 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 27 Jun 2016 14:04:37 -0700 Subject: Guard firrtl stop, fixing pipelined reset --- src/main/scala/chisel/Driver.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/main/scala/chisel/Driver.scala b/src/main/scala/chisel/Driver.scala index ba2b1389..8fdc8f65 100644 --- a/src/main/scala/chisel/Driver.scala +++ b/src/main/scala/chisel/Driver.scala @@ -71,6 +71,7 @@ trait BackendCompilationUtilities { "--top-module", topModule, "+define+TOP_TYPE=V" + dutFile, s"+define+PRINTF_COND=!$topModule.reset", + s"+define+STOP_COND=!$topModule.reset", "-CFLAGS", s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""", "-Mdir", dir.toString, -- cgit v1.2.3 From fb39f7dc372b5836f02d8d7964f5fcc6a38f8747 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 7 Jul 2016 00:11:15 -0700 Subject: Avoid needlessly creating Vecs --- src/main/scala/chisel3/util/Bitwise.scala | 2 +- src/main/scala/chisel3/util/OneHot.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index ab1ff550..7f295200 100644 --- a/src/main/scala/chisel3/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -11,7 +11,7 @@ import chisel3.core.SeqUtils object FillInterleaved { def apply(n: Int, in: UInt): UInt = apply(n, in.toBools) - def apply(n: Int, in: Seq[Bool]): UInt = Vec(in.map(Fill(n, _))).toBits + def apply(n: Int, in: Seq[Bool]): UInt = Cat(in.map(Fill(n, _)).reverse) } /** Returns the number of bits set (i.e value is 1) in the input signal. diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala index 820c72d6..abede61e 100644 --- a/src/main/scala/chisel3/util/OneHot.scala +++ b/src/main/scala/chisel3/util/OneHot.scala @@ -10,7 +10,7 @@ import chisel3._ /** Converts from One Hot Encoding to a UInt indicating which bit is active * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/ object OHToUInt { - def apply(in: Seq[Bool]): UInt = apply(Vec(in)) + def apply(in: Seq[Bool]): UInt = apply(Cat(in.reverse), in.size) def apply(in: Vec[Bool]): UInt = apply(in.toBits, in.size) def apply(in: Bits): UInt = apply(in, in.getWidth) -- cgit v1.2.3 From bae5cbbbf64782ffe7a5a06981d94655bfc76089 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 6 Jul 2016 23:01:42 -0700 Subject: Correct erroneous Log2 documentation --- src/main/scala/chisel3/util/CircuitMath.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala index 1174c71c..b5be03bf 100644 --- a/src/main/scala/chisel3/util/CircuitMath.scala +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -7,11 +7,11 @@ package chisel3.util import chisel3._ -/** Compute Log2 with truncation of a UInt in hardware using a Mux Tree - * An alternative interpretation is it computes the minimum number of bits needed to represent x +/** Compute the base-2 integer logarithm of a UInt * @example * {{{ data_out := Log2(data_in) }}} - * @note Truncation is used so Log2(UInt(12412)) = 13*/ + * @note The result is truncated, so e.g. Log2(UInt(13)) = 3 + */ object Log2 { /** Compute the Log2 on the least significant n bits of x */ def apply(x: Bits, width: Int): UInt = { -- cgit v1.2.3 From a49e27d1247597de5997f0fe6f3d2ac594ec2e6b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 7 Jul 2016 00:37:34 -0700 Subject: Improve Fill code generation --- src/main/scala/chisel3/util/Bitwise.scala | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index 7f295200..3134d043 100644 --- a/src/main/scala/chisel3/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -29,22 +29,17 @@ object Fill { n match { case 0 => UInt(width=0) case 1 => x - case y if n > 1 => + case _ if x.width.known && x.getWidth == 1 => + Mux(x.toBool, UInt((BigInt(1) << n) - 1, n), UInt(0, n)) + case _ if n > 1 => val p2 = Array.ofDim[UInt](log2Up(n + 1)) p2(0) = x for (i <- 1 until p2.length) p2(i) = Cat(p2(i-1), p2(i-1)) - Cat((0 until log2Up(y + 1)).filter(i => (y & (1 << i)) != 0).map(p2(_))) + Cat((0 until log2Up(n + 1)).filter(i => (n & (1 << i)) != 0).map(p2(_))) case _ => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.") } } - /** Fan out x n times */ - def apply(n: Int, x: Bool): UInt = - if (n > 1) { - UInt(0,n) - x - } else { - apply(n, x: UInt) - } } /** Litte/big bit endian convertion: reverse the order of the bits in a UInt. -- cgit v1.2.3 From c90be4ea06faf9a39c85f38e932d29fe63eb4b37 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 7 Jul 2016 15:41:10 -0700 Subject: Improve QoR for Log2 For reasonable circuit delay, need to divide & conquer. --- src/main/scala/chisel3/util/CircuitMath.scala | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala index b5be03bf..a64447d9 100644 --- a/src/main/scala/chisel3/util/CircuitMath.scala +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -19,10 +19,18 @@ object Log2 { UInt(0) } else if (width == 2) { x(1) - } else { + } else if (width <= divideAndConquerThreshold) { Mux(x(width-1), UInt(width-1), apply(x, width-1)) + } else { + val mid = 1 << (log2Ceil(width) - 1) + val hi = x(width-1, mid) + val lo = x(mid-1, 0) + val useHi = hi.orR + Cat(useHi, Mux(useHi, Log2(hi, width - mid), Log2(lo, mid))) } } def apply(x: Bits): UInt = apply(x, x.getWidth) + + private def divideAndConquerThreshold = 4 } -- cgit v1.2.3 From 1b8f84859f2ac2d40085e6c31034dd598a5c6aad Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 7 Jul 2016 20:12:30 -0700 Subject: Don't check GCD result before sending it a request --- src/test/scala/chiselTests/GCD.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala index 60a70cc8..23df3256 100644 --- a/src/test/scala/chiselTests/GCD.scala +++ b/src/test/scala/chiselTests/GCD.scala @@ -31,7 +31,7 @@ class GCDTester(a: Int, b: Int, z: Int) extends BasicTester { dut.io.b := UInt(b) dut.io.e := first when(first) { first := Bool(false) } - when(dut.io.v) { + when(!first && dut.io.v) { assert(dut.io.z === UInt(z)) stop() } -- cgit v1.2.3 From bb5467fc67d3b8fc6cc2a15f6e681dc45f7cb029 Mon Sep 17 00:00:00 2001 From: Donggyu Date: Mon, 11 Jul 2016 15:17:59 -0700 Subject: bitpat should keep the width of uint (#232) --- src/main/scala/chisel3/util/BitPat.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala index 9eb5cf67..d476f957 100644 --- a/src/main/scala/chisel3/util/BitPat.scala +++ b/src/main/scala/chisel3/util/BitPat.scala @@ -68,7 +68,8 @@ object BitPat { */ def apply(x: UInt): BitPat = { require(x.isLit) - BitPat("b" + x.litValue.toString(2)) + val len = if (x.width.known) x.getWidth else 0 + apply("b" + x.litValue.toString(2).reverse.padTo(len, "0").reverse.mkString) } } @@ -83,7 +84,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) { def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg def != (that: UInt): Bool = macro SourceInfoTransform.thatArg - def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value) === (that & UInt(mask)) + def do_=== (that: UInt)(implicit sourceInfo: SourceInfo): Bool = UInt(value, width) === (that & UInt(mask)) def do_=/= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = !(this === that) def do_!= (that: UInt)(implicit sourceInfo: SourceInfo): Bool = this =/= that } -- cgit v1.2.3 From 54cd58cbb435170dd2ed67dafe1cb1d769a799e8 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 20 Jul 2016 13:33:23 -0700 Subject: Generate better names for nodes (#190) For Chisel nodes defined in Module class-level values of type Option or Iterable, we can still use reflection to assign names based on the name of the value. This works for arbitrary nesting of Option and Iterable so long as the innermost type is HasId. Note that this excludes Maps which always have an innermost type of Tuple2[_,_]. --- src/test/scala/chiselTests/BetterNamingTests.scala | 101 +++++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 src/test/scala/chiselTests/BetterNamingTests.scala (limited to 'src') diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala new file mode 100644 index 00000000..44fc542a --- /dev/null +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -0,0 +1,101 @@ +package chiselTests + +import org.scalatest.{FlatSpec, Matchers} +import collection.mutable + +import Chisel._ + + +// Defined outside of the class so we don't get $ in name +class Other(w: Int) extends Module { + val io = new Bundle { + val a = UInt(width = w) + } +} +class PerNameIndexing(count: Int) extends Module { + val io = new Bundle { } + + val wires = Seq.tabulate(count) { i => Module(new Other(i)) } + val queues = Seq.tabulate(count) { i => Module(new Queue(UInt(width = i), 16)) } +} + +// Note this only checks Iterable[Chisel.Data] which excludes Maps +class IterableNaming extends Module { + val io = new Bundle { } + + val seq = Seq.tabulate(3) { i => + Seq.tabulate(2) { j => Wire(init = (i * j).U) } + } + val optSet = Some(Set(Wire(init = 0.U), + Wire(init = 1.U), + Wire(init = 2.U), + Wire(init = 3.U))) + + val stack = mutable.Stack[Module]() + for (i <- 0 until 4) { + stack push Module(new Other(i)) + } + + def streamFrom(x: Int): Stream[Module] = + Module(new Other(x)) #:: streamFrom(x + 1) + val stream = streamFrom(0) // Check that we don't get into infinite loop + val list = stream.take(8).toList +} + +/* Better Naming Tests + * + * These tests are intended to validate that Chisel picks better names + */ +class BetterNamingTests extends FlatSpec { + + behavior of "Better Naming" + + it should "provide unique counters for each name" in { + val verilog = Driver.emit(() => new PerNameIndexing(4)) + val ModuleDef = """\s*module\s+(\S+)\s+:\s*""".r + val expectedModules = Set("PerNameIndexing", + "Queue", "Queue_1", "Queue_2", "Queue_3", + "Other", "Other_1", "Other_2", "Other_3") + val foundModules = for { + ModuleDef(name) <- verilog.split("\n").toSeq + } yield name + assert(foundModules.toSet === expectedModules) + } + + it should "provide names for things defined in Iterable[HasId] and Option[HasId]" in { + val verilog = Driver.emit(() => new IterableNaming) + + val lines = verilog.split("\n").toSeq + + val SeqDef = """\s*wire\s+seq_(\d+)_(\d+)\s+:\s+UInt\s*""".r + val seqs = for { + i <- (0 until 3) + j <- (0 until 2) + } yield (i.toString, j.toString) + val foundSeqs = for { + SeqDef(i, j) <- lines + } yield (i, j) + assert(foundSeqs.toSet === seqs.toSet) + + val OptSetDef = """\s*wire\s+optSet_(\d+)\s+:\s+UInt\s*""".r + val optSets = (0 until 4) map (_.toString) + val foundOptSets = for { + OptSetDef(i) <- lines + } yield i + assert(foundOptSets.toSet === optSets.toSet) + + val StackDef = """\s*inst\s+stack_(\d+)\s+of\s+Other.*""".r + val stacks = (0 until 4) map (_.toString) + val foundStacks = for { + StackDef(i) <- lines + } yield i + assert(foundStacks.toSet === stacks.toSet) + + val ListDef = """\s*inst\s+list_(\d+)\s+of\s+Other.*""".r + val lists = (0 until 8) map (_.toString) + val foundLists = for { + ListDef(i) <- lines + } yield i + assert(foundLists.toSet === lists.toSet) + } +} -- cgit v1.2.3