From 32828f3fd64e75a937d67634d60e6e914417ef09 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Mon, 18 Feb 2019 20:06:58 -0500
Subject: Add requirement that Pipe latency >= 0

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 src/main/scala/chisel3/util/Valid.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index df458927..7dcad2c7 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -111,6 +111,7 @@ object Pipe {
     */
   @chiselName
   def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = {
+    require(latency >= 0, "Pipe latency must be greater than or equal to zero!")
     if (latency == 0) {
       val out = Wire(Valid(chiselTypeOf(enqBits)))
       out.valid := enqValid
-- 
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