From 2c53527f6c232121a2340e75c0109c1618fc2428 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 27 Nov 2019 16:29:32 -0800
Subject: Fix bidirectional Wire with Analog (#1252)

---
 src/test/scala/chiselTests/AnalogSpec.scala | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index d81ed009..c443ce7b 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -194,6 +194,27 @@ class AnalogSpec extends ChiselFlatSpec {
     })
   }
 
+  it should "work in bidirectional Aggregate wires" in {
+    class MyBundle extends Bundle {
+      val x = Input(UInt(8.W))
+      val y = Analog(8.W)
+    }
+    elaborate(new Module {
+      val io = IO(new Bundle {
+        val a = new MyBundle
+      })
+      val w = Wire(new MyBundle)
+      w <> io.a
+    })
+    elaborate(new Module {
+      val io = IO(new Bundle {
+        val a = Vec(1, new MyBundle)
+      })
+      val w = Wire(Vec(1, new MyBundle))
+      w <> io.a
+    })
+  }
+
   it should "work with 3 blackboxes attached" in {
     assertTesterPasses(new AnalogTester {
       val mods = Seq.fill(2)(Module(new AnalogReaderBlackBox))
-- 
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