From 2b9b7d3bf58a96b5cb79bbcb1578031e1db953ea Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 30 Jul 2015 17:35:04 -0700
Subject: Add missing Wire()

---
 src/main/scala/Chisel/utils.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/Chisel/utils.scala b/src/main/scala/Chisel/utils.scala
index e3aff994..f1c5e484 100644
--- a/src/main/scala/Chisel/utils.scala
+++ b/src/main/scala/Chisel/utils.scala
@@ -530,7 +530,7 @@ object Pipe
 {
   def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): ValidIO[T] = {
     if (latency == 0) {
-      val out = Valid(enqBits)
+      val out = Wire(Valid(enqBits))
       out.valid <> enqValid
       out.bits <> enqBits
       out
-- 
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