From 2453ac10fae363455398dd1ef5bcdb79e6d23f27 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Tue, 24 May 2022 22:02:52 +0000
Subject: Support Vecs of empty Bundles (#2543) (#2545)

(cherry picked from commit a1e3a6b5324997864168111bee8c02a60abb0acc)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/Vec.scala | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 2eb6ae5f..02743187 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -517,4 +517,26 @@ class VecSpec extends ChiselPropSpec with Utils {
   property("reduceTree should preserve input/output type") {
     assertTesterPasses { new ReduceTreeTester() }
   }
+
+  property("Vecs of empty Bundles and empty Records should work") {
+    class MyModule(gen: Record) extends Module {
+      val idx = IO(Input(UInt(2.W)))
+      val in = IO(Input(gen))
+      val out = IO(Output(gen))
+
+      val reg = RegInit(0.U.asTypeOf(Vec(4, gen)))
+      reg(idx) := in
+      out := reg(idx)
+    }
+    class EmptyBundle extends Bundle
+    class EmptyRecord extends Record {
+      val elements = collection.immutable.ListMap.empty
+      override def cloneType = (new EmptyRecord).asInstanceOf[this.type]
+    }
+    for (gen <- List(new EmptyBundle, new EmptyRecord)) {
+      val chirrtl = ChiselStage.emitChirrtl(new MyModule(gen))
+      chirrtl should include("input in : { }")
+      chirrtl should include("reg reg : { }[4]")
+    }
+  }
 }
-- 
cgit v1.2.3