From 1abb84497315cff795e24afda0e4790fe535132f Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 14 Jan 2019 21:01:16 -0500 Subject: Add chisel3.stage.ChiselStage This adds ChiselStage, a reimplementation of chisel3.Driver as a firrtl.options.Stage. This is simplistically described as a pipeline of Phases. Co-Authored-By: Schuyler Eldridge Co-Authored-By: chick Signed-off-by: Schuyler Eldridge --- src/main/scala/chisel3/stage/ChiselStage.scala | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 src/main/scala/chisel3/stage/ChiselStage.scala (limited to 'src') diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala new file mode 100644 index 00000000..1e92aaf6 --- /dev/null +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -0,0 +1,26 @@ +// See LICENSE for license details. + +package chisel3.stage + +import firrtl.AnnotationSeq +import firrtl.options.{Phase, Shell, Stage} +import firrtl.stage.FirrtlCli + +class ChiselStage extends Stage { + val shell: Shell = new Shell("chisel") with ChiselCli with FirrtlCli + + private val phases: Seq[Phase] = + Seq( new chisel3.stage.phases.Checks, + new chisel3.stage.phases.Elaborate, + new chisel3.stage.phases.AddImplicitOutputFile, + new chisel3.stage.phases.AddImplicitOutputAnnotationFile, + new chisel3.stage.phases.Emitter, + new chisel3.stage.phases.Convert, + new chisel3.stage.phases.MaybeFirrtlStage ) + .map(firrtl.options.phases.DeletedWrapper(_)) + + def run(annotations: AnnotationSeq): AnnotationSeq = + /* @todo: Should this be wrapped in a try/catch? */ + phases.foldLeft(annotations)( (a, f) => f.transform(a) ) + +} -- cgit v1.2.3