From 0f5ba51572b22ff5c85f9dd1add82680e0620797 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 19 Dec 2017 18:20:06 -0800
Subject: Properly invalidate submodule IOs in tests (#745)

---
 src/test/scala/chiselTests/ConnectSpec.scala    | 1 +
 src/test/scala/chiselTests/RecordSpec.scala     | 1 +
 src/test/scala/chiselTests/VectorPacketIO.scala | 3 ++-
 3 files changed, 4 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/ConnectSpec.scala b/src/test/scala/chiselTests/ConnectSpec.scala
index fb0675c4..ac6508ef 100644
--- a/src/test/scala/chiselTests/ConnectSpec.scala
+++ b/src/test/scala/chiselTests/ConnectSpec.scala
@@ -32,6 +32,7 @@ class PipeInternalWires extends Module {
 
 class CrossConnectTester(inType: Data, outType: Data) extends BasicTester {
   val dut = Module(new CrossConnects(inType, outType))
+  dut.io := DontCare
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index 834153a5..2eb7cfc8 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -61,6 +61,7 @@ trait RecordSpecUtils {
 
   class RecordQueueTester extends BasicTester {
     val queue = Module(new Queue(fooBarType, 4))
+    queue.io <> DontCare
     queue.io.enq.valid := false.B
     val (cycle, done) = Counter(true.B, 4)
 
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index ba3664a3..7745db57 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -51,7 +51,8 @@ class BrokenVectorPacketModule extends Module {
 }
 
 class VectorPacketIOUnitTester extends BasicTester {
-  val device_under_test = Module(new BrokenVectorPacketModule)
+  val dut = Module(new BrokenVectorPacketModule)
+  dut.io <> DontCare
 
   // This counter just makes the test end quicker
   val c = Counter(1)
-- 
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