From 0ed5eb48cdb916b644aaf9e5dbf48f6cfb6c60f4 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 7 Sep 2016 14:18:29 -0700
Subject: Add Printable (#270)

Printable is a new type that changes how printing of Chisel types is represented
It uses an ordered collection rather than a format string and specifiers
Features:
 - Custom String Interpolator for Scala-like printf
 - String-like manipulation of "hardware strings" for custom pretty-printing
 - Default pretty-printing for Chisel data types---
 .../scala/chisel3/internal/firrtl/Emitter.scala    |   6 +-
 src/main/scala/chisel3/package.scala               |  51 +++++++
 src/test/scala/chiselTests/PrintableSpec.scala     | 162 +++++++++++++++++++++
 src/test/scala/chiselTests/Printf.scala            |   9 ++
 4 files changed, 227 insertions(+), 1 deletion(-)
 create mode 100644 src/test/scala/chiselTests/PrintableSpec.scala

(limited to 'src')

diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 8b94c68f..8ace27f9 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -25,7 +25,11 @@ private class Emitter(circuit: Circuit) {
       case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
       case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
       case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})"
-      case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})"""
+      case e: Printf =>
+        val (fmt, args) = e.pable.unpack
+        val printfArgs = Seq(e.clk.fullName(ctx), "UInt<1>(1)",
+          "\"" + printf.format(fmt) + "\"") ++ args
+        printfArgs mkString ("printf(", ", ", ")")
       case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
       case e: DefInstance => s"inst ${e.name} of ${e.id.modName}"
       case w: WhenBegin =>
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 0b548683..30e2b5c3 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -54,6 +54,27 @@ package object chisel3 {
   val when = chisel3.core.when
   type WhenContext = chisel3.core.WhenContext
 
+  type Printable = chisel3.core.Printable
+  val Printable = chisel3.core.Printable
+  type Printables = chisel3.core.Printables
+  val Printables = chisel3.core.Printables
+  type PString = chisel3.core.PString
+  val PString = chisel3.core.PString
+  type FirrtlFormat = chisel3.core.FirrtlFormat
+  val FirrtlFormat = chisel3.core.FirrtlFormat
+  type Decimal = chisel3.core.Decimal
+  val Decimal = chisel3.core.Decimal
+  type Hexadecimal = chisel3.core.Hexadecimal
+  val Hexadecimal = chisel3.core.Hexadecimal
+  type Binary = chisel3.core.Binary
+  val Binary = chisel3.core.Binary
+  type Character = chisel3.core.Character
+  val Character = chisel3.core.Character
+  type Name = chisel3.core.Name
+  val Name = chisel3.core.Name
+  type FullName = chisel3.core.FullName
+  val FullName = chisel3.core.FullName
+  val Percent = chisel3.core.Percent
 
   implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
     def U: UInt = UInt(x, Width())
@@ -79,4 +100,34 @@ package object chisel3 {
     def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
     def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
   }
+
+  /** Implicit for custom Printable string interpolator */
+  implicit class PrintableHelper(val sc: StringContext) extends AnyVal {
+    /** Custom string interpolator for generating Printables: p"..."
+      * Will call .toString on any non-Printable arguments (mimicking s"...")
+      */
+    def p(args: Any*): Printable = {
+      sc.checkLengths(args) // Enforce sc.parts.size == pargs.size + 1
+      val pargs: Seq[Option[Printable]] = args map {
+        case p: Printable => Some(p)
+        case d: Data => Some(d.toPrintable)
+        case any => for {
+          v <- Option(any) // Handle null inputs
+          str = v.toString
+          if !str.isEmpty // Handle empty Strings
+        } yield PString(str)
+      }
+      val parts = sc.parts map StringContext.treatEscapes
+      // Zip sc.parts and pargs together ito flat Seq
+      // eg. Seq(sc.parts(0), pargs(0), sc.parts(1), pargs(1), ...)
+      val seq = for { // append None because sc.parts.size == pargs.size + 1
+        (literal, arg) <- parts zip (pargs :+ None)
+        optPable <- Seq(Some(PString(literal)), arg)
+        pable <- optPable // Remove Option[_]
+      } yield pable
+      Printables(seq)
+    }
+  }
+
+  implicit def string2Printable(str: String): Printable = PString(str)
 }
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
new file mode 100644
index 00000000..a2c8c62a
--- /dev/null
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -0,0 +1,162 @@
+package chiselTests
+
+import org.scalatest.{FlatSpec, Matchers}
+import scala.collection.mutable
+
+import chisel3._
+import chisel3.testers.BasicTester
+
+/* Printable Tests */
+class PrintableSpec extends FlatSpec with Matchers {
+  private val PrintfRegex = """\s*printf\((.*)\).*""".r
+  // This regex is brittle, it relies on the first two arguments of the printf
+  // not containing quotes, problematic if Chisel were to emit UInt<1>("h01")
+  // instead of the current UInt<1>(1) for the enable signal
+  private val StringRegex = """([^"]*)"(.*?)"(.*)""".r
+  private case class Printf(str: String, args: Seq[String])
+  private def getPrintfs(firrtl: String): Seq[Printf] = {
+    def processArgs(str: String): Seq[String] =
+      str split "," map (_.trim) filter (_.nonEmpty)
+    def processBody(str: String): (String, Seq[String]) = {
+      str match {
+        case StringRegex(_, fmt, args) =>
+          (fmt, processArgs(args))
+        case _ => fail(s"Regex to process Printf should work on $str!")
+      }
+    }
+
+    firrtl split "\n" collect {
+      case PrintfRegex(matched) =>
+        val (str, args) = processBody(matched)
+        Printf(str, args)
+    }
+  }
+
+  behavior of "Printable & Custom Interpolator"
+
+  it should "pass exact strings through" in {
+    class MyModule extends BasicTester {
+      printf(p"An exact string")
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("An exact string", Seq())) =>
+      case e => fail()
+    }
+  }
+  it should "handle Printable and String concatination" in {
+    class MyModule extends BasicTester {
+      printf(p"First " + PString("Second ") + "Third")
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("First Second Third", Seq())) =>
+      case e => fail()
+    }
+  }
+  it should "call toString on non-Printable objects" in {
+    class MyModule extends BasicTester {
+      val myInt = 1234
+      printf(p"myInt = $myInt")
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("myInt = 1234", Seq())) =>
+      case e => fail()
+    }
+  }
+  it should "generate proper printf for simple Decimal printing" in {
+    class MyModule extends BasicTester {
+      val myWire = Wire(init = UInt(1234))
+      printf(p"myWire = ${Decimal(myWire)}")
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("myWire = %d", Seq("myWire"))) =>
+      case e => fail()
+    }
+  }
+  it should "handle printing literals" in {
+    class MyModule extends BasicTester {
+      printf(Decimal(UInt(10, 32)))
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("%d", Seq(lit))) =>
+        assert(lit contains "UInt<32>")
+      case e => fail()
+    }
+  }
+  it should "correctly escape percent" in {
+    class MyModule extends BasicTester {
+      printf(p"%")
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("%%", Seq())) =>
+      case e => fail()
+    }
+  }
+  it should "support names of circuit elements and the current module" in {
+    class MyBundle extends Bundle {
+      val foo = UInt(width = 32)
+      override def cloneType = (new MyBundle).asInstanceOf[this.type]
+    }
+    class MyModule extends BasicTester {
+      override def desiredName = "MyModule"
+      val myWire = Wire(new MyBundle)
+      printf(p"${Name(myWire.foo)}")
+      printf(p"${FullName(myWire.foo)}")
+      printf(p"${FullName(this)}")
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("foo", Seq()),
+               Printf("myWire.foo", Seq()),
+               Printf("MyModule", Seq())) =>
+      case e => fail()
+    }
+  }
+  it should "print UInts and SInts as Decimal by default" in {
+    class MyModule extends BasicTester {
+      val myUInt = Wire(init = UInt(0))
+      val mySInt = Wire(init = SInt(-1))
+      printf(p"$myUInt & $mySInt")
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("%d & %d", Seq("myUInt", "mySInt"))) =>
+      case e => fail()
+    }
+  }
+  it should "print Vecs like Scala Seqs by default" in {
+    class MyModule extends BasicTester {
+      val myVec = Wire(Vec(4, UInt(width = 32)))
+      myVec foreach (_ := UInt(0))
+      printf(p"$myVec")
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("Vec(%d, %d, %d, %d)",
+               Seq("myVec[0]", "myVec[1]", "myVec[2]", "myVec[3]"))) =>
+      case e => fail()
+    }
+  }
+  it should "print Bundles like Scala Maps by default" in {
+    class MyModule extends BasicTester {
+      val myBun = Wire(new Bundle {
+        val foo = UInt(width = 32)
+        val bar = UInt(width = 32)
+      })
+      myBun.foo := UInt(0)
+      myBun.bar := UInt(0)
+      printf(p"$myBun")
+    }
+    val firrtl = Driver.emit(() => new MyModule)
+    getPrintfs(firrtl) match {
+      case Seq(Printf("Bundle(foo -> %d, bar -> %d)",
+               Seq("myBun.foo", "myBun.bar"))) =>
+      case e => fail()
+    }
+  }
+}
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index c872fde4..28b6132b 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import org.scalatest._
 import chisel3._
+import chisel3.util._
 import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
@@ -24,6 +25,11 @@ class MultiPrintfTester() extends BasicTester {
   stop()
 }
 
+class ASCIIPrintableTester extends BasicTester {
+  printf(PString((0x20 to 0x7e) map (_.toChar) mkString ""))
+  stop()
+}
+
 class PrintfSpec extends ChiselFlatSpec {
   "A printf with a single argument" should "run" in {
     assertTesterPasses { new SinglePrintfTester }
@@ -34,4 +40,7 @@ class PrintfSpec extends ChiselFlatSpec {
   "A printf with ASCII characters 1-127" should "run" in {
     assertTesterPasses { new ASCIIPrintfTester }
   }
+  "A printf with Printable ASCII characters 1-127" should "run" in {
+    assertTesterPasses { new ASCIIPrintableTester }
+  }
 }
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