From 0ac473b5f80b9627a06fc5caa052899680fd13cb Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 3 May 2019 13:00:05 -0400 Subject: Add chisel3.stage.phases.MaybeFirrtlStage Signed-off-by: Schuyler Eldridge --- .../scala/chisel3/stage/phases/MaybeFirrtlStage.scala | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala (limited to 'src') diff --git a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala new file mode 100644 index 00000000..f830c182 --- /dev/null +++ b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala @@ -0,0 +1,19 @@ +// See LICENSE for license details. + +package chisel3.stage.phases + +import chisel3.stage.NoRunFirrtlCompilerAnnotation + +import firrtl.AnnotationSeq +import firrtl.options.Phase +import firrtl.stage.FirrtlStage + +/** Run [[firrtl.stage.FirrtlStage]] if a [[chisel3.stage.NoRunFirrtlCompilerAnnotation]] is not present. + */ +class MaybeFirrtlStage extends Phase { + + def transform(annotations: AnnotationSeq): AnnotationSeq = annotations + .collectFirst { case NoRunFirrtlCompilerAnnotation => annotations } + .getOrElse { (new FirrtlStage).transform(annotations) } + +} -- cgit v1.2.3