From 0a8ffcb856da4007d1a39503c629295bee42acfb Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Thu, 10 Jan 2019 12:47:37 -0500
Subject: Add chisel3.stage.ChiselCli

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 src/main/scala/chisel3/stage/ChiselCli.scala | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 src/main/scala/chisel3/stage/ChiselCli.scala

(limited to 'src')

diff --git a/src/main/scala/chisel3/stage/ChiselCli.scala b/src/main/scala/chisel3/stage/ChiselCli.scala
new file mode 100644
index 00000000..4f7ac19e
--- /dev/null
+++ b/src/main/scala/chisel3/stage/ChiselCli.scala
@@ -0,0 +1,12 @@
+// See LICENSE for license details.
+
+package chisel3.stage
+
+import firrtl.options.Shell
+
+trait ChiselCli { this: Shell =>
+  parser.note("Chisel Front End Options")
+  Seq( NoRunFirrtlCompilerAnnotation,
+       PrintFullStackTraceAnnotation )
+    .foreach(_.addOptions(parser))
+}
-- 
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