From 089987c3e0b2bc390935a4d9d44db38a18c47901 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 10:29:13 -0700
Subject: Correct EnqIO/DeqIO Flipped-ness.

---
 src/test/scala/chiselTests/VectorPacketIO.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 86c0d66f..b8e3a154 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -41,8 +41,8 @@ class BrokenVectorPacketModule extends Module {
   val io = IO(new VectorPacketIO(n))
 
   /* the following method of initializing the circuit may change in the future */
-  io.ins.foreach(_.noenq())
-  io.outs.foreach(_.nodeq())
+  io.ins.foreach(_.nodeq())
+  io.outs.foreach(_.noenq())
 }
 
 class VectorPacketIOUnitTester extends BasicTester {
-- 
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