From e27657118ff5915b96f8e3a467d464245fe09769 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 20 Dec 2017 15:54:25 -0800
Subject: Add compileOptions to Module.apply, use for invalidating submod ports
 (#747)

Fixes #746
Also add test for https://github.com/freechipsproject/firrtl/issues/705
---
 .../CompatibilityInteroperabilitySpec.scala        | 22 ++++++++++++++++++++++
 src/test/scala/chiselTests/Util.scala              | 22 ++++++++++++++++++++++
 src/test/scala/chiselTests/Vec.scala               | 11 +----------
 src/test/scala/chiselTests/When.scala              | 20 ++++++++++++++++++++
 4 files changed, 65 insertions(+), 10 deletions(-)
 create mode 100644 src/test/scala/chiselTests/Util.scala

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index c0538123..457f26de 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -217,5 +217,27 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
       stop()
     })
   }
+
+  "An instance of a chisel3.Module inside a Chisel.Module" should "have its inputs invalidated" in {
+    compile {
+      import Chisel._
+      new Module {
+        val io = new Bundle {
+          val in = UInt(INPUT, width = 32)
+          val cond = Bool(INPUT)
+          val out = UInt(OUTPUT, width = 32)
+        }
+        val children = Seq(Module(new PassthroughModule),
+                           Module(new PassthroughMultiIOModule),
+                           Module(new PassthroughRawModule))
+        io.out := children.map(_.io.out).reduce(_ + _)
+        children.foreach { child =>
+          when (io.cond) {
+            child.io.in := io.in
+          }
+        }
+      }
+    }
+  }
 }
 
diff --git a/src/test/scala/chiselTests/Util.scala b/src/test/scala/chiselTests/Util.scala
new file mode 100644
index 00000000..80e37285
--- /dev/null
+++ b/src/test/scala/chiselTests/Util.scala
@@ -0,0 +1,22 @@
+// Useful utilities for tests
+
+package chiselTests
+
+import chisel3._
+import chisel3.experimental._
+
+class PassthroughModuleIO extends Bundle {
+  val in = Input(UInt(32.W))
+  val out = Output(UInt(32.W))
+}
+
+trait AbstractPassthroughModule extends RawModule {
+  val io = IO(new PassthroughModuleIO)
+  io.out := io.in
+}
+
+class PassthroughModule extends Module with AbstractPassthroughModule
+class PassthroughMultiIOModule extends MultiIOModule with AbstractPassthroughModule
+class PassthroughRawModule extends RawModule with AbstractPassthroughModule
+
+
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 08b9cdf5..bf25ed82 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -3,6 +3,7 @@
 package chiselTests
 
 import chisel3._
+import chisel3.experimental.RawModule
 import chisel3.core.Binding.BindingException
 import chisel3.testers.BasicTester
 import chisel3.util._
@@ -153,16 +154,6 @@ class ZeroEntryVecTester extends BasicTester {
   stop()
 }
 
-class PassthroughModuleIO extends Bundle {
-  val in = Input(UInt(32.W))
-  val out = Output(UInt(32.W))
-}
-
-class PassthroughModule extends Module {
-  val io = IO(new PassthroughModuleIO)
-  io.out := io.in
-}
-
 class PassthroughModuleTester extends Module {
   val io = IO(Flipped(new PassthroughModuleIO))
   // This drives the input of a PassthroughModule
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 3bd63831..a1a7afb7 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -76,6 +76,23 @@ class NoOtherwiseOverlappedWhenTester() extends BasicTester {
   }
 }
 
+class SubmoduleWhenTester extends BasicTester {
+  val (cycle, done) = Counter(true.B, 3)
+  when (done) { stop() }
+  val children = Seq(Module(new PassthroughModule),
+                     Module(new PassthroughMultiIOModule),
+                     Module(new PassthroughRawModule))
+  children.foreach { child =>
+    when (cycle === 1.U) {
+      child.io.in := "hdeadbeef".U
+      assert(child.io.out === "hdeadbeef".U)
+    } .otherwise {
+      child.io.in := "h0badcad0".U
+      assert(child.io.out === "h0badcad0".U)
+    }
+  }
+}
+
 class WhenSpec extends ChiselFlatSpec {
   "When, elsewhen, and otherwise with orthogonal conditions" should "work" in {
     assertTesterPasses{ new WhenTester }
@@ -86,4 +103,7 @@ class WhenSpec extends ChiselFlatSpec {
   "When and elsewhen without otherwise with overlapped conditions" should "work" in {
     assertTesterPasses{ new NoOtherwiseOverlappedWhenTester }
   }
+  "Conditional connections to submodule ports" should "be handled properly" in {
+    assertTesterPasses(new SubmoduleWhenTester)
+  }
 }
-- 
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