From d675043717593fb7e96fb0f1952debbeb7f20a57 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 21 Jun 2016 09:17:30 -0700
Subject: New Module, IO, Input/Output wrapping.

---
 src/test/scala/chiselTests/Assert.scala            |  2 +-
 src/test/scala/chiselTests/BundleWire.scala        |  8 ++---
 src/test/scala/chiselTests/Decoder.scala           |  8 ++---
 src/test/scala/chiselTests/DeqIOSpec.scala         | 11 ++++---
 .../scala/chiselTests/EnableShiftRegister.scala    | 10 +++---
 src/test/scala/chiselTests/LFSR16.scala            |  8 ++---
 src/test/scala/chiselTests/Module.scala            | 22 ++++++-------
 src/test/scala/chiselTests/OptionBundle.scala      |  6 ++--
 .../scala/chiselTests/ParameterizedModule.scala    |  8 ++---
 src/test/scala/chiselTests/Risc.scala              | 16 +++++-----
 src/test/scala/chiselTests/SIntOps.scala           | 36 +++++++++++-----------
 src/test/scala/chiselTests/Tbl.scala               | 14 ++++-----
 src/test/scala/chiselTests/Vec.scala               | 30 ------------------
 src/test/scala/chiselTests/VendingMachine.scala    |  9 +++---
 14 files changed, 80 insertions(+), 108 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 24eb8b55..750ed6e4 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -25,7 +25,7 @@ class SucceedingAssertTester() extends BasicTester {
 }
 
 class PipelinedResetModule extends Module {
-  val io = new Bundle { }
+  val io = IO(new Bundle { })
   val a = Reg(init = UInt(0xbeef))
   val b = Reg(init = UInt(0xbeef))
   assert(a === b)
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index d2e42fa9..147575e1 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -12,10 +12,10 @@ class Coord extends Bundle {
 }
 
 class BundleWire(n: Int) extends Module {
-  val io = new Bundle {
-    val in   = (new Coord).asInput
-    val outs = Vec(n, new Coord).asOutput
-  }
+  val io = IO(new Bundle {
+    val in   = Input(new Coord)
+    val outs = Output(Vec(n, new Coord))
+  })
   val coords = Wire(Vec(n, new Coord))
   for (i <- 0 until n) {
     coords(i)  := io.in
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index e5cdfd07..07622667 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -8,10 +8,10 @@ import org.scalacheck._
 import Chisel.testers.BasicTester
 
 class Decoder(bitpats: List[String]) extends Module {
-  val io = new Bundle {
-    val inst  = UInt(INPUT, 32)
-    val matched = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val inst  = Input(UInt(32))
+    val matched = Output(Bool())
+  })
   io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
 }
 
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 8f7937ab..38e00690 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -15,17 +15,17 @@ class UsesDeqIOInfo extends Bundle {
 }
 
 class UsesDeqIO extends Module {
-  val io = new Bundle {
-    val in = new DeqIO(new UsesDeqIOInfo)
-    val out = new EnqIO(new UsesDeqIOInfo)
-  }
+  val io = IO(new Bundle {
+    val in = DeqIO(new UsesDeqIOInfo)
+    val out = EnqIO(new UsesDeqIOInfo)
+  })
 }
 
 class DeqIOSpec extends ChiselFlatSpec {
   runTester {
     new BasicTester {
       val dut = new UsesDeqIO
-
+/*
       "DeqIO" should "set the direction of it's parameter to INPUT" in {
         assert(dut.io.in.bits.info_data.dir === INPUT)
       }
@@ -55,6 +55,7 @@ class DeqIOSpec extends ChiselFlatSpec {
         assert(dut.io.out.ready.dir == out_clone.ready.dir)
         assert(dut.io.out.valid.dir == out_clone.valid.dir)
       }
+      */
     }
   }
 }
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 6600df2a..11e8b70b 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -5,11 +5,11 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class EnableShiftRegister extends Module {
-  val io = new Bundle {
-    val in    = UInt(INPUT, 4)
-    val shift = Bool(INPUT)
-    val out   = UInt(OUTPUT, 4)
-  }
+  val io = IO(new Bundle {
+    val in    = Input(UInt(4))
+    val shift = Input(Bool())
+    val out   = Output(UInt(4))
+  })
   val r0 = Reg(init = UInt(0, 4))
   val r1 = Reg(init = UInt(0, 4))
   val r2 = Reg(init = UInt(0, 4))
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index ed76a296..54144bea 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -5,10 +5,10 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class LFSR16 extends Module {
-  val io = new Bundle {
-    val inc = Bool(INPUT)
-    val out = UInt(OUTPUT, 16)
-  }
+  val io = IO(new Bundle {
+    val inc = Input(Bool())
+    val out = Output(UInt(16))
+  })
   val res = Reg(init = UInt(1, 16))
   when (io.inc) {
     val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 88ba795b..ba251916 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -4,20 +4,20 @@ package chiselTests
 import Chisel._
 
 class SimpleIO extends Bundle {
-  val in  = UInt(INPUT,  32)
-  val out = UInt(OUTPUT, 32)
+  val in  = Input(UInt(32))
+  val out = Output(UInt(32))
 }
 
 class PlusOne extends Module {
-  val io = new SimpleIO
+  val io = IO(new SimpleIO)
   io.out := io.in + UInt(1)
 }
 
 class ModuleVec(val n: Int) extends Module {
-  val io = new Bundle {
-    val ins  = Vec(n, UInt(INPUT,  32))
-    val outs = Vec(n, UInt(OUTPUT, 32))
-  }
+  val io = IO(new Bundle {
+    val ins  = Input(Vec(n, UInt(32)))
+    val outs = Output(Vec(n, UInt(32)))
+  })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
     pluses(i).in := io.ins(i)
@@ -39,8 +39,8 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
 */
 
 class ModuleWire extends Module {
-  val io = new SimpleIO
-  val inc = Wire(Module(new PlusOne).io)
+  val io = IO(new SimpleIO)
+  val inc = Wire(Module(new PlusOne).io.newType)
   inc.in := io.in
   io.out := inc.out
 }
@@ -57,10 +57,10 @@ class ModuleWireTester(c: ModuleWire) extends Tester(c) {
 */
 
 class ModuleWhen extends Module {
-  val io = new Bundle {
+  val io = IO(new Bundle {
     val s = new SimpleIO
     val en = Bool()
-  }
+  })
   when(io.en) {
     val inc = Module(new PlusOne).io
     inc.in := io.s.in
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index c5a347e6..ad694925 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -8,15 +8,15 @@ import Chisel.testers.BasicTester
 
 class OptionBundle(hasIn: Boolean) extends Bundle {
   val in = if (hasIn) {
-    Some(Bool(INPUT))
+    Some(Input(Bool()))
   } else {
     None
   }
-  val out = Bool(OUTPUT)
+  val out = Output(Bool())
 }
 
 class OptionBundleModule(hasIn: Boolean) extends Module {
-  val io = new OptionBundle(hasIn)
+  val io = IO(new OptionBundle(hasIn))
   if (hasIn) {
     io.out := io.in.get
   } else {
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index 35e3ba78..f682f310 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -7,10 +7,10 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class ParameterizedModule(invert: Boolean) extends Module {
-  val io = new Bundle {
-    val in = new Bool(INPUT)
-    val out = new Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val in  = Input(Bool())
+    val out = Output(Bool())
+  })
   if (invert) {
     io.out := !io.in
   } else {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 3daa5bd2..670aa703 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -4,14 +4,14 @@ package chiselTests
 import Chisel._
 
 class Risc extends Module {
-  val io = new Bundle {
-    val isWr   = Bool(INPUT)
-    val wrAddr = UInt(INPUT, 8)
-    val wrData = Bits(INPUT, 32)
-    val boot   = Bool(INPUT)
-    val valid  = Bool(OUTPUT)
-    val out    = Bits(OUTPUT, 32)
-  }
+  val io = IO(new Bundle {
+    val isWr   = Input(Bool())
+    val wrAddr = Input(UInt(8))
+    val wrData = Input(Bits(32))
+    val boot   = Input(Bool())
+    val valid  = Output(Bool())
+    val out    = Output(Bits(32))
+  })
   val memSize = 256
   val file = Mem(memSize, Bits(width = 32))
   val code = Mem(memSize, Bits(width = 32))
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 0835fb4d..934c66a4 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -5,24 +5,24 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class SIntOps extends Module {
-  val io = new Bundle {
-    val a = SInt(INPUT, 16)
-    val b = SInt(INPUT, 16)
-    val addout = SInt(OUTPUT, 16)
-    val subout = SInt(OUTPUT, 16)
-    val timesout = SInt(OUTPUT, 16)
-    val divout = SInt(OUTPUT, 16)
-    val modout = SInt(OUTPUT, 16)
-    val lshiftout = SInt(OUTPUT, 16)
-    val rshiftout = SInt(OUTPUT, 16)
-    val lessout = Bool(OUTPUT)
-    val greatout = Bool(OUTPUT)
-    val eqout = Bool(OUTPUT)
-    val noteqout = Bool(OUTPUT)
-    val lesseqout = Bool(OUTPUT)
-    val greateqout = Bool(OUTPUT)
-    val negout = SInt(OUTPUT, 16)
-  }
+  val io = IO(new Bundle {
+    val a = Input(SInt(16))
+    val b = Input(SInt(16))
+    val addout = Output(SInt(16))
+    val subout = Output(SInt(16))
+    val timesout = Output(SInt(16))
+    val divout = Output(SInt(16))
+    val modout = Output(SInt(16))
+    val lshiftout = Output(SInt(16))
+    val rshiftout = Output(SInt(16))
+    val lessout = Output(Bool())
+    val greatout = Output(Bool())
+    val eqout = Output(Bool())
+    val noteqout = Output(Bool())
+    val lesseqout = Output(Bool())
+    val greateqout = Output(Bool())
+    val negout = Output(SInt(16))
+  })
 
   val a = io.a
   val b = io.b
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index c79eb8a4..751dc127 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -8,13 +8,13 @@ import org.scalatest.prop._
 import Chisel.testers.BasicTester
 
 class Tbl(w: Int, n: Int) extends Module {
-  val io = new Bundle {
-    val wi  = UInt(INPUT, log2Up(n))
-    val ri  = UInt(INPUT, log2Up(n))
-    val we  = Bool(INPUT)
-    val  d  = UInt(INPUT, w)
-    val  o  = UInt(OUTPUT, w)
-  }
+  val io = IO(new Bundle {
+    val wi  = Input(UInt(log2Up(n)))
+    val ri  = Input(UInt(log2Up(n)))
+    val we  = Input(Bool())
+    val  d  = Input(UInt(w))
+    val  o  = Output(UInt(w))
+  })
   val m = Mem(n, UInt(width = w))
   io.o := m(io.ri)
   when (io.we) {
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 943d9e4b..5239c6ba 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -41,32 +41,6 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
   }
 }
 
-class FunBundle extends Bundle {
-  val stuff = UInt(width = 10)
-}
-
-class ZeroModule extends Module {
-  val io = new Bundle {
-    val mem = UInt(width = 10)
-    val interrupts = Vec(2, Bool()).asInput
-    val mmio_axi = Vec(0, new FunBundle)
-    val mmio_ahb = Vec(0, new FunBundle).flip
-  }
-  
-  io.mmio_axi <> io.mmio_ahb
-  
-  io.mem := UInt(0)
-  when (io.interrupts(0)) { io.mem := UInt(1) }
-  when (io.interrupts(1)) { io.mem := UInt(2) }
-}
-
-class ZeroTester extends BasicTester {
-  val foo = Module(new ZeroModule)
-  foo.io.interrupts := Vec.tabulate(2) { _ => Bool(true) }
-  assert (foo.io.mem === UInt(2))
-  stop()
-}
-
 class VecSpec extends ChiselPropSpec {
   property("Vecs should be assignable") {
     forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) =>
@@ -81,8 +55,4 @@ class VecSpec extends ChiselPropSpec {
   property("Regs of vecs should be usable as shift registers") {
     forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } }
   }
-  
-  property("Dual empty Vectors") {
-    assertTesterPasses{ new ZeroTester }
-  }
 }
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 012fc493..5baff275 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -4,10 +4,11 @@ package chiselTests
 import Chisel._
 
 class VendingMachine extends Module {
-  val io = new Bundle {
-    val nickel = Bool(dir = INPUT)
-    val dime   = Bool(dir = INPUT)
-    val valid  = Bool(dir = OUTPUT) }
+  val io = IO(new Bundle {
+    val nickel = Input(Bool())
+    val dime   = Input(Bool())
+    val valid  = Output(Bool())
+  })
   val c = UInt(5, width = 3)
   val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
   val state = Reg(init = sIdle)
-- 
cgit v1.2.3


From 083610b2faa456dfccc4365dd115565d36e522fa Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 21 Jun 2016 10:13:51 -0700
Subject: Most of the remaining tests with Module, IO wrapping.

---
 src/test/scala/chiselTests/BlackBox.scala       | 32 ++++++++--------
 src/test/scala/chiselTests/ComplexAssign.scala  | 10 ++---
 src/test/scala/chiselTests/Direction.scala      |  8 ++--
 src/test/scala/chiselTests/GCD.scala            | 14 +++----
 src/test/scala/chiselTests/MemorySearch.scala   | 12 +++---
 src/test/scala/chiselTests/MulLookup.scala      | 10 ++---
 src/test/scala/chiselTests/Padding.scala        | 10 ++---
 src/test/scala/chiselTests/Stack.scala          | 14 +++----
 src/test/scala/chiselTests/UIntOps.scala        | 50 ++++++++++++-------------
 src/test/scala/chiselTests/VectorPacketIO.scala |  9 +++--
 10 files changed, 85 insertions(+), 84 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index ca94087c..5877149f 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -8,25 +8,25 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class BlackBoxInverter extends BlackBox {
-  val io = new Bundle() {
-    val in = Bool(INPUT)
-    val out = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle() {
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
 }
 
 class BlackBoxPassthrough extends BlackBox {
-  val io = new Bundle() {
-    val in = Bool(INPUT)
-    val out = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle() {
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
 }
 
 class BlackBoxRegister extends BlackBox {
-  val io = new Bundle() {
-    val clock = Clock().asInput
-    val in = Bool(INPUT)
-    val out = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle() {
+    val clock = Input(Clock())
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
 }
 
 class BlackBoxTester extends BasicTester {
@@ -84,9 +84,9 @@ class BlackBoxWithClockTester extends BasicTester {
 /*
 // Must determine how to handle parameterized Verilog
 class BlackBoxConstant(value: Int) extends BlackBox {
-  val io = new Bundle() {
-    val out = UInt(width=log2Up(value)).asOutput
-  }
+  val io = IO(new Bundle() {
+    val out = Output(UInt(width=log2Up(value)))
+  })
   override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) "
 }
 
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index d79a2625..58f26c1f 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -13,11 +13,11 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
 }
 
 class ComplexAssign(w: Int) extends Module {
-  val io = new Bundle {
-    val e   = new Bool(INPUT)
-    val in  = new Complex(UInt(width = w), UInt(width = w)).asInput
-    val out = new Complex(UInt(width = w), UInt(width = w)).asOutput
-  }
+  val io = IO(new Bundle {
+    val e   = Input(Bool())
+    val in  = Input(new Complex(UInt(width = w), UInt(width = w)))
+    val out = Output(new Complex(UInt(width = w), UInt(width = w)))
+  })
   when (io.e) {
     val tmp = Wire(new Complex(UInt(width = w), UInt(width = w)))
     tmp := io.in
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index dd2f6572..28b00adb 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -8,10 +8,10 @@ import org.scalatest.prop._
 import Chisel.testers.BasicTester
 
 class DirectionHaver extends Module {
-  val io = new Bundle {
-    val in = UInt(INPUT, 32)
-    val out = UInt(OUTPUT, 32)
-  }
+  val io = IO(new Bundle {
+    val in = Input(UInt(32))
+    val out = Output(UInt(32))
+  })
 }
 
 class GoodDirection extends DirectionHaver {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index a1bfffda..edb8c80f 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -8,13 +8,13 @@ import org.scalatest._
 import org.scalatest.prop._
 
 class GCD extends Module {
-  val io = new Bundle {
-    val a  = UInt(INPUT, 32)
-    val b  = UInt(INPUT, 32)
-    val e  = Bool(INPUT)
-    val z  = UInt(OUTPUT, 32)
-    val v  = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val a  = Input(UInt(32))
+    val b  = Input(UInt(32))
+    val e  = Input(Bool())
+    val z  = Output(UInt(32))
+    val v  = Output(Bool())
+  })
   val x = Reg(UInt(width = 32))
   val y = Reg(UInt(width = 32))
   when (x > y)   { x := x -% y }
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 55b704a0..a321522b 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -5,12 +5,12 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class MemorySearch extends Module {
-  val io = new Bundle {
-    val target  = UInt(INPUT,  4)
-    val en      = Bool(INPUT)
-    val done    = Bool(OUTPUT)
-    val address = UInt(OUTPUT, 3)
-  }
+  val io = IO(new Bundle {
+    val target  = Input(UInt(4))
+    val en      = Input(Bool())
+    val done    = Output(Bool())
+    val address = Output(UInt(3))
+  })
   val vals  = Array(0, 4, 15, 14, 2, 5, 13)
   val index = Reg(init = UInt(0, width = 3))
   val elts  = Vec(vals.map(UInt(_,4)))
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 49ba13c7..1e5ee798 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -8,11 +8,11 @@ import org.scalatest.prop._
 import Chisel.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
-  val io = new Bundle {
-    val x   = UInt(INPUT,  w)
-    val y   = UInt(INPUT,  w)
-    val z   = UInt(OUTPUT, 2 * w)
-  }
+  val io = IO(new Bundle {
+    val x   = Input(UInt(w))
+    val y   = Input(UInt(w))
+    val z   = Output(UInt(2 * w))
+  })
   val tbl = Vec(
     for {
       i <- 0 until 1 << w
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 999b7d36..1f33f8ab 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -4,11 +4,11 @@ package chiselTests
 import Chisel._
 
 class Padder extends Module {
-  val io = new Bundle {
-    val a   = Bits(INPUT,  4)
-    val asp = SInt(OUTPUT, 8)
-    val aup = UInt(OUTPUT, 8)
-  }
+  val io = IO(new Bundle {
+    val a   = Input(UInt(4))
+    val asp = Output(SInt(8))
+    val aup = Output(UInt(8))
+  })
   io.asp := io.a.asSInt
   io.aup := io.a.asUInt
 }
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ac799c8a..46e5dc23 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -5,13 +5,13 @@ import scala.collection.mutable.Stack
 import Chisel._
 
 class ChiselStack(val depth: Int) extends Module {
-  val io = new Bundle {
-    val push    = Bool(INPUT)
-    val pop     = Bool(INPUT)
-    val en      = Bool(INPUT)
-    val dataIn  = UInt(INPUT,  32)
-    val dataOut = UInt(OUTPUT, 32)
-  }
+  val io = IO(new Bundle {
+    val push    = Input(Bool())
+    val pop     = Input(Bool())
+    val en      = Input(Bool())
+    val dataIn  = Input(UInt(32))
+    val dataOut = Output(UInt(32))
+  })
 
   val stack_mem = Mem(depth, UInt(width = 32))
   val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index bb0b0f06..4e8506cf 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -6,23 +6,23 @@ import org.scalatest._
 import Chisel.testers.BasicTester
 
 class UIntOps extends Module {
-  val io = new Bundle {
-    val a = UInt(INPUT, 16)
-    val b = UInt(INPUT, 16)
-    val addout = UInt(OUTPUT, 16)
-    val subout = UInt(OUTPUT, 16)
-    val timesout = UInt(OUTPUT, 16)
-    val divout = UInt(OUTPUT, 16)
-    val modout = UInt(OUTPUT, 16)
-    val lshiftout = UInt(OUTPUT, 16)
-    val rshiftout = UInt(OUTPUT, 16)
-    val lessout = Bool(OUTPUT)
-    val greatout = Bool(OUTPUT)
-    val eqout = Bool(OUTPUT)
-    val noteqout = Bool(OUTPUT)
-    val lesseqout = Bool(OUTPUT)
-    val greateqout = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val a = Input(UInt(16))
+    val b = Input(UInt(16))
+    val addout = Output(UInt(16))
+    val subout = Output(UInt(16))
+    val timesout = Output(UInt(16))
+    val divout = Output(UInt(16))
+    val modout = Output(UInt(16))
+    val lshiftout = Output(UInt(16))
+    val rshiftout = Output(UInt(16))
+    val lessout = Output(Bool())
+    val greatout = Output(Bool())
+    val eqout = Output(Bool())
+    val noteqout = Output(Bool())
+    val lesseqout = Output(Bool())
+    val greateqout = Output(Bool())
+  })
 
   val a = io.a
   val b = io.b
@@ -76,18 +76,18 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) {
 */
 
 class GoodBoolConversion extends Module {
-  val io = new Bundle {
-    val u = UInt(1, width = 1).asInput
-    val b = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val u = Input(UInt(1))
+    val b = Output(Bool())
+  })
   io.b := io.u.toBool
 }
 
 class BadBoolConversion extends Module {
-  val io = new Bundle {
-    val u = UInt(1, width = 5).asInput
-    val b = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val u = Input(UInt(width = 5))
+    val b = Output(Bool())
+  })
   io.b := io.u.toBool
 }
 
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 99ec66a6..936541c0 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -27,8 +27,8 @@ class Packet extends Bundle {
   * The problem does not occur if the Vec is taken out
   */
 class VectorPacketIO(n: Int) extends Bundle {
-  val ins  = Vec(n, new DeqIO(new Packet()))
-  val outs = Vec(n, new EnqIO(new Packet()))
+  val ins  = Vec(n, DeqIO(new Packet()))
+  val outs = Vec(n, EnqIO(new Packet()))
 }
 
 /**
@@ -37,10 +37,11 @@ class VectorPacketIO(n: Int) extends Bundle {
   */
 class BrokenVectorPacketModule extends Module {
   val n  = 4
-  val io = new VectorPacketIO(n)
+  val io = IO(new VectorPacketIO(n))
 
   /* the following method of initializing the circuit may change in the future */
-  io.outs.foreach(_.init())
+  io.ins.foreach(_.noenq())
+  io.outs.foreach(_.nodeq())
 }
 
 class VectorPacketIOUnitTester extends BasicTester {
-- 
cgit v1.2.3


From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 09:31:47 -0700
Subject: Update Chisel -> chisel3 references.

---
 src/test/scala/chiselTests/Assert.scala            |  5 +++--
 src/test/scala/chiselTests/BitwiseOps.scala        |  4 ++--
 src/test/scala/chiselTests/BlackBox.scala          |  6 ++++--
 src/test/scala/chiselTests/BundleWire.scala        |  4 ++--
 src/test/scala/chiselTests/ChiselSpec.scala        |  4 ++--
 src/test/scala/chiselTests/ComplexAssign.scala     |  6 ++++--
 src/test/scala/chiselTests/Counter.scala           |  7 +++++--
 src/test/scala/chiselTests/Decoder.scala           |  7 +++++--
 src/test/scala/chiselTests/DeqIOSpec.scala         |  5 +++--
 src/test/scala/chiselTests/Direction.scala         |  4 ++--
 .../scala/chiselTests/EnableShiftRegister.scala    |  4 ++--
 src/test/scala/chiselTests/GCD.scala               |  4 ++--
 src/test/scala/chiselTests/Harness.scala           |  5 +++--
 src/test/scala/chiselTests/LFSR16.scala            |  8 +++++---
 src/test/scala/chiselTests/MemorySearch.scala      |  5 +++--
 src/test/scala/chiselTests/Module.scala            |  3 ++-
 src/test/scala/chiselTests/MulLookup.scala         |  4 ++--
 src/test/scala/chiselTests/MultiAssign.scala       | 22 ++++++++++++----------
 src/test/scala/chiselTests/OptionBundle.scala      |  4 ++--
 src/test/scala/chiselTests/Padding.scala           |  3 ++-
 .../scala/chiselTests/ParameterizedModule.scala    |  4 ++--
 src/test/scala/chiselTests/Printf.scala            |  4 ++--
 src/test/scala/chiselTests/Reg.scala               |  5 +++--
 src/test/scala/chiselTests/Risc.scala              |  4 +++-
 src/test/scala/chiselTests/SIntOps.scala           |  5 +++--
 src/test/scala/chiselTests/Stack.scala             |  5 ++++-
 src/test/scala/chiselTests/Stop.scala              |  4 ++--
 src/test/scala/chiselTests/Tbl.scala               |  6 ++++--
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  5 +++--
 src/test/scala/chiselTests/UIntOps.scala           |  5 +++--
 src/test/scala/chiselTests/Vec.scala               |  6 ++++--
 src/test/scala/chiselTests/VectorPacketIO.scala    |  5 +++--
 src/test/scala/chiselTests/VendingMachine.scala    |  4 +++-
 src/test/scala/chiselTests/When.scala              |  6 ++++--
 34 files changed, 110 insertions(+), 72 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 24eb8b55..3fed2bd4 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -3,8 +3,9 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class FailingAssertTester() extends BasicTester {
   assert(Bool(false))
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 19aa956c..08999a1b 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index ca94087c..fdc5970e 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -4,8 +4,10 @@ package chiselTests
 
 import java.io.File
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class BlackBoxInverter extends BlackBox {
   val io = new Bundle() {
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index d2e42fa9..e5e9fb1a 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class Coord extends Bundle {
   val x = UInt(width = 32)
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index da68b0cb..d335bdf6 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -6,8 +6,8 @@ import java.io.File
 import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
-import Chisel._
-import Chisel.testers._
+import chisel3._
+import chisel3.testers._
 
 /** Common utility functions for Chisel unit tests. */
 trait ChiselRunners extends Assertions {
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index d79a2625..304fbcf5 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -1,11 +1,13 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
 import org.scalatest._
 import org.scalatest.prop._
 
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 07a76cdc..69d8a44a 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -1,10 +1,13 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index e5cdfd07..5586561b 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -1,11 +1,14 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
 import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 8f7937ab..09891647 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -2,8 +2,9 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /**
   * Created by chick on 2/8/16.
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index dd2f6572..8b84f844 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class DirectionHaver extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 6600df2a..7db20fc1 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class EnableShiftRegister extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index a1bfffda..60a70cc8 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -2,8 +2,8 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 
diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index bc838766..83f60391 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -1,13 +1,14 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel.testers.BasicTester
+
+import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 import java.io.File
 
 class HarnessSpec extends ChiselPropSpec
-  with Chisel.BackendCompilationUtilities {
+  with chisel3.BackendCompilationUtilities {
 
   def makeTrivialVerilog: (File => File) = makeHarness((prefix: String) => s"""
 module ${prefix};
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index ed76a296..a1699441 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -1,8 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class LFSR16 extends Module {
   val io = new Bundle {
@@ -34,7 +36,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) {
 }
 */
 
-//TODO: Use chisel.util version instead?
+//TODO: Use chisel3.util version instead?
 
 class LFSRSpec extends ChiselPropSpec {
 
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 55b704a0..679b894c 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -1,8 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
 
 class MemorySearch extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 88ba795b..23788b72 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
 
 class SimpleIO extends Bundle {
   val in  = UInt(INPUT,  32)
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 49ba13c7..831e323f 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 2f464123..d5e9b998 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -3,29 +3,31 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
 
   val test = Wire(UInt(width=4))
-  assert(test === UInt(7))  // allow read references before assign references
+  assert(test === UInt.Lit(7))  // allow read references before assign references
 
-  test := UInt(13)
-  assert(test === UInt(7))  // output value should be position-independent
+  test := UInt.Lit(13)
+  assert(test === UInt.Lit(7))  // output value should be position-independent
 
-  test := UInt(7)
-  assert(test === UInt(7))  // this obviously should work
+  test := UInt.Lit(7)
+  assert(test === UInt.Lit(7))  // this obviously should work
 
-  when(cnt.value === UInt(1)) {
+  when(cnt.value === UInt.Lit(1)) {
     stop()
   }
 }
 
 class ReassignmentTester() extends BasicTester {
-  val test = UInt(15)
-  test := UInt(7)
+  val test = UInt.Lit(15)
+  test := UInt.Lit(7)
 }
 
 class MultiAssignSpec extends ChiselFlatSpec {
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index c5a347e6..fa691b43 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class OptionBundle(hasIn: Boolean) extends Bundle {
   val in = if (hasIn) {
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 999b7d36..3fb0f955 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
 
 class Padder extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index 35e3ba78..4859759e 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class ParameterizedModule(invert: Boolean) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index eb8b4b25..c872fde4 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
   val x = UInt(254)
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index f2620d88..391dd7de 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -3,8 +3,9 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.core.DataMirror
+import chisel3.testers.BasicTester
 
 class RegSpec extends ChiselFlatSpec {
   "A Reg" should "throw an exception if not given any parameters" in {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 3daa5bd2..f5e61115 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -1,7 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
+import chisel3.util._
 
 class Risc extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 0835fb4d..6cd013f1 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -1,8 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
 
 class SIntOps extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ac799c8a..cbd9f3e3 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -1,8 +1,11 @@
 // See LICENSE for license details.
 
 package chiselTests
+
 import scala.collection.mutable.Stack
-import Chisel._
+
+import chisel3._
+import chisel3.util._
 
 class ChiselStack(val depth: Int) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala
index 878f090c..4afb077a 100644
--- a/src/test/scala/chiselTests/Stop.scala
+++ b/src/test/scala/chiselTests/Stop.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class StopTester() extends BasicTester {
   stop()
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index c79eb8a4..d84cd85e 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -2,10 +2,12 @@
 
 package chiselTests
 
-import Chisel._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 3c57daae..2f3e9368 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -2,8 +2,9 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /** Extend BasicTester with a simple circuit and finish method.  TesterDriver will call the
   * finish method after the FinishTester's constructor has completed, which will alter the
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index bb0b0f06..c5069fc4 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -1,9 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
 import org.scalatest._
-import Chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class UIntOps extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 943d9e4b..7dd80a13 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -2,10 +2,12 @@
 
 package chiselTests
 
-import Chisel._
 import org.scalatest._
 import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 99ec66a6..07779faa 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -2,8 +2,9 @@
 
 package chiselTests
 
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /**
   * This test used to fail when assignment statements were
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 012fc493..f03cb881 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -1,7 +1,9 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
+
+import chisel3._
+import chisel3.util._
 
 class VendingMachine extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index a6572706..5f3d3e61 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -3,8 +3,10 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)
-- 
cgit v1.2.3


From 3120eefc8a73b5ab3d8f909445a3e004b5e60cc6 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 19 Jul 2016 15:08:22 -0700
Subject: Incorporate connection logic. Compiles but fails tests.

---
 src/test/scala/chiselTests/Module.scala      |  2 +-
 src/test/scala/chiselTests/MultiAssign.scala | 19 ++++++++++---------
 src/test/scala/chiselTests/Reg.scala         | 18 +++++++++---------
 3 files changed, 20 insertions(+), 19 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 7c0bc40e..f1608d5b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
 
 class ModuleWire extends Module {
   val io = IO(new SimpleIO)
-  val inc = Wire(Module(new PlusOne).io.newType)
+  val inc = Wire(Module(new PlusOne).io.cloneType)
   inc.in := io.in
   io.out := inc.out
 }
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index d5e9b998..fc6c5edc 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -12,29 +12,30 @@ class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
 
   val test = Wire(UInt(width=4))
-  assert(test === UInt.Lit(7))  // allow read references before assign references
+  assert(test === 7.U)  // allow read references before assign references
 
-  test := UInt.Lit(13)
-  assert(test === UInt.Lit(7))  // output value should be position-independent
+  test := 13.U
+  assert(test === 7.U)  // output value should be position-independent
 
-  test := UInt.Lit(7)
-  assert(test === UInt.Lit(7))  // this obviously should work
+  test := 7.U
+  assert(test === 7.U)  // this obviously should work
 
-  when(cnt.value === UInt.Lit(1)) {
+  when(cnt.value === 1.U) {
     stop()
   }
 }
 
 class ReassignmentTester() extends BasicTester {
-  val test = UInt.Lit(15)
-  test := UInt.Lit(7)
+  val test = 15.U
+  test := 7.U
 }
 
 class MultiAssignSpec extends ChiselFlatSpec {
   "The last assignment" should "be used when multiple assignments happen" in {
     assertTesterPasses{ new LastAssignTester }
   }
-  "Reassignments to non-wire types" should "be disallowed" in {
+  intercept[chisel3.internal.ChiselException] {
+//    "Reassignments to non-wire types" should "be disallowed" in {
     assertTesterFails{ new ReassignmentTester }
   }
 }
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 391dd7de..0caf6315 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,20 +16,20 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20))
-      reg.width.get should be (2)
+      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20))
+      reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
   }
 
   "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
     class RegUnknownWidthTester extends BasicTester {
-      val reg1 = Reg(next=UInt(width=3), init=UInt(20))
-      reg1.width.known should be (false)
-      val reg2 = Reg(init=UInt(20))
-      reg2.width.known should be (false)
-      val reg3 = Reg(next=UInt(width=3), init=UInt(width=5))
-      reg3.width.known should be (false)
+      val reg1 = Reg(next=Wire(UInt(width=3)), init=20.U)
+      DataMirror.widthOf(reg1).known should be (false)
+      val reg2 = Reg(init=20.U)
+      DataMirror.widthOf(reg2).known should be (false)
+      val reg3 = Reg(next=Wire(UInt(width=3)), init=5.U)
+      DataMirror.widthOf(reg3).known should be (false)
     }
     elaborate { new RegUnknownWidthTester }
   }
@@ -37,7 +37,7 @@ class RegSpec extends ChiselFlatSpec {
   "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
     class RegForcedWidthTester extends BasicTester {
       val reg2 = Reg(init=UInt(20, width=7))
-      reg2.width.get should be (7)
+      reg2.getWidth should be (7)
     }
     elaborate{ new RegForcedWidthTester }
   }
-- 
cgit v1.2.3


From 21a3c12b309df88cdb8114c01ef35b044282d647 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 19 Jul 2016 16:16:35 -0700
Subject: Fix LitBinding and MultiAssign tests.

---
 src/test/scala/chiselTests/MultiAssign.scala | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index fc6c5edc..2399267e 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -34,8 +34,12 @@ class MultiAssignSpec extends ChiselFlatSpec {
   "The last assignment" should "be used when multiple assignments happen" in {
     assertTesterPasses{ new LastAssignTester }
   }
-  intercept[chisel3.internal.ChiselException] {
-//    "Reassignments to non-wire types" should "be disallowed" in {
-    assertTesterFails{ new ReassignmentTester }
+}
+
+class IllegalAssignSpec extends ChiselFlatSpec {
+  "Reassignments to non-wire types" should "be disallowed" in {
+    intercept[chisel3.internal.ChiselException] {
+      assertTesterFails{ new ReassignmentTester }
+    }
   }
 }
-- 
cgit v1.2.3


From 28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 13:28:15 -0700
Subject: Compile ok. Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)

---
 src/test/scala/chiselTests/GCD.scala    | 14 +++++++-------
 src/test/scala/chiselTests/Module.scala |  2 +-
 src/test/scala/chiselTests/Risc.scala   | 12 ++++++------
 3 files changed, 14 insertions(+), 14 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index a8b907af..7c04ae00 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -21,18 +21,18 @@ class GCD extends Module {
   .otherwise     { y := y -% x }
   when (io.e) { x := io.a; y := io.b }
   io.z := x
-  io.v := y === UInt(0)
+  io.v := y === 0.U
 }
 
 class GCDTester(a: Int, b: Int, z: Int) extends BasicTester {
   val dut = Module(new GCD)
-  val first = Reg(init=Bool(true))
-  dut.io.a := UInt(a)
-  dut.io.b := UInt(b)
+  val first = Reg(init=true.B)
+  dut.io.a := a.U
+  dut.io.b := b.U
   dut.io.e := first
-  when(first) { first := Bool(false) }
-  when(dut.io.v) {
-    assert(dut.io.z === UInt(z))
+  when(first) { first := false.B }
+  when(!first && dut.io.v) {
+    assert(dut.io.z === z.U)
     stop()
   }
 }
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index f1608d5b..857aeda3 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -11,7 +11,7 @@ class SimpleIO extends Bundle {
 
 class PlusOne extends Module {
   val io = IO(new SimpleIO)
-  io.out := io.in + UInt(1)
+  io.out := io.in + 1.asUInt
 }
 
 class ModuleVec(val n: Int) extends Module {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index fafec95a..c110d37e 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -27,13 +27,13 @@ class Risc extends Module {
   val rai  = inst(15, 8)
   val rbi  = inst( 7, 0)
 
-  val ra = Mux(rai === Bits(0), Bits(0), file(rai))
-  val rb = Mux(rbi === Bits(0), Bits(0), file(rbi))
+  val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
+  val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
   val rc = Wire(Bits(width = 32))
 
   io.valid := Bool(false)
-  io.out   := Bits(0)
-  rc       := Bits(0)
+  io.out   := 0.asUInt()
+  rc       := 0.asUInt()
 
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
@@ -45,12 +45,12 @@ class Risc extends Module {
       is(imm_op) { rc := (rai << 8) | rbi }
     }
     io.out := rc
-    when (rci === UInt(255)) {
+    when (rci === 255.asUInt()) {
       io.valid := Bool(true)
     } .otherwise {
       file(rci) := rc
     }
-    pc := pc +% UInt(1)
+    pc := pc +% 1.asUInt()
   }
 }
 
-- 
cgit v1.2.3


From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 14:49:35 -0700
Subject: Distinguish between ?Int.Lit and ?Int.width

---
 src/test/scala/chiselTests/Assert.scala            |  4 +--
 src/test/scala/chiselTests/BlackBox.scala          | 30 +++++++++---------
 src/test/scala/chiselTests/BundleWire.scala        |  8 ++---
 src/test/scala/chiselTests/ComplexAssign.scala     | 12 ++++----
 src/test/scala/chiselTests/Counter.scala           |  8 ++---
 src/test/scala/chiselTests/Decoder.scala           |  4 +--
 src/test/scala/chiselTests/Direction.scala         |  8 ++---
 .../scala/chiselTests/EnableShiftRegister.scala    |  4 +--
 src/test/scala/chiselTests/GCD.scala               |  6 ++--
 src/test/scala/chiselTests/LFSR16.scala            |  2 +-
 src/test/scala/chiselTests/MemorySearch.scala      | 10 +++---
 src/test/scala/chiselTests/Module.scala            |  8 ++---
 src/test/scala/chiselTests/MulLookup.scala         | 12 ++++----
 src/test/scala/chiselTests/Padding.scala           |  6 ++--
 src/test/scala/chiselTests/Printf.scala            |  6 ++--
 src/test/scala/chiselTests/Reg.scala               |  2 +-
 src/test/scala/chiselTests/Risc.scala              |  4 +--
 src/test/scala/chiselTests/SIntOps.scala           | 26 ++++++++--------
 src/test/scala/chiselTests/Stack.scala             | 16 +++++-----
 src/test/scala/chiselTests/Tbl.scala               | 10 +++---
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  6 ++--
 src/test/scala/chiselTests/UIntOps.scala           | 24 +++++++--------
 src/test/scala/chiselTests/Vec.scala               |  6 ++--
 src/test/scala/chiselTests/When.scala              | 36 +++++++++++-----------
 24 files changed, 129 insertions(+), 129 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index efc2e1e7..bf3c8092 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester {
 
 class PipelinedResetModule extends Module {
   val io = IO(new Bundle { })
-  val a = Reg(init = UInt(0xbeef))
-  val b = Reg(init = UInt(0xbeef))
+  val a = Reg(init = UInt.Lit(0xbeef))
+  val b = Reg(init = UInt.Lit(0xbeef))
   assert(a === b)
 }
 
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index c1154883..9b43f0ef 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -35,11 +35,11 @@ class BlackBoxTester extends BasicTester {
   val blackBoxPos = Module(new BlackBoxInverter)
   val blackBoxNeg = Module(new BlackBoxInverter)
 
-  blackBoxPos.io.in := UInt(1)
-  blackBoxNeg.io.in := UInt(0)
+  blackBoxPos.io.in := UInt.Lit(1)
+  blackBoxNeg.io.in := UInt.Lit(0)
 
-  assert(blackBoxNeg.io.out === UInt(1))
-  assert(blackBoxPos.io.out === UInt(0))
+  assert(blackBoxNeg.io.out === UInt.Lit(1))
+  assert(blackBoxPos.io.out === UInt.Lit(0))
   stop()
 }
 
@@ -54,15 +54,15 @@ class MultiBlackBoxTester extends BasicTester {
   val blackBoxPassPos = Module(new BlackBoxPassthrough)
   val blackBoxPassNeg = Module(new BlackBoxPassthrough)
 
-  blackBoxInvPos.io.in := UInt(1)
-  blackBoxInvNeg.io.in := UInt(0)
-  blackBoxPassPos.io.in := UInt(1)
-  blackBoxPassNeg.io.in := UInt(0)
+  blackBoxInvPos.io.in := UInt.Lit(1)
+  blackBoxInvNeg.io.in := UInt.Lit(0)
+  blackBoxPassPos.io.in := UInt.Lit(1)
+  blackBoxPassNeg.io.in := UInt.Lit(0)
 
-  assert(blackBoxInvNeg.io.out === UInt(1))
-  assert(blackBoxInvPos.io.out === UInt(0))
-  assert(blackBoxPassNeg.io.out === UInt(0))
-  assert(blackBoxPassPos.io.out === UInt(1))
+  assert(blackBoxInvNeg.io.out === UInt.Lit(1))
+  assert(blackBoxInvPos.io.out === UInt.Lit(0))
+  assert(blackBoxPassNeg.io.out === UInt.Lit(0))
+  assert(blackBoxPassPos.io.out === UInt.Lit(1))
   stop()
 }
 
@@ -77,7 +77,7 @@ class BlackBoxWithClockTester extends BasicTester {
   blackBox.io.in := impetus
   model := impetus
 
-  when(cycles > UInt(0)) {
+  when(cycles > UInt.Lit(0)) {
     assert(blackBox.io.out === model)
   }
   when(end) { stop() }
@@ -98,8 +98,8 @@ class BlackBoxWithParamsTester extends BasicTester {
 
   val (cycles, end) = Counter(Bool(true), 4)
 
-  assert(blackBoxOne.io.out  === UInt(1))
-  assert(blackBoxFour.io.out === UInt(4))
+  assert(blackBoxOne.io.out  === UInt.Lit(1))
+  assert(blackBoxFour.io.out === UInt.Lit(4))
 
   when(end) { stop() }
 }
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 029407dd..2f6322b1 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -25,11 +25,11 @@ class BundleWire(n: Int) extends Module {
 
 class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new BundleWire(n))
-  dut.io.in.x := UInt(x)
-  dut.io.in.y := UInt(y)
+  dut.io.in.x := UInt.Lit(x)
+  dut.io.in.y := UInt.Lit(y)
   for (elt <- dut.io.outs) {
-    assert(elt.x === UInt(x))
-    assert(elt.y === UInt(y))
+    assert(elt.x === UInt.Lit(x))
+    assert(elt.y === UInt.Lit(y))
   }
   stop()
 }
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index e5d1fbea..638ef9b7 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -26,19 +26,19 @@ class ComplexAssign(w: Int) extends Module {
     io.out.re := tmp.re
     io.out.im := tmp.im
   } .otherwise {
-    io.out.re := UInt(0)
-    io.out.im := UInt(0)
+    io.out.re := UInt.Lit(0)
+    io.out.im := UInt.Lit(0)
   }
 }
 
 class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), enList.size)
   val dut = Module(new ComplexAssign(32))
-  dut.io.in.re := UInt(re)
-  dut.io.in.im := UInt(im)
+  dut.io.in.re := UInt.Lit(re)
+  dut.io.in.im := UInt.Lit(im)
   dut.io.e := Vec(enList.map(Bool(_)))(cnt)
-  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0))
-  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0))
+  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt.Lit(0))
+  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt.Lit(0))
   assert(re_correct && im_correct)
   when(wrap) {
     stop()
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 69d8a44a..af2fa550 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -12,20 +12,20 @@ import chisel3.util._
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
   when(Bool(true)) { cnt.inc() }
-  when(cnt.value === UInt(max-1)) {
+  when(cnt.value === UInt.Lit(max-1)) {
     stop()
   }
 }
 
 class EnableTester(seed: Int) extends BasicTester {
-  val ens = Reg(init = UInt(seed))
+  val ens = Reg(init = UInt.Lit(seed))
   ens := ens >> 1
 
   val (cntEnVal, _) = Counter(ens(0), 32)
   val (_, done) = Counter(Bool(true), 33)
 
   when(done) {
-    assert(cntEnVal === UInt(popCount(seed)))
+    assert(cntEnVal === UInt.Lit(popCount(seed)))
     stop()
   }
 }
@@ -33,7 +33,7 @@ class EnableTester(seed: Int) extends BasicTester {
 class WrapTester(max: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), max)
   when(wrap) {
-    assert(cnt === UInt(max - 1))
+    assert(cnt === UInt.Lit(max - 1))
     stop()
   }
 }
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 4a872245..ee892fc5 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = IO(new Bundle {
-    val inst  = Input(UInt(32))
+    val inst  = Input(UInt.width(32))
     val matched = Output(Bool())
   })
   io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
@@ -24,7 +24,7 @@ class DecoderTester(pairs: List[(String, String)]) extends BasicTester {
   val dut = Module(new Decoder(bitpats))
   dut.io.inst := Vec(insts.map(UInt(_)))(cnt)
   when(!dut.io.matched) {
-    assert(cnt === UInt(0))
+    assert(cnt === UInt.Lit(0))
     stop()
   }
   when(wrap) {
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 682103f7..e22e120b 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -9,17 +9,17 @@ import chisel3.testers.BasicTester
 
 class DirectionHaver extends Module {
   val io = IO(new Bundle {
-    val in = Input(UInt(32))
-    val out = Output(UInt(32))
+    val in = Input(UInt.width(32))
+    val out = Output(UInt.width(32))
   })
 }
 
 class GoodDirection extends DirectionHaver {
-  io.out := UInt(0)
+  io.out := UInt.Lit(0)
 }
 
 class BadDirection extends DirectionHaver {
-  io.in := UInt(0)
+  io.in := UInt.Lit(0)
 }
 
 class DirectionSpec extends ChiselPropSpec {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 26af944f..5f3e0dd1 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -6,9 +6,9 @@ import chisel3.testers.BasicTester
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
-    val in    = Input(UInt(4))
+    val in    = Input(UInt.width(4))
     val shift = Input(Bool())
-    val out   = Output(UInt(4))
+    val out   = Output(UInt.width(4))
   })
   val r0 = Reg(init = UInt(0, 4))
   val r1 = Reg(init = UInt(0, 4))
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index 7c04ae00..d0d945b7 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -9,10 +9,10 @@ import org.scalatest.prop._
 
 class GCD extends Module {
   val io = IO(new Bundle {
-    val a  = Input(UInt(32))
-    val b  = Input(UInt(32))
+    val a  = Input(UInt.width(32))
+    val b  = Input(UInt.width(32))
     val e  = Input(Bool())
-    val z  = Output(UInt(32))
+    val z  = Output(UInt.width(32))
     val v  = Output(Bool())
   })
   val x = Reg(UInt(width = 32))
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index 2d5e7f3e..b13b67e3 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -9,7 +9,7 @@ import chisel3.util._
 class LFSR16 extends Module {
   val io = IO(new Bundle {
     val inc = Input(Bool())
-    val out = Output(UInt(16))
+    val out = Output(UInt.width(16))
   })
   val res = Reg(init = UInt(1, 16))
   when (io.inc) {
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 770be326..e4063532 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -7,21 +7,21 @@ import chisel3.testers.BasicTester
 
 class MemorySearch extends Module {
   val io = IO(new Bundle {
-    val target  = Input(UInt(4))
+    val target  = Input(UInt.width(4))
     val en      = Input(Bool())
     val done    = Output(Bool())
-    val address = Output(UInt(3))
+    val address = Output(UInt.width(3))
   })
   val vals  = Array(0, 4, 15, 14, 2, 5, 13)
   val index = Reg(init = UInt(0, width = 3))
   val elts  = Vec(vals.map(UInt(_,4)))
   // val elts  = Mem(UInt(width = 32), 8) TODO ????
   val elt  = elts(index)
-  val end  = !io.en && ((elt === io.target) || (index === UInt(7)))
+  val end  = !io.en && ((elt === io.target) || (index === UInt.Lit(7)))
   when (io.en) {
-    index := UInt(0)
+    index := UInt.Lit(0)
   } .elsewhen (!end) {
-    index := index +% UInt(1)
+    index := index +% UInt.Lit(1)
   }
   io.done    := end
   io.address := index
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 857aeda3..59451a2b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -5,8 +5,8 @@ package chiselTests
 import chisel3._
 
 class SimpleIO extends Bundle {
-  val in  = Input(UInt(32))
-  val out = Output(UInt(32))
+  val in  = Input(UInt.width(32))
+  val out = Output(UInt.width(32))
 }
 
 class PlusOne extends Module {
@@ -16,8 +16,8 @@ class PlusOne extends Module {
 
 class ModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Input(Vec(n, UInt(32)))
-    val outs = Output(Vec(n, UInt(32)))
+    val ins  = Input(Vec(n, UInt.Lit(32)))
+    val outs = Output(Vec(n, UInt.Lit(32)))
   })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index b22b2820..16a29104 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -9,9 +9,9 @@ import chisel3.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
-    val x   = Input(UInt(w))
-    val y   = Input(UInt(w))
-    val z   = Output(UInt(2 * w))
+    val x   = Input(UInt.width(w))
+    val y   = Input(UInt.width(w))
+    val z   = Output(UInt.width(2 * w))
   })
   val tbl = Vec(
     for {
@@ -24,9 +24,9 @@ class MulLookup(val w: Int) extends Module {
 
 class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new MulLookup(w))
-  dut.io.x := UInt(x)
-  dut.io.y := UInt(y)
-  assert(dut.io.z === UInt(x * y))
+  dut.io.x := UInt.Lit(x)
+  dut.io.y := UInt.Lit(y)
+  assert(dut.io.z === UInt.Lit(x * y))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 6c92e87b..42df6802 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -6,9 +6,9 @@ import chisel3._
 
 class Padder extends Module {
   val io = IO(new Bundle {
-    val a   = Input(UInt(4))
-    val asp = Output(SInt(8))
-    val aup = Output(UInt(8))
+    val a   = Input(UInt.width(4))
+    val asp = Output(SInt.width(8))
+    val aup = Output(UInt.width(8))
   })
   io.asp := io.a.asSInt
   io.aup := io.a.asUInt
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index c872fde4..92b6fee1 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
-  val x = UInt(254)
+  val x = UInt.Lit(254)
   printf("x=%x", x)
   stop()
 }
@@ -18,8 +18,8 @@ class ASCIIPrintfTester() extends BasicTester {
 }
 
 class MultiPrintfTester() extends BasicTester {
-  val x = UInt(254)
-  val y = UInt(255)
+  val x = UInt.Lit(254)
+  val y = UInt.Lit(255)
   printf("x=%x y=%x", x, y)
   stop()
 }
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 0caf6315..5d4bd18d 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20))
+      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt.Lit(20))
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index c110d37e..156e5df2 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 class Risc extends Module {
   val io = IO(new Bundle {
     val isWr   = Input(Bool())
-    val wrAddr = Input(UInt(8))
+    val wrAddr = Input(UInt.width(8))
     val wrData = Input(Bits(32))
     val boot   = Input(Bool())
     val valid  = Output(Bool())
@@ -38,7 +38,7 @@ class Risc extends Module {
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
   } .elsewhen (io.boot) {
-    pc := UInt(0)
+    pc := UInt.Lit(0)
   } .otherwise {
     switch(op) {
       is(add_op) { rc := ra +% rb }
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index a98edf9b..d827c096 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -7,22 +7,22 @@ import chisel3.testers.BasicTester
 
 class SIntOps extends Module {
   val io = IO(new Bundle {
-    val a = Input(SInt(16))
-    val b = Input(SInt(16))
-    val addout = Output(SInt(16))
-    val subout = Output(SInt(16))
-    val timesout = Output(SInt(16))
-    val divout = Output(SInt(16))
-    val modout = Output(SInt(16))
-    val lshiftout = Output(SInt(16))
-    val rshiftout = Output(SInt(16))
+    val a = Input(SInt.width(16))
+    val b = Input(SInt.width(16))
+    val addout = Output(SInt.width(16))
+    val subout = Output(SInt.width(16))
+    val timesout = Output(SInt.width(16))
+    val divout = Output(SInt.width(16))
+    val modout = Output(SInt.width(16))
+    val lshiftout = Output(SInt.width(16))
+    val rshiftout = Output(SInt.width(16))
     val lessout = Output(Bool())
     val greatout = Output(Bool())
     val eqout = Output(Bool())
     val noteqout = Output(Bool())
     val lesseqout = Output(Bool())
     val greateqout = Output(Bool())
-    val negout = Output(SInt(16))
+    val negout = Output(SInt.width(16))
   })
 
   val a = io.a
@@ -32,9 +32,9 @@ class SIntOps extends Module {
   io.subout := a -% b
   // TODO:
   //io.timesout := (a * b)(15, 0)
-  //io.divout := a / Mux(b === SInt(0), SInt(1), b)
+  //io.divout := a / Mux(b === SInt.Lit(0), SInt.Lit(1), b)
   //io.divout := (a / b)(15, 0)
-  //io.modout := SInt(0)
+  //io.modout := SInt.Lit(0)
   //io.lshiftout := (a << 12)(15, 0) //  (a << ub(3, 0))(15, 0).toSInt
   io.rshiftout := (a >> 8) // (a >> ub).toSInt
   io.lessout := a < b
@@ -44,7 +44,7 @@ class SIntOps extends Module {
   io.lesseqout := a <= b
   io.greateqout := a >= b
   // io.negout := -a(15, 0).toSInt
-  io.negout := (SInt(0) -% a)
+  io.negout := (SInt.Lit(0) -% a)
 }
 
 /*
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 683c5224..440228c9 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -12,8 +12,8 @@ class ChiselStack(val depth: Int) extends Module {
     val push    = Input(Bool())
     val pop     = Input(Bool())
     val en      = Input(Bool())
-    val dataIn  = Input(UInt(32))
-    val dataOut = Output(UInt(32))
+    val dataIn  = Input(UInt.width(32))
+    val dataOut = Output(UInt.width(32))
   })
 
   val stack_mem = Mem(depth, UInt(width = 32))
@@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module {
   val out       = Reg(init = UInt(0, width = 32))
 
   when (io.en) {
-    when(io.push && (sp < UInt(depth))) {
+    when(io.push && (sp < UInt.Lit(depth))) {
       stack_mem(sp) := io.dataIn
-      sp := sp +% UInt(1)
-    } .elsewhen(io.pop && (sp > UInt(0))) {
-      sp := sp -% UInt(1)
+      sp := sp +% UInt.Lit(1)
+    } .elsewhen(io.pop && (sp > UInt.Lit(0))) {
+      sp := sp -% UInt.Lit(1)
     }
-    when (sp > UInt(0)) {
-      out := stack_mem(sp -% UInt(1))
+    when (sp > UInt.Lit(0)) {
+      out := stack_mem(sp -% UInt.Lit(1))
     }
   }
   io.dataOut := out
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 6ebe0875..75c4278f 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -14,8 +14,8 @@ class Tbl(w: Int, n: Int) extends Module {
     val wi  = Input(UInt(log2Up(n)))
     val ri  = Input(UInt(log2Up(n)))
     val we  = Input(Bool())
-    val  d  = Input(UInt(w))
-    val  o  = Output(UInt(w))
+    val  d  = Input(UInt.width(w))
+    val  o  = Output(UInt.width(w))
   })
   val m = Mem(n, UInt(width = w))
   io.o := m(io.ri)
@@ -32,13 +32,13 @@ class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends Basi
   val dut = Module(new Tbl(w, n))
   val vvalues = Vec(values.map(UInt(_)))
   val vidxs = Vec(idxs.map(UInt(_)))
-  val prev_idx = vidxs(cnt - UInt(1))
-  val prev_value = vvalues(cnt - UInt(1))
+  val prev_idx = vidxs(cnt - UInt.Lit(1))
+  val prev_value = vvalues(cnt - UInt.Lit(1))
   dut.io.wi := vidxs(cnt)
   dut.io.ri := prev_idx
   dut.io.we := Bool(true) //TODO enSequence
   dut.io.d := vvalues(cnt)
-  when (cnt > UInt(0)) {
+  when (cnt > UInt.Lit(0)) {
     when (prev_idx === vidxs(cnt)) {
       assert(dut.io.o === vvalues(cnt))
     } .otherwise {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 2f3e9368..4c1e41c8 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -20,17 +20,17 @@ class FinishTester extends BasicTester {
     stop()
   }
 
-  val test_wire = Wire(UInt(1, width = test_wire_width))
+  val test_wire = UInt(1, width = test_wire_width)
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
-  assert(test_wire === UInt(test_wire_override_value))
+  assert(test_wire === UInt.Lit(test_wire_override_value))
 
   /** In finish we use last connect semantics to alter the test_wire in the circuit
     * with a new value
     */
   override def finish(): Unit = {
-    test_wire := UInt(test_wire_override_value)
+    test_wire := UInt.Lit(test_wire_override_value)
   }
 }
 
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index ca83ee1d..812f822d 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -8,15 +8,15 @@ import chisel3.testers.BasicTester
 
 class UIntOps extends Module {
   val io = IO(new Bundle {
-    val a = Input(UInt(16))
-    val b = Input(UInt(16))
-    val addout = Output(UInt(16))
-    val subout = Output(UInt(16))
-    val timesout = Output(UInt(16))
-    val divout = Output(UInt(16))
-    val modout = Output(UInt(16))
-    val lshiftout = Output(UInt(16))
-    val rshiftout = Output(UInt(16))
+    val a = Input(UInt.width(16))
+    val b = Input(UInt.width(16))
+    val addout = Output(UInt.width(16))
+    val subout = Output(UInt.width(16))
+    val timesout = Output(UInt.width(16))
+    val divout = Output(UInt.width(16))
+    val modout = Output(UInt.width(16))
+    val lshiftout = Output(UInt.width(16))
+    val rshiftout = Output(UInt.width(16))
     val lessout = Output(Bool())
     val greatout = Output(Bool())
     val eqout = Output(Bool())
@@ -31,10 +31,10 @@ class UIntOps extends Module {
   io.addout := a +% b
   io.subout := a -% b
   io.timesout := (a * b)(15, 0)
-  io.divout := a / Mux(b === UInt(0), UInt(1), b)
+  io.divout := a / Mux(b === UInt.Lit(0), UInt.Lit(1), b)
   // io.modout := a % b
   // TODO:
-  io.modout := UInt(0)
+  io.modout := UInt.Lit(0)
   io.lshiftout := (a << b(3, 0))(15, 0)
   io.rshiftout := a >> b
   io.lessout := a < b
@@ -78,7 +78,7 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) {
 
 class GoodBoolConversion extends Module {
   val io = IO(new Bundle {
-    val u = Input(UInt(1))
+    val u = Input(UInt.width(1))
     val b = Output(Bool())
   })
   io.b := io.u.toBool
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index b90c1f09..cdb1ba8d 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
   for ((a,b) <- v.zip(values)) {
-    assert(a === UInt(b))
+    assert(a === UInt.Lit(b))
   }
   stop()
 }
@@ -34,8 +34,8 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
   val shifter = Reg(Vec(n, UInt(width = log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
-  when (cnt >= UInt(n)) {
-    val expected = cnt - UInt(n)
+  when (cnt >= UInt.Lit(n)) {
+    val expected = cnt - UInt.Lit(n)
     assert(shifter(0) === expected)
   }
   when (wrap) {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 5f3d3e61..58aa43e7 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -13,19 +13,19 @@ class WhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt(width=3))
-  when(cnt.value === UInt(0)) {
-    out := UInt(1)
-  } .elsewhen (cnt.value === UInt(1)) {
-    out := UInt(2)
-  } .elsewhen (cnt.value === UInt(2)) {
-    out := UInt(3)
+  when(cnt.value === UInt.Lit(0)) {
+    out := UInt.Lit(1)
+  } .elsewhen (cnt.value === UInt.Lit(1)) {
+    out := UInt.Lit(2)
+  } .elsewhen (cnt.value === UInt.Lit(2)) {
+    out := UInt.Lit(3)
   } .otherwise {
-    out := UInt(0)
+    out := UInt.Lit(0)
   }
 
-  assert(out === cnt.value + UInt(1))
+  assert(out === cnt.value + UInt.Lit(1))
 
-  when(cnt.value === UInt(3)) {
+  when(cnt.value === UInt.Lit(3)) {
     stop()
   }
 }
@@ -35,19 +35,19 @@ class OverlappedWhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt(width=3))
-  when(cnt.value <= UInt(0)) {
-    out := UInt(1)
-  } .elsewhen (cnt.value <= UInt(1)) {
-    out := UInt(2)
-  } .elsewhen (cnt.value <= UInt(2)) {
-    out := UInt(3)
+  when(cnt.value <= UInt.Lit(0)) {
+    out := UInt.Lit(1)
+  } .elsewhen (cnt.value <= UInt.Lit(1)) {
+    out := UInt.Lit(2)
+  } .elsewhen (cnt.value <= UInt.Lit(2)) {
+    out := UInt.Lit(3)
   } .otherwise {
-    out := UInt(0)
+    out := UInt.Lit(0)
   }
 
-  assert(out === cnt.value + UInt(1))
+  assert(out === cnt.value + UInt.Lit(1))
 
-  when(cnt.value === UInt(3)) {
+  when(cnt.value === UInt.Lit(3)) {
     stop()
   }
 }
-- 
cgit v1.2.3


From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 17:08:55 -0700
Subject: More literal/width rangling.

---
 src/test/scala/chiselTests/BitwiseOps.scala     |  8 ++++----
 src/test/scala/chiselTests/BundleWire.scala     |  4 ++--
 src/test/scala/chiselTests/ComplexAssign.scala  |  6 +++---
 src/test/scala/chiselTests/DeqIOSpec.scala      |  2 +-
 src/test/scala/chiselTests/GCD.scala            |  4 ++--
 src/test/scala/chiselTests/MultiAssign.scala    |  2 +-
 src/test/scala/chiselTests/Reg.scala            |  6 +++---
 src/test/scala/chiselTests/Risc.scala           | 12 ++++++------
 src/test/scala/chiselTests/Stack.scala          |  2 +-
 src/test/scala/chiselTests/Tbl.scala            | 10 +++++-----
 src/test/scala/chiselTests/UIntOps.scala        |  2 +-
 src/test/scala/chiselTests/Vec.scala            |  8 ++++----
 src/test/scala/chiselTests/VectorPacketIO.scala |  2 +-
 src/test/scala/chiselTests/When.scala           |  4 ++--
 14 files changed, 36 insertions(+), 36 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 08999a1b..0aaa3c57 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -11,10 +11,10 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
   val a = UInt(_a, w)
   val b = UInt(_b, w)
-  assert(~a === UInt(mask & ~_a))
-  assert((a & b) === UInt(_a & _b))
-  assert((a | b) === UInt(_a | _b))
-  assert((a ^ b) === UInt(_a ^ _b))
+  assert(~a === UInt.Lit(mask & ~_a))
+  assert((a & b) === UInt.Lit(_a & _b))
+  assert((a | b) === UInt.Lit(_a | _b))
+  assert((a ^ b) === UInt.Lit(_a ^ _b))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 2f6322b1..3d3d58f3 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -7,8 +7,8 @@ import org.scalatest.prop._
 import chisel3.testers.BasicTester
 
 class Coord extends Bundle {
-  val x = UInt(width = 32)
-  val y = UInt(width = 32)
+  val x = UInt.width( 32)
+  val y = UInt.width( 32)
 }
 
 class BundleWire(n: Int) extends Module {
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 638ef9b7..c5aaa554 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -17,11 +17,11 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
 class ComplexAssign(w: Int) extends Module {
   val io = IO(new Bundle {
     val e   = Input(Bool())
-    val in  = Input(new Complex(UInt(width = w), UInt(width = w)))
-    val out = Output(new Complex(UInt(width = w), UInt(width = w)))
+    val in  = Input(new Complex(UInt.width(w), UInt.width(w)))
+    val out = Output(new Complex(UInt.width(w), UInt.width(w)))
   })
   when (io.e) {
-    val tmp = Wire(new Complex(UInt(width = w), UInt(width = w)))
+    val tmp = Wire(new Complex(UInt.width(w), UInt.width(w)))
     tmp := io.in
     io.out.re := tmp.re
     io.out.im := tmp.im
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 770d2e0e..cd8a5d63 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 class UsesDeqIOInfo extends Bundle {
   val test_width = 32
 
-  val info_data = UInt(width = test_width)
+  val info_data = UInt.width(test_width)
 }
 
 class UsesDeqIO extends Module {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index d0d945b7..5e4c897a 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -15,8 +15,8 @@ class GCD extends Module {
     val z  = Output(UInt.width(32))
     val v  = Output(Bool())
   })
-  val x = Reg(UInt(width = 32))
-  val y = Reg(UInt(width = 32))
+  val x = Reg(UInt.width( 32))
+  val y = Reg(UInt.width( 32))
   when (x > y)   { x := x -% y }
   .otherwise     { y := y -% x }
   when (io.e) { x := io.a; y := io.b }
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 2399267e..fa4c4898 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -11,7 +11,7 @@ import chisel3.util._
 class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
 
-  val test = Wire(UInt(width=4))
+  val test = Wire(UInt.width(4))
   assert(test === 7.U)  // allow read references before assign references
 
   test := 13.U
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 5d4bd18d..8b9016b1 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt.Lit(20))
+      val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20))
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
@@ -24,11 +24,11 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
     class RegUnknownWidthTester extends BasicTester {
-      val reg1 = Reg(next=Wire(UInt(width=3)), init=20.U)
+      val reg1 = Reg(next=Wire(UInt.width(3)), init=20.U)
       DataMirror.widthOf(reg1).known should be (false)
       val reg2 = Reg(init=20.U)
       DataMirror.widthOf(reg2).known should be (false)
-      val reg3 = Reg(next=Wire(UInt(width=3)), init=5.U)
+      val reg3 = Reg(next=Wire(UInt.width(3)), init=5.U)
       DataMirror.widthOf(reg3).known should be (false)
     }
     elaborate { new RegUnknownWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 156e5df2..665bb8e6 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -9,17 +9,17 @@ class Risc extends Module {
   val io = IO(new Bundle {
     val isWr   = Input(Bool())
     val wrAddr = Input(UInt.width(8))
-    val wrData = Input(Bits(32))
+    val wrData = Input(Bits.width(32))
     val boot   = Input(Bool())
     val valid  = Output(Bool())
-    val out    = Output(Bits(32))
+    val out    = Output(Bits.width(32))
   })
   val memSize = 256
-  val file = Mem(memSize, Bits(width = 32))
-  val code = Mem(memSize, Bits(width = 32))
+  val file = Mem(memSize, Bits.width(32))
+  val code = Mem(memSize, Bits.width(32))
   val pc   = Reg(init=UInt(0, 8))
 
-  val add_op :: imm_op :: Nil = Enum(Bits(width = 8), 2)
+  val add_op :: imm_op :: Nil = Enum(Bits.width(8), 2)
 
   val inst = code(pc)
   val op   = inst(31,24)
@@ -29,7 +29,7 @@ class Risc extends Module {
 
   val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
   val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
-  val rc = Wire(Bits(width = 32))
+  val rc = Wire(Bits.width(32))
 
   io.valid := Bool(false)
   io.out   := 0.asUInt()
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 440228c9..0c84e62a 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -16,7 +16,7 @@ class ChiselStack(val depth: Int) extends Module {
     val dataOut = Output(UInt.width(32))
   })
 
-  val stack_mem = Mem(depth, UInt(width = 32))
+  val stack_mem = Mem(depth, UInt.width(32))
   val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
   val out       = Reg(init = UInt(0, width = 32))
 
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 75c4278f..40730264 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -11,13 +11,13 @@ import chisel3.util._
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = IO(new Bundle {
-    val wi  = Input(UInt(log2Up(n)))
-    val ri  = Input(UInt(log2Up(n)))
+    val wi  = Input(UInt.width(log2Up(n)))
+    val ri  = Input(UInt.width(log2Up(n)))
     val we  = Input(Bool())
     val  d  = Input(UInt.width(w))
     val  o  = Output(UInt.width(w))
   })
-  val m = Mem(n, UInt(width = w))
+  val m = Mem(n, UInt.width(w))
   io.o := m(io.ri)
   when (io.we) {
     m(io.wi) := io.d
@@ -30,8 +30,8 @@ class Tbl(w: Int, n: Int) extends Module {
 class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), idxs.size)
   val dut = Module(new Tbl(w, n))
-  val vvalues = Vec(values.map(UInt(_)))
-  val vidxs = Vec(idxs.map(UInt(_)))
+  val vvalues = Vec(values.map(UInt.Lit(_)))
+  val vidxs = Vec(idxs.map(UInt.Lit(_)))
   val prev_idx = vidxs(cnt - UInt.Lit(1))
   val prev_value = vvalues(cnt - UInt.Lit(1))
   dut.io.wi := vidxs(cnt)
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 812f822d..69633461 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -86,7 +86,7 @@ class GoodBoolConversion extends Module {
 
 class BadBoolConversion extends Module {
   val io = IO(new Bundle {
-    val u = Input(UInt(width = 5))
+    val u = Input(UInt.width( 5))
     val b = Output(Bool())
   })
   io.b := io.u.toBool
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index cdb1ba8d..22b518a2 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -18,9 +18,9 @@ class ValueTester(w: Int, values: List[Int]) extends BasicTester {
 }
 
 class TabulateTester(n: Int) extends BasicTester {
-  val v = Vec(Range(0, n).map(i => UInt(i * 2)))
-  val x = Vec(Array.tabulate(n){ i => UInt(i * 2) })
-  val u = Vec.tabulate(n)(i => UInt(i*2))
+  val v = Vec(Range(0, n).map(i => UInt.Lit(i * 2)))
+  val x = Vec(Array.tabulate(n){ i => UInt.Lit(i * 2) })
+  val u = Vec.tabulate(n)(i => UInt.Lit(i*2))
 
   assert(v.toBits === x.toBits)
   assert(v.toBits === u.toBits)
@@ -31,7 +31,7 @@ class TabulateTester(n: Int) extends BasicTester {
 
 class ShiftRegisterTester(n: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), n*2)
-  val shifter = Reg(Vec(n, UInt(width = log2Up(n))))
+  val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
   when (cnt >= UInt.Lit(n)) {
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 081990ad..6e1d267d 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -19,7 +19,7 @@ import chisel3.util._
   * IMPORTANT:  The canonical way to initialize a decoupled inteface is still being debated.
   */
 class Packet extends Bundle {
-  val header = UInt(width = 1)
+  val header = UInt.width(1)
 }
 
 /**
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 58aa43e7..2f5c49e4 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -12,7 +12,7 @@ class WhenTester() extends BasicTester {
   val cnt = Counter(4)
   when(Bool(true)) { cnt.inc() }
 
-  val out = Wire(UInt(width=3))
+  val out = Wire(UInt.width(3))
   when(cnt.value === UInt.Lit(0)) {
     out := UInt.Lit(1)
   } .elsewhen (cnt.value === UInt.Lit(1)) {
@@ -34,7 +34,7 @@ class OverlappedWhenTester() extends BasicTester {
   val cnt = Counter(4)
   when(Bool(true)) { cnt.inc() }
 
-  val out = Wire(UInt(width=3))
+  val out = Wire(UInt.width(3))
   when(cnt.value <= UInt.Lit(0)) {
     out := UInt.Lit(1)
   } .elsewhen (cnt.value <= UInt.Lit(1)) {
-- 
cgit v1.2.3


From d269818bdd4f2b71abebfaba9d7f8c9b4d488688 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 21 Jul 2016 09:24:55 -0700
Subject: Ensure test_wire is sinkable.

---
 src/test/scala/chiselTests/TesterDriverSpec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 4c1e41c8..b0f3a981 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -20,7 +20,7 @@ class FinishTester extends BasicTester {
     stop()
   }
 
-  val test_wire = UInt(1, width = test_wire_width)
+  val test_wire = Wire(init=UInt(1, test_wire_width))
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
-- 
cgit v1.2.3


From 7c9043859994b32bb07d2fce4ae61a7a3362a1b3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 21 Jul 2016 17:12:06 -0700
Subject: Introduce chiselCloneType to distinguish from cloneType. Still fails
 one test - DirectionSpec in Direction.scala

---
 src/test/scala/chiselTests/ComplexAssign.scala | 2 +-
 src/test/scala/chiselTests/Module.scala        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index c5aaa554..fce2c602 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -11,7 +11,7 @@ import chisel3.util._
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
-    new Complex(re.cloneType, im.cloneType).asInstanceOf[this.type]
+    new Complex(re.chiselCloneType, im.chiselCloneType).asInstanceOf[this.type]
 }
 
 class ComplexAssign(w: Int) extends Module {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 59451a2b..26953f5f 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
 
 class ModuleWire extends Module {
   val io = IO(new SimpleIO)
-  val inc = Wire(Module(new PlusOne).io.cloneType)
+  val inc = Wire(Module(new PlusOne).io.chiselCloneType)
   inc.in := io.in
   io.out := inc.out
 }
-- 
cgit v1.2.3


From 922d43c085585b9eb0276ff2e8e680ca93ec1c2e Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 08:48:41 -0700
Subject: catch Bad connection exception

---
 src/test/scala/chiselTests/Direction.scala | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index e22e120b..bb01f0eb 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -31,7 +31,15 @@ class DirectionSpec extends ChiselPropSpec {
   }
 
   property("Inputs should not be assignable") {
-    elaborate(new BadDirection)
+    var excepts: Boolean = false
+    try elaborate(new BadDirection)
+    catch {
+      case e: Exception => {
+        excepts = true
+      }
+      // Should except so this is okay
+      // Ideally, would throw and catch more precise exception
+    }
+    assert(excepts, "Bad connection should have thrown exception!")
   }
-
 }
-- 
cgit v1.2.3


From 50518f43cbd9c783633714a26ecdb0f2f18a1142 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 09:19:14 -0700
Subject: Use more idiomatic ScalaTest exception expecting code.

---
 src/test/scala/chiselTests/Direction.scala | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index bb01f0eb..2fe31475 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -22,7 +22,7 @@ class BadDirection extends DirectionHaver {
   io.in := UInt.Lit(0)
 }
 
-class DirectionSpec extends ChiselPropSpec {
+class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
 
   //TODO: In Chisel3 these are actually FIRRTL errors. Remove from tests?
 
@@ -31,15 +31,8 @@ class DirectionSpec extends ChiselPropSpec {
   }
 
   property("Inputs should not be assignable") {
-    var excepts: Boolean = false
-    try elaborate(new BadDirection)
-    catch {
-      case e: Exception => {
-        excepts = true
-      }
-      // Should except so this is okay
-      // Ideally, would throw and catch more precise exception
+    a[ChiselException] should be thrownBy {
+     elaborate(new BadDirection)
     }
-    assert(excepts, "Bad connection should have thrown exception!")
   }
 }
-- 
cgit v1.2.3


From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 14:06:51 -0700
Subject: Minimize differences with master. Remove .Lit(x) usage. Undo
 "private" scope change. Change "firing" back to "fire". Add package level
 NODIR definition.

---
 src/test/scala/chiselTests/Assert.scala           |  4 +--
 src/test/scala/chiselTests/BitwiseOps.scala       |  8 ++---
 src/test/scala/chiselTests/BlackBox.scala         | 30 +++++++++----------
 src/test/scala/chiselTests/BundleWire.scala       |  8 ++---
 src/test/scala/chiselTests/ComplexAssign.scala    | 12 ++++----
 src/test/scala/chiselTests/Counter.scala          |  8 ++---
 src/test/scala/chiselTests/Decoder.scala          |  2 +-
 src/test/scala/chiselTests/Direction.scala        |  4 +--
 src/test/scala/chiselTests/MemorySearch.scala     |  6 ++--
 src/test/scala/chiselTests/Module.scala           |  4 +--
 src/test/scala/chiselTests/MulLookup.scala        |  6 ++--
 src/test/scala/chiselTests/Printf.scala           |  6 ++--
 src/test/scala/chiselTests/Reg.scala              |  2 +-
 src/test/scala/chiselTests/Risc.scala             |  2 +-
 src/test/scala/chiselTests/SIntOps.scala          |  6 ++--
 src/test/scala/chiselTests/Stack.scala            | 12 ++++----
 src/test/scala/chiselTests/Tbl.scala              | 10 +++----
 src/test/scala/chiselTests/TesterDriverSpec.scala |  4 +--
 src/test/scala/chiselTests/UIntOps.scala          |  4 +--
 src/test/scala/chiselTests/Vec.scala              | 12 ++++----
 src/test/scala/chiselTests/When.scala             | 36 +++++++++++------------
 21 files changed, 93 insertions(+), 93 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index bf3c8092..efc2e1e7 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester {
 
 class PipelinedResetModule extends Module {
   val io = IO(new Bundle { })
-  val a = Reg(init = UInt.Lit(0xbeef))
-  val b = Reg(init = UInt.Lit(0xbeef))
+  val a = Reg(init = UInt(0xbeef))
+  val b = Reg(init = UInt(0xbeef))
   assert(a === b)
 }
 
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 0aaa3c57..08999a1b 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -11,10 +11,10 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
   val a = UInt(_a, w)
   val b = UInt(_b, w)
-  assert(~a === UInt.Lit(mask & ~_a))
-  assert((a & b) === UInt.Lit(_a & _b))
-  assert((a | b) === UInt.Lit(_a | _b))
-  assert((a ^ b) === UInt.Lit(_a ^ _b))
+  assert(~a === UInt(mask & ~_a))
+  assert((a & b) === UInt(_a & _b))
+  assert((a | b) === UInt(_a | _b))
+  assert((a ^ b) === UInt(_a ^ _b))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 9b43f0ef..c1154883 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -35,11 +35,11 @@ class BlackBoxTester extends BasicTester {
   val blackBoxPos = Module(new BlackBoxInverter)
   val blackBoxNeg = Module(new BlackBoxInverter)
 
-  blackBoxPos.io.in := UInt.Lit(1)
-  blackBoxNeg.io.in := UInt.Lit(0)
+  blackBoxPos.io.in := UInt(1)
+  blackBoxNeg.io.in := UInt(0)
 
-  assert(blackBoxNeg.io.out === UInt.Lit(1))
-  assert(blackBoxPos.io.out === UInt.Lit(0))
+  assert(blackBoxNeg.io.out === UInt(1))
+  assert(blackBoxPos.io.out === UInt(0))
   stop()
 }
 
@@ -54,15 +54,15 @@ class MultiBlackBoxTester extends BasicTester {
   val blackBoxPassPos = Module(new BlackBoxPassthrough)
   val blackBoxPassNeg = Module(new BlackBoxPassthrough)
 
-  blackBoxInvPos.io.in := UInt.Lit(1)
-  blackBoxInvNeg.io.in := UInt.Lit(0)
-  blackBoxPassPos.io.in := UInt.Lit(1)
-  blackBoxPassNeg.io.in := UInt.Lit(0)
+  blackBoxInvPos.io.in := UInt(1)
+  blackBoxInvNeg.io.in := UInt(0)
+  blackBoxPassPos.io.in := UInt(1)
+  blackBoxPassNeg.io.in := UInt(0)
 
-  assert(blackBoxInvNeg.io.out === UInt.Lit(1))
-  assert(blackBoxInvPos.io.out === UInt.Lit(0))
-  assert(blackBoxPassNeg.io.out === UInt.Lit(0))
-  assert(blackBoxPassPos.io.out === UInt.Lit(1))
+  assert(blackBoxInvNeg.io.out === UInt(1))
+  assert(blackBoxInvPos.io.out === UInt(0))
+  assert(blackBoxPassNeg.io.out === UInt(0))
+  assert(blackBoxPassPos.io.out === UInt(1))
   stop()
 }
 
@@ -77,7 +77,7 @@ class BlackBoxWithClockTester extends BasicTester {
   blackBox.io.in := impetus
   model := impetus
 
-  when(cycles > UInt.Lit(0)) {
+  when(cycles > UInt(0)) {
     assert(blackBox.io.out === model)
   }
   when(end) { stop() }
@@ -98,8 +98,8 @@ class BlackBoxWithParamsTester extends BasicTester {
 
   val (cycles, end) = Counter(Bool(true), 4)
 
-  assert(blackBoxOne.io.out  === UInt.Lit(1))
-  assert(blackBoxFour.io.out === UInt.Lit(4))
+  assert(blackBoxOne.io.out  === UInt(1))
+  assert(blackBoxFour.io.out === UInt(4))
 
   when(end) { stop() }
 }
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 3d3d58f3..0071041c 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -25,11 +25,11 @@ class BundleWire(n: Int) extends Module {
 
 class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new BundleWire(n))
-  dut.io.in.x := UInt.Lit(x)
-  dut.io.in.y := UInt.Lit(y)
+  dut.io.in.x := UInt(x)
+  dut.io.in.y := UInt(y)
   for (elt <- dut.io.outs) {
-    assert(elt.x === UInt.Lit(x))
-    assert(elt.y === UInt.Lit(y))
+    assert(elt.x === UInt(x))
+    assert(elt.y === UInt(y))
   }
   stop()
 }
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index fce2c602..0a1f31cc 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -26,19 +26,19 @@ class ComplexAssign(w: Int) extends Module {
     io.out.re := tmp.re
     io.out.im := tmp.im
   } .otherwise {
-    io.out.re := UInt.Lit(0)
-    io.out.im := UInt.Lit(0)
+    io.out.re := UInt(0)
+    io.out.im := UInt(0)
   }
 }
 
 class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), enList.size)
   val dut = Module(new ComplexAssign(32))
-  dut.io.in.re := UInt.Lit(re)
-  dut.io.in.im := UInt.Lit(im)
+  dut.io.in.re := UInt(re)
+  dut.io.in.im := UInt(im)
   dut.io.e := Vec(enList.map(Bool(_)))(cnt)
-  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt.Lit(0))
-  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt.Lit(0))
+  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0))
+  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0))
   assert(re_correct && im_correct)
   when(wrap) {
     stop()
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index af2fa550..69d8a44a 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -12,20 +12,20 @@ import chisel3.util._
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
   when(Bool(true)) { cnt.inc() }
-  when(cnt.value === UInt.Lit(max-1)) {
+  when(cnt.value === UInt(max-1)) {
     stop()
   }
 }
 
 class EnableTester(seed: Int) extends BasicTester {
-  val ens = Reg(init = UInt.Lit(seed))
+  val ens = Reg(init = UInt(seed))
   ens := ens >> 1
 
   val (cntEnVal, _) = Counter(ens(0), 32)
   val (_, done) = Counter(Bool(true), 33)
 
   when(done) {
-    assert(cntEnVal === UInt.Lit(popCount(seed)))
+    assert(cntEnVal === UInt(popCount(seed)))
     stop()
   }
 }
@@ -33,7 +33,7 @@ class EnableTester(seed: Int) extends BasicTester {
 class WrapTester(max: Int) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), max)
   when(wrap) {
-    assert(cnt === UInt.Lit(max - 1))
+    assert(cnt === UInt(max - 1))
     stop()
   }
 }
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index ee892fc5..b50a80c0 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -24,7 +24,7 @@ class DecoderTester(pairs: List[(String, String)]) extends BasicTester {
   val dut = Module(new Decoder(bitpats))
   dut.io.inst := Vec(insts.map(UInt(_)))(cnt)
   when(!dut.io.matched) {
-    assert(cnt === UInt.Lit(0))
+    assert(cnt === UInt(0))
     stop()
   }
   when(wrap) {
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 2fe31475..83484a64 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -15,11 +15,11 @@ class DirectionHaver extends Module {
 }
 
 class GoodDirection extends DirectionHaver {
-  io.out := UInt.Lit(0)
+  io.out := UInt(0)
 }
 
 class BadDirection extends DirectionHaver {
-  io.in := UInt.Lit(0)
+  io.in := UInt(0)
 }
 
 class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index e4063532..1d09f3c5 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -17,11 +17,11 @@ class MemorySearch extends Module {
   val elts  = Vec(vals.map(UInt(_,4)))
   // val elts  = Mem(UInt(width = 32), 8) TODO ????
   val elt  = elts(index)
-  val end  = !io.en && ((elt === io.target) || (index === UInt.Lit(7)))
+  val end  = !io.en && ((elt === io.target) || (index === UInt(7)))
   when (io.en) {
-    index := UInt.Lit(0)
+    index := UInt(0)
   } .elsewhen (!end) {
-    index := index +% UInt.Lit(1)
+    index := index +% UInt(1)
   }
   io.done    := end
   io.address := index
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 26953f5f..7a4050db 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -16,8 +16,8 @@ class PlusOne extends Module {
 
 class ModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Input(Vec(n, UInt.Lit(32)))
-    val outs = Output(Vec(n, UInt.Lit(32)))
+    val ins  = Input(Vec(n, UInt(32)))
+    val outs = Output(Vec(n, UInt(32)))
   })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 16a29104..26ee4e03 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -24,9 +24,9 @@ class MulLookup(val w: Int) extends Module {
 
 class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new MulLookup(w))
-  dut.io.x := UInt.Lit(x)
-  dut.io.y := UInt.Lit(y)
-  assert(dut.io.z === UInt.Lit(x * y))
+  dut.io.x := UInt(x)
+  dut.io.y := UInt(y)
+  assert(dut.io.z === UInt(x * y))
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index 92b6fee1..c872fde4 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
-  val x = UInt.Lit(254)
+  val x = UInt(254)
   printf("x=%x", x)
   stop()
 }
@@ -18,8 +18,8 @@ class ASCIIPrintfTester() extends BasicTester {
 }
 
 class MultiPrintfTester() extends BasicTester {
-  val x = UInt.Lit(254)
-  val y = UInt.Lit(255)
+  val x = UInt(254)
+  val y = UInt(255)
   printf("x=%x y=%x", x, y)
   stop()
 }
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 8b9016b1..b66d7cb4 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20))
+      val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt(20))
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 665bb8e6..6d5a0a76 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -38,7 +38,7 @@ class Risc extends Module {
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
   } .elsewhen (io.boot) {
-    pc := UInt.Lit(0)
+    pc := UInt(0)
   } .otherwise {
     switch(op) {
       is(add_op) { rc := ra +% rb }
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index d827c096..392c4803 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -32,9 +32,9 @@ class SIntOps extends Module {
   io.subout := a -% b
   // TODO:
   //io.timesout := (a * b)(15, 0)
-  //io.divout := a / Mux(b === SInt.Lit(0), SInt.Lit(1), b)
+  //io.divout := a / Mux(b === SInt(0), SInt(1), b)
   //io.divout := (a / b)(15, 0)
-  //io.modout := SInt.Lit(0)
+  //io.modout := SInt(0)
   //io.lshiftout := (a << 12)(15, 0) //  (a << ub(3, 0))(15, 0).toSInt
   io.rshiftout := (a >> 8) // (a >> ub).toSInt
   io.lessout := a < b
@@ -44,7 +44,7 @@ class SIntOps extends Module {
   io.lesseqout := a <= b
   io.greateqout := a >= b
   // io.negout := -a(15, 0).toSInt
-  io.negout := (SInt.Lit(0) -% a)
+  io.negout := (SInt(0) -% a)
 }
 
 /*
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 0c84e62a..a72af928 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module {
   val out       = Reg(init = UInt(0, width = 32))
 
   when (io.en) {
-    when(io.push && (sp < UInt.Lit(depth))) {
+    when(io.push && (sp < UInt(depth))) {
       stack_mem(sp) := io.dataIn
-      sp := sp +% UInt.Lit(1)
-    } .elsewhen(io.pop && (sp > UInt.Lit(0))) {
-      sp := sp -% UInt.Lit(1)
+      sp := sp +% UInt(1)
+    } .elsewhen(io.pop && (sp > UInt(0))) {
+      sp := sp -% UInt(1)
     }
-    when (sp > UInt.Lit(0)) {
-      out := stack_mem(sp -% UInt.Lit(1))
+    when (sp > UInt(0)) {
+      out := stack_mem(sp -% UInt(1))
     }
   }
   io.dataOut := out
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 40730264..66a06435 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -30,15 +30,15 @@ class Tbl(w: Int, n: Int) extends Module {
 class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester {
   val (cnt, wrap) = Counter(Bool(true), idxs.size)
   val dut = Module(new Tbl(w, n))
-  val vvalues = Vec(values.map(UInt.Lit(_)))
-  val vidxs = Vec(idxs.map(UInt.Lit(_)))
-  val prev_idx = vidxs(cnt - UInt.Lit(1))
-  val prev_value = vvalues(cnt - UInt.Lit(1))
+  val vvalues = Vec(values.map(UInt(_)))
+  val vidxs = Vec(idxs.map(UInt(_)))
+  val prev_idx = vidxs(cnt - UInt(1))
+  val prev_value = vvalues(cnt - UInt(1))
   dut.io.wi := vidxs(cnt)
   dut.io.ri := prev_idx
   dut.io.we := Bool(true) //TODO enSequence
   dut.io.d := vvalues(cnt)
-  when (cnt > UInt.Lit(0)) {
+  when (cnt > UInt(0)) {
     when (prev_idx === vidxs(cnt)) {
       assert(dut.io.o === vvalues(cnt))
     } .otherwise {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index b0f3a981..23eed15f 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -24,13 +24,13 @@ class FinishTester extends BasicTester {
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
-  assert(test_wire === UInt.Lit(test_wire_override_value))
+  assert(test_wire === UInt(test_wire_override_value))
 
   /** In finish we use last connect semantics to alter the test_wire in the circuit
     * with a new value
     */
   override def finish(): Unit = {
-    test_wire := UInt.Lit(test_wire_override_value)
+    test_wire := UInt(test_wire_override_value)
   }
 }
 
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 69633461..ad5aecd8 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -31,10 +31,10 @@ class UIntOps extends Module {
   io.addout := a +% b
   io.subout := a -% b
   io.timesout := (a * b)(15, 0)
-  io.divout := a / Mux(b === UInt.Lit(0), UInt.Lit(1), b)
+  io.divout := a / Mux(b === UInt(0), UInt(1), b)
   // io.modout := a % b
   // TODO:
-  io.modout := UInt.Lit(0)
+  io.modout := UInt(0)
   io.lshiftout := (a << b(3, 0))(15, 0)
   io.rshiftout := a >> b
   io.lessout := a < b
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 22b518a2..e8bd66bd 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -12,15 +12,15 @@ import chisel3.util._
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
   for ((a,b) <- v.zip(values)) {
-    assert(a === UInt.Lit(b))
+    assert(a === UInt(b))
   }
   stop()
 }
 
 class TabulateTester(n: Int) extends BasicTester {
-  val v = Vec(Range(0, n).map(i => UInt.Lit(i * 2)))
-  val x = Vec(Array.tabulate(n){ i => UInt.Lit(i * 2) })
-  val u = Vec.tabulate(n)(i => UInt.Lit(i*2))
+  val v = Vec(Range(0, n).map(i => UInt(i * 2)))
+  val x = Vec(Array.tabulate(n){ i => UInt(i * 2) })
+  val u = Vec.tabulate(n)(i => UInt(i*2))
 
   assert(v.toBits === x.toBits)
   assert(v.toBits === u.toBits)
@@ -34,8 +34,8 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
   val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
-  when (cnt >= UInt.Lit(n)) {
-    val expected = cnt - UInt.Lit(n)
+  when (cnt >= UInt(n)) {
+    val expected = cnt - UInt(n)
     assert(shifter(0) === expected)
   }
   when (wrap) {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 2f5c49e4..07ab3444 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -13,19 +13,19 @@ class WhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt.width(3))
-  when(cnt.value === UInt.Lit(0)) {
-    out := UInt.Lit(1)
-  } .elsewhen (cnt.value === UInt.Lit(1)) {
-    out := UInt.Lit(2)
-  } .elsewhen (cnt.value === UInt.Lit(2)) {
-    out := UInt.Lit(3)
+  when(cnt.value === UInt(0)) {
+    out := UInt(1)
+  } .elsewhen (cnt.value === UInt(1)) {
+    out := UInt(2)
+  } .elsewhen (cnt.value === UInt(2)) {
+    out := UInt(3)
   } .otherwise {
-    out := UInt.Lit(0)
+    out := UInt(0)
   }
 
-  assert(out === cnt.value + UInt.Lit(1))
+  assert(out === cnt.value + UInt(1))
 
-  when(cnt.value === UInt.Lit(3)) {
+  when(cnt.value === UInt(3)) {
     stop()
   }
 }
@@ -35,19 +35,19 @@ class OverlappedWhenTester() extends BasicTester {
   when(Bool(true)) { cnt.inc() }
 
   val out = Wire(UInt.width(3))
-  when(cnt.value <= UInt.Lit(0)) {
-    out := UInt.Lit(1)
-  } .elsewhen (cnt.value <= UInt.Lit(1)) {
-    out := UInt.Lit(2)
-  } .elsewhen (cnt.value <= UInt.Lit(2)) {
-    out := UInt.Lit(3)
+  when(cnt.value <= UInt(0)) {
+    out := UInt(1)
+  } .elsewhen (cnt.value <= UInt(1)) {
+    out := UInt(2)
+  } .elsewhen (cnt.value <= UInt(2)) {
+    out := UInt(3)
   } .otherwise {
-    out := UInt.Lit(0)
+    out := UInt(0)
   }
 
-  assert(out === cnt.value + UInt.Lit(1))
+  assert(out === cnt.value + UInt(1))
 
-  when(cnt.value === UInt.Lit(3)) {
+  when(cnt.value === UInt(3)) {
     stop()
   }
 }
-- 
cgit v1.2.3


From e09a09e3f4e5d6d8650b1db4add96c0a5b09e8ca Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 25 Jul 2016 16:36:06 -0700
Subject: Enable current (chisel2-style) compatibility mode.

---
 src/test/scala/chiselTests/IOCompatibility.scala | 45 ++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 src/test/scala/chiselTests/IOCompatibility.scala

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
new file mode 100644
index 00000000..b904d77e
--- /dev/null
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -0,0 +1,45 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+
+class IOCSimpleIO extends Bundle {
+  val in  = UInt(INPUT,  32)
+  val out = UInt(OUTPUT, 32)
+}
+
+class IOCPlusOne extends Module {
+  val io = new IOCSimpleIO
+  io.out := io.in + UInt(1)
+}
+
+class IOCModuleVec(val n: Int) extends Module {
+  val io = new Bundle {
+    val ins  = Vec(n, UInt(INPUT,  32))
+    val outs = Vec(n, UInt(OUTPUT, 32))
+  }
+  val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
+  for (i <- 0 until n) {
+    pluses(i).in := io.ins(i)
+    io.outs(i)   := pluses(i).out
+  }
+}
+
+class IOCModuleWire extends Module {
+  val io = new IOCSimpleIO
+  val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType)
+  inc.in := io.in
+  io.out := inc.out
+}
+
+class IOCompatibilitySpec extends ChiselPropSpec {
+
+  property("IOCModuleVec should elaborate") {
+    elaborate { new IOCModuleVec(2) }
+  }
+
+  property("IOCModuleWire should elaborate") {
+    elaborate { new IOCModuleWire }
+  }
+}
-- 
cgit v1.2.3


From e065416d59871d790cca9d75dc9a40fcc7b52015 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 09:13:45 -0700
Subject: Additional compatibility code.

---
 src/test/scala/chiselTests/DeqIOSpec.scala      | 4 ++--
 src/test/scala/chiselTests/VectorPacketIO.scala | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index cd8a5d63..d41c50e5 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -17,8 +17,8 @@ class UsesDeqIOInfo extends Bundle {
 
 class UsesDeqIO extends Module {
   val io = IO(new Bundle {
-    val in = DeqIO(new UsesDeqIOInfo)
-    val out = EnqIO(new UsesDeqIOInfo)
+    val in = chisel3.util.DeqIO(new UsesDeqIOInfo)
+    val out = chisel3.util.EnqIO(new UsesDeqIOInfo)
   })
 }
 
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 6e1d267d..86c0d66f 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -28,8 +28,8 @@ class Packet extends Bundle {
   * The problem does not occur if the Vec is taken out
   */
 class VectorPacketIO(n: Int) extends Bundle {
-  val ins  = Vec(n, DeqIO(new Packet()))
-  val outs = Vec(n, EnqIO(new Packet()))
+  val ins  = Vec(n, chisel3.util.DeqIO(new Packet()))
+  val outs = Vec(n, chisel3.util.EnqIO(new Packet()))
 }
 
 /**
-- 
cgit v1.2.3


From 089987c3e0b2bc390935a4d9d44db38a18c47901 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 10:29:13 -0700
Subject: Correct EnqIO/DeqIO Flipped-ness.

---
 src/test/scala/chiselTests/VectorPacketIO.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 86c0d66f..b8e3a154 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -41,8 +41,8 @@ class BrokenVectorPacketModule extends Module {
   val io = IO(new VectorPacketIO(n))
 
   /* the following method of initializing the circuit may change in the future */
-  io.ins.foreach(_.noenq())
-  io.outs.foreach(_.nodeq())
+  io.ins.foreach(_.nodeq())
+  io.outs.foreach(_.noenq())
 }
 
 class VectorPacketIOUnitTester extends BasicTester {
-- 
cgit v1.2.3


From 138329479914ac37b49a5a44841dc1de2929dca5 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 10:36:55 -0700
Subject: More compatibility fixes

---
 src/test/scala/chiselTests/Direction.scala       | 2 +-
 src/test/scala/chiselTests/IOCompatibility.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 83484a64..949b92ed 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -31,7 +31,7 @@ class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
   }
 
   property("Inputs should not be assignable") {
-    a[ChiselException] should be thrownBy {
+    a[Exception] should be thrownBy {
      elaborate(new BadDirection)
     }
   }
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index b904d77e..edbd3d09 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -2,7 +2,7 @@
 
 package chiselTests
 
-import chisel3._
+import Chisel._
 
 class IOCSimpleIO extends Bundle {
   val in  = UInt(INPUT,  32)
-- 
cgit v1.2.3


From 6df3a785f8abe706838bc5b4b35c3374b6512f96 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 12:17:48 -0700
Subject: Pass compileOptions as an implicit Module parameter.

---
 src/test/scala/chiselTests/Assert.scala              | 1 +
 src/test/scala/chiselTests/BetterNamingTests.scala   | 1 +
 src/test/scala/chiselTests/BundleWire.scala          | 1 +
 src/test/scala/chiselTests/ComplexAssign.scala       | 1 +
 src/test/scala/chiselTests/Decoder.scala             | 1 +
 src/test/scala/chiselTests/DeqIOSpec.scala           | 1 +
 src/test/scala/chiselTests/Direction.scala           | 1 +
 src/test/scala/chiselTests/EnableShiftRegister.scala | 1 +
 src/test/scala/chiselTests/GCD.scala                 | 1 +
 src/test/scala/chiselTests/IOCompatibility.scala     | 1 +
 src/test/scala/chiselTests/LFSR16.scala              | 1 +
 src/test/scala/chiselTests/MemorySearch.scala        | 1 +
 src/test/scala/chiselTests/Module.scala              | 1 +
 src/test/scala/chiselTests/MulLookup.scala           | 1 +
 src/test/scala/chiselTests/OptionBundle.scala        | 1 +
 src/test/scala/chiselTests/Padding.scala             | 1 +
 src/test/scala/chiselTests/ParameterizedModule.scala | 1 +
 src/test/scala/chiselTests/Risc.scala                | 1 +
 src/test/scala/chiselTests/SIntOps.scala             | 1 +
 src/test/scala/chiselTests/Stack.scala               | 1 +
 src/test/scala/chiselTests/Tbl.scala                 | 1 +
 src/test/scala/chiselTests/UIntOps.scala             | 1 +
 src/test/scala/chiselTests/VectorPacketIO.scala      | 1 +
 src/test/scala/chiselTests/VendingMachine.scala      | 1 +
 24 files changed, 24 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index efc2e1e7..0afeac7b 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -6,6 +6,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class FailingAssertTester() extends BasicTester {
   assert(Bool(false))
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
index 44fc542a..7d69d604 100644
--- a/src/test/scala/chiselTests/BetterNamingTests.scala
+++ b/src/test/scala/chiselTests/BetterNamingTests.scala
@@ -4,6 +4,7 @@ import org.scalatest.{FlatSpec, Matchers}
 import collection.mutable
 
 import Chisel._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 
 // Defined outside of the class so we don't get $ in name
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 0071041c..c72ad78d 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -5,6 +5,7 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
+import chisel3.Strict.StrictCompileOptions
 
 class Coord extends Bundle {
   val x = UInt.width( 32)
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 0a1f31cc..efca4947 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -8,6 +8,7 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index b50a80c0..758b4f6d 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -9,6 +9,7 @@ import org.scalacheck._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index d41c50e5..9ad776da 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -5,6 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 /**
   * Created by chick on 2/8/16.
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 949b92ed..ec1232e2 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -6,6 +6,7 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class DirectionHaver extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 5f3e0dd1..ee568be5 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -3,6 +3,7 @@
 package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index d683ce34..8c298d14 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -6,6 +6,7 @@ import chisel3._
 import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class GCD extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index edbd3d09..c247973d 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -3,6 +3,7 @@
 package chiselTests
 
 import Chisel._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class IOCSimpleIO extends Bundle {
   val in  = UInt(INPUT,  32)
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index b13b67e3..b1b2b415 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -5,6 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class LFSR16 extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 1d09f3c5..b05a112b 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.testers.BasicTester
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class MemorySearch extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 7a4050db..8d72fc44 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -3,6 +3,7 @@
 package chiselTests
 
 import chisel3._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class SimpleIO extends Bundle {
   val in  = Input(UInt.width(32))
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 26ee4e03..63a0a7c7 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -6,6 +6,7 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index 8e4c7579..236e1007 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -5,6 +5,7 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class OptionBundle(hasIn: Boolean) extends Bundle {
   val in = if (hasIn) {
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 42df6802..ca769b49 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -3,6 +3,7 @@
 package chiselTests
 
 import chisel3._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class Padder extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index 14b21631..2929cccc 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -5,6 +5,7 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class ParameterizedModule(invert: Boolean) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 6d5a0a76..f255f996 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class Risc extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 392c4803..227a4514 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.testers.BasicTester
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class SIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index a72af928..9ccfc9ee 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -6,6 +6,7 @@ import scala.collection.mutable.Stack
 
 import chisel3._
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class ChiselStack(val depth: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 66a06435..2aa8b031 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -8,6 +8,7 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index ad5aecd8..836ad864 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -5,6 +5,7 @@ package chiselTests
 import chisel3._
 import org.scalatest._
 import chisel3.testers.BasicTester
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class UIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index b8e3a154..66b599a9 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -5,6 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 /**
   * This test used to fail when assignment statements were
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 00b1e7de..89060941 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util._
+import chisel3.NotStrict.NotStrictCompileOptions
 
 class VendingMachine extends Module {
   val io = IO(new Bundle {
-- 
cgit v1.2.3


From 62817134d222747f1eab34626fe7b1bb13b9f6df Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 13:45:05 -0700
Subject: Rename CompileOptions implicit objects.

---
 src/test/scala/chiselTests/Assert.scala              | 2 +-
 src/test/scala/chiselTests/BetterNamingTests.scala   | 2 +-
 src/test/scala/chiselTests/BundleWire.scala          | 2 +-
 src/test/scala/chiselTests/ComplexAssign.scala       | 2 +-
 src/test/scala/chiselTests/Decoder.scala             | 2 +-
 src/test/scala/chiselTests/DeqIOSpec.scala           | 2 +-
 src/test/scala/chiselTests/Direction.scala           | 2 +-
 src/test/scala/chiselTests/EnableShiftRegister.scala | 2 +-
 src/test/scala/chiselTests/GCD.scala                 | 2 +-
 src/test/scala/chiselTests/IOCompatibility.scala     | 2 +-
 src/test/scala/chiselTests/LFSR16.scala              | 2 +-
 src/test/scala/chiselTests/MemorySearch.scala        | 2 +-
 src/test/scala/chiselTests/Module.scala              | 2 +-
 src/test/scala/chiselTests/MulLookup.scala           | 2 +-
 src/test/scala/chiselTests/OptionBundle.scala        | 2 +-
 src/test/scala/chiselTests/Padding.scala             | 2 +-
 src/test/scala/chiselTests/ParameterizedModule.scala | 2 +-
 src/test/scala/chiselTests/Risc.scala                | 2 +-
 src/test/scala/chiselTests/SIntOps.scala             | 2 +-
 src/test/scala/chiselTests/Stack.scala               | 2 +-
 src/test/scala/chiselTests/Tbl.scala                 | 2 +-
 src/test/scala/chiselTests/UIntOps.scala             | 2 +-
 src/test/scala/chiselTests/VectorPacketIO.scala      | 2 +-
 src/test/scala/chiselTests/VendingMachine.scala      | 2 +-
 24 files changed, 24 insertions(+), 24 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 0afeac7b..509dedbd 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -6,7 +6,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class FailingAssertTester() extends BasicTester {
   assert(Bool(false))
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
index 7d69d604..a480da98 100644
--- a/src/test/scala/chiselTests/BetterNamingTests.scala
+++ b/src/test/scala/chiselTests/BetterNamingTests.scala
@@ -4,7 +4,7 @@ import org.scalatest.{FlatSpec, Matchers}
 import collection.mutable
 
 import Chisel._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 
 // Defined outside of the class so we don't get $ in name
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index c72ad78d..15c5d5f8 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -5,7 +5,7 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
-import chisel3.Strict.StrictCompileOptions
+import chisel3.Strict.CompileOptions
 
 class Coord extends Bundle {
   val x = UInt.width( 32)
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index efca4947..48a673cf 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -8,7 +8,7 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 758b4f6d..35c83a8a 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -9,7 +9,7 @@ import org.scalacheck._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 9ad776da..31508149 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 /**
   * Created by chick on 2/8/16.
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index ec1232e2..7cfe8268 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -6,7 +6,7 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class DirectionHaver extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index ee568be5..15173e0f 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -3,7 +3,7 @@
 package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index 8c298d14..21082fc9 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -6,7 +6,7 @@ import chisel3._
 import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class GCD extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index c247973d..aa3bd962 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -3,7 +3,7 @@
 package chiselTests
 
 import Chisel._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class IOCSimpleIO extends Bundle {
   val in  = UInt(INPUT,  32)
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index b1b2b415..3b2b28f6 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class LFSR16 extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index b05a112b..a2a8eb8b 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class MemorySearch extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 8d72fc44..1f0ab084 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -3,7 +3,7 @@
 package chiselTests
 
 import chisel3._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class SimpleIO extends Bundle {
   val in  = Input(UInt.width(32))
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 63a0a7c7..4548ae40 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -6,7 +6,7 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index 236e1007..d2165f62 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -5,7 +5,7 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class OptionBundle(hasIn: Boolean) extends Bundle {
   val in = if (hasIn) {
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index ca769b49..c7265c6c 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -3,7 +3,7 @@
 package chiselTests
 
 import chisel3._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class Padder extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index 2929cccc..b75d898b 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -5,7 +5,7 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class ParameterizedModule(invert: Boolean) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index f255f996..e27cbdca 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class Risc extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 227a4514..d070295c 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class SIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 9ccfc9ee..f1210260 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -6,7 +6,7 @@ import scala.collection.mutable.Stack
 
 import chisel3._
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class ChiselStack(val depth: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 2aa8b031..df8ce02c 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -8,7 +8,7 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 836ad864..237cea16 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import org.scalatest._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class UIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 66b599a9..588e1ce2 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 /**
   * This test used to fail when assignment statements were
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 89060941..2a0ac824 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util._
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 class VendingMachine extends Module {
   val io = IO(new Bundle {
-- 
cgit v1.2.3


From 1973e4d7333e2c57be4bcb7204210ecafdacab93 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 17:04:51 -0700
Subject: Check module-specific compile options. Import
 chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 180 +++++++++++++++++++++
 1 file changed, 180 insertions(+)
 create mode 100644 src/test/scala/chiselTests/CompileOptionsTest.scala

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
new file mode 100644
index 00000000..5bd3f959
--- /dev/null
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -0,0 +1,180 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import org.scalatest._
+import chisel3._
+import chisel3.core.Binding.BindingException
+import chisel3.testers.BasicTester
+
+class CompileOptionsSpec extends ChiselFlatSpec {
+
+  class SmallBundle extends Bundle {
+    val f1 = UInt(width = 4)
+    val f2 = UInt(width = 5)
+    override def cloneType: this.type = (new SmallBundle).asInstanceOf[this.type]
+  }
+  class BigBundle extends SmallBundle {
+    val f3 = UInt(width = 6)
+    override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type]
+  }
+
+  "A Module with missing bundle fields when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [ChiselException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class ConnectFieldMismatchModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(new SmallBundle)
+          val out = Output(new BigBundle)
+        })
+        io.out := io.in
+      }
+      elaborate { new ConnectFieldMismatchModule() }
+    }
+  }
+
+  "A Module with missing bundle fields when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class ConnectFieldMismatchModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(new SmallBundle)
+        val out = Output(new BigBundle)
+      })
+      io.out := io.in
+    }
+    elaborate { new ConnectFieldMismatchModule() }
+  }
+
+  "A Module in which a Reg is created with a bound type when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [BindingException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class CreateRegFromBoundTypeModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(new SmallBundle)
+          val out = Output(new BigBundle)
+        })
+        val badReg = Reg(UInt(7, width=4))
+      }
+      elaborate { new CreateRegFromBoundTypeModule() }
+    }
+  }
+
+  "A Module in which a Reg is created with a bound type when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class CreateRegFromBoundTypeModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(new SmallBundle)
+        val out = Output(new BigBundle)
+      })
+      val badReg = Reg(UInt(7, width=4))
+    }
+    elaborate { new CreateRegFromBoundTypeModule() }
+  }
+
+
+  "A Module with wrapped IO when compiled with Strict.CompileOption " should "not throw an exception" in {
+    import chisel3.Strict.CompileOptions
+
+    class RequireIOWrapModule extends Module {
+      val io = IO(new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      })
+      io.out := io.in(1)
+    }
+    elaborate { new RequireIOWrapModule() }
+}
+
+  "A Module with unwrapped IO when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class RequireIOWrapModule extends Module {
+      val io = new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      }
+      io.out := io.in(1)
+    }
+      elaborate { new RequireIOWrapModule() }
+  }
+
+  "A Module connecting output as source to input as sink when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [ChiselException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class SimpleModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(width = 3))
+          val out = Output(UInt(width = 4))
+        })
+      }
+      class SwappedConnectionModule extends SimpleModule {
+        val child = Module(new SimpleModule)
+        io.in := child.io.out
+      }
+      elaborate { new SwappedConnectionModule() }
+    }
+  }
+
+  "A Module connecting output as source to input as sink when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class SimpleModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(UInt(width = 3))
+        val out = Output(UInt(width = 4))
+      })
+    }
+    class SwappedConnectionModule extends SimpleModule {
+      val child = Module(new SimpleModule)
+      io.in := child.io.out
+    }
+    elaborate { new SwappedConnectionModule() }
+  }
+
+  "A Module with directionless connections when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [ChiselException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class SimpleModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(width = 3))
+          val out = Output(UInt(width = 4))
+        })
+        val noDir = Wire(UInt(width = 3))
+      }
+
+      class DirectionLessConnectionModule extends SimpleModule {
+        val a = UInt(0, width = 3)
+        val b = Wire(UInt(width = 3))
+        val child = Module(new SimpleModule)
+        b := child.noDir
+      }
+      elaborate { new DirectionLessConnectionModule() }
+    }
+  }
+
+  "A Module with directionless connections when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class SimpleModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(UInt(width = 3))
+        val out = Output(UInt(width = 4))
+      })
+      val noDir = Wire(UInt(width = 3))
+    }
+
+    class DirectionLessConnectionModule extends SimpleModule {
+      val a = UInt(0, width = 3)
+      val b = Wire(UInt(width = 3))
+      val child = Module(new SimpleModule)
+      b := child.noDir
+    }
+    elaborate { new DirectionLessConnectionModule() }
+  }
+}
-- 
cgit v1.2.3


From 5df671531c4a83dc17ecfdce6aecc8789d50fa7f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 30 Aug 2016 09:18:35 -0700
Subject: Add abstract classes with explicit connection checking options.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 81 +++++++++++++++++++---
 1 file changed, 70 insertions(+), 11 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 5bd3f959..5b27bf90 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -9,6 +9,9 @@ import chisel3.testers.BasicTester
 
 class CompileOptionsSpec extends ChiselFlatSpec {
 
+  abstract class StrictModule extends Module()(chisel3.Strict.CompileOptions)
+  abstract class NotStrictModule extends Module()(chisel3.NotStrict.CompileOptions)
+
   class SmallBundle extends Bundle {
     val f1 = UInt(width = 4)
     val f2 = UInt(width = 5)
@@ -19,7 +22,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type]
   }
 
-  "A Module with missing bundle fields when compiled with Strict.CompileOption " should "throw an exception" in {
+  "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
       import chisel3.Strict.CompileOptions
 
@@ -34,7 +37,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
   }
 
-  "A Module with missing bundle fields when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class ConnectFieldMismatchModule extends Module {
@@ -47,7 +50,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     elaborate { new ConnectFieldMismatchModule() }
   }
 
-  "A Module in which a Reg is created with a bound type when compiled with Strict.CompileOption " should "throw an exception" in {
+  "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
       import chisel3.Strict.CompileOptions
 
@@ -62,7 +65,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
   }
 
-  "A Module in which a Reg is created with a bound type when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class CreateRegFromBoundTypeModule extends Module {
@@ -75,8 +78,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     elaborate { new CreateRegFromBoundTypeModule() }
   }
 
-
-  "A Module with wrapped IO when compiled with Strict.CompileOption " should "not throw an exception" in {
+  "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in {
     import chisel3.Strict.CompileOptions
 
     class RequireIOWrapModule extends Module {
@@ -89,7 +91,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     elaborate { new RequireIOWrapModule() }
 }
 
-  "A Module with unwrapped IO when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class RequireIOWrapModule extends Module {
@@ -102,7 +104,24 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       elaborate { new RequireIOWrapModule() }
   }
 
-  "A Module connecting output as source to input as sink when compiled with Strict.CompileOption " should "throw an exception" in {
+  "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in {
+    a [BindingException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class RequireIOWrapModule extends Module {
+        val io = new Bundle {
+          val in = UInt(width = 32).asInput
+          val out = Bool().asOutput
+        }
+        io.out := io.in(1)
+      }
+      elaborate {
+        new RequireIOWrapModule()
+      }
+    }
+  }
+
+  "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
       import chisel3.Strict.CompileOptions
 
@@ -120,7 +139,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
   }
 
-  "A Module connecting output as source to input as sink when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class SimpleModule extends Module {
@@ -136,7 +155,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     elaborate { new SwappedConnectionModule() }
   }
 
-  "A Module with directionless connections when compiled with Strict.CompileOption " should "throw an exception" in {
+  "A Module with directionless connections when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
       import chisel3.Strict.CompileOptions
 
@@ -158,7 +177,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
   }
 
-  "A Module with directionless connections when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class SimpleModule extends Module {
@@ -177,4 +196,44 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
     elaborate { new DirectionLessConnectionModule() }
   }
+
+  "A Module with wrapped IO when compiled with explicit Strict.CompileOption " should "not throw an exception" in {
+
+    class RequireIOWrapModule extends StrictModule {
+      val io = IO(new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      })
+      io.out := io.in(1)
+    }
+    elaborate { new RequireIOWrapModule() }
+  }
+
+  "A Module with unwrapped IO when compiled with explicit NotStrict.CompileOption " should "not throw an exception" in {
+
+    class RequireIOWrapModule extends NotStrictModule {
+      val io = new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      }
+      io.out := io.in(1)
+    }
+    elaborate { new RequireIOWrapModule() }
+  }
+
+  "A Module with unwrapped IO when compiled with explicit Strict.CompileOption " should "throw an exception" in {
+    a [BindingException] should be thrownBy {
+
+      class RequireIOWrapModule extends StrictModule {
+        val io = new Bundle {
+          val in = UInt(width = 32).asInput
+          val out = Bool().asOutput
+        }
+        io.out := io.in(1)
+      }
+      elaborate {
+        new RequireIOWrapModule()
+      }
+    }
+  }
 }
-- 
cgit v1.2.3


From 1379a192ca1f6c05aeba454b81e19fb8356e6cf3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 30 Aug 2016 10:17:18 -0700
Subject: Add example of specific CompileOptions settings to tests.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 5b27bf90..70843c3e 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -5,6 +5,7 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.core.Binding.BindingException
+import chisel3.internal.ExplicitCompileOptions
 import chisel3.testers.BasicTester
 
 class CompileOptionsSpec extends ChiselFlatSpec {
@@ -236,4 +237,29 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       }
     }
   }
+
+  "A Module with unwrapped IO when compiled with an explicit requireIOWrap false " should "not throw an exception" in {
+
+    object StrictNotIOWrap {
+
+      implicit object CompileOptions extends ExplicitCompileOptions {
+        val connectFieldsMustMatch = true
+        val declaredTypeMustBeUnbound = true
+        val requireIOWrap = false
+        val dontTryConnectionsSwapped = true
+        val dontAssumeDirectionality = true
+      }
+
+    }
+    class NotIOWrapModule extends Module()(StrictNotIOWrap.CompileOptions) {
+      val io = new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      }
+      io.out := io.in(1)
+    }
+    elaborate {
+      new NotIOWrapModule()
+    }
+  }
 }
-- 
cgit v1.2.3


From 8002f7ac6731b1da5e0d8e7b1536995a23878037 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 30 Aug 2016 13:45:37 -0700
Subject: Make compileOptions in the Chisel package effective. Remove
 references to the Chisel package in favor of explicit chisel3 imports in
 tests,

---
 src/test/scala/chiselTests/BetterNamingTests.scala | 3 ++-
 src/test/scala/chiselTests/IOCompatibility.scala   | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
index a480da98..98ca0306 100644
--- a/src/test/scala/chiselTests/BetterNamingTests.scala
+++ b/src/test/scala/chiselTests/BetterNamingTests.scala
@@ -3,7 +3,8 @@ package chiselTests
 import org.scalatest.{FlatSpec, Matchers}
 import collection.mutable
 
-import Chisel._
+import chisel3._
+import chisel3.util._
 import chisel3.NotStrict.CompileOptions
 
 
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index aa3bd962..d100df2b 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -2,7 +2,7 @@
 
 package chiselTests
 
-import Chisel._
+import chisel3._
 import chisel3.NotStrict.CompileOptions
 
 class IOCSimpleIO extends Bundle {
-- 
cgit v1.2.3


From 4b88a5dd45337fa88178fe17324eef3661daf1b3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 1 Sep 2016 10:21:57 -0700
Subject: Move connection implicits from Module constructor to connection
 methods. Eliminate builder compileOptions.

---
 src/test/scala/chiselTests/BlackBox.scala          |  1 +
 .../scala/chiselTests/CompileOptionsTest.scala     | 25 ++++++++++++++++------
 src/test/scala/chiselTests/Counter.scala           |  1 +
 src/test/scala/chiselTests/MultiAssign.scala       |  1 +
 src/test/scala/chiselTests/Reg.scala               |  1 +
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  1 +
 src/test/scala/chiselTests/Vec.scala               |  1 +
 src/test/scala/chiselTests/When.scala              |  1 +
 8 files changed, 26 insertions(+), 6 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index c1154883..b26b7d77 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -8,6 +8,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.Strict.CompileOptions
 
 class BlackBoxInverter extends BlackBox {
   val io = IO(new Bundle() {
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 70843c3e..f835ab0d 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -13,6 +13,16 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   abstract class StrictModule extends Module()(chisel3.Strict.CompileOptions)
   abstract class NotStrictModule extends Module()(chisel3.NotStrict.CompileOptions)
 
+  // Generate a set of options that do not have requireIOWrap enabled, in order to
+  // ensure its definition comes from the implicit options passed to the Module constructor.
+  object StrictWithoutIOWrap extends ExplicitCompileOptions {
+    val connectFieldsMustMatch = true
+    val declaredTypeMustBeUnbound = true
+    val requireIOWrap = false
+    val dontTryConnectionsSwapped = true
+    val dontAssumeDirectionality = true
+  }
+
   class SmallBundle extends Bundle {
     val f1 = UInt(width = 4)
     val f2 = UInt(width = 5)
@@ -199,7 +209,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with wrapped IO when compiled with explicit Strict.CompileOption " should "not throw an exception" in {
-
+    implicit val strictWithoutIOWrap = StrictWithoutIOWrap
     class RequireIOWrapModule extends StrictModule {
       val io = IO(new Bundle {
         val in = UInt(width = 32).asInput
@@ -207,11 +217,13 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       })
       io.out := io.in(1)
     }
-    elaborate { new RequireIOWrapModule() }
+    elaborate {
+      new RequireIOWrapModule()
+    }
   }
 
   "A Module with unwrapped IO when compiled with explicit NotStrict.CompileOption " should "not throw an exception" in {
-
+    implicit val strictWithoutIOWrap = StrictWithoutIOWrap
     class RequireIOWrapModule extends NotStrictModule {
       val io = new Bundle {
         val in = UInt(width = 32).asInput
@@ -219,12 +231,14 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       }
       io.out := io.in(1)
     }
-    elaborate { new RequireIOWrapModule() }
+    elaborate {
+      new RequireIOWrapModule()
+    }
   }
 
   "A Module with unwrapped IO when compiled with explicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-
+      implicit val strictWithoutIOWrap = StrictWithoutIOWrap
       class RequireIOWrapModule extends StrictModule {
         val io = new Bundle {
           val in = UInt(width = 32).asInput
@@ -256,7 +270,6 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         val in = UInt(width = 32).asInput
         val out = Bool().asOutput
       }
-      io.out := io.in(1)
     }
     elaborate {
       new NotIOWrapModule()
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 69d8a44a..46ab6dfc 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -8,6 +8,7 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.Strict.CompileOptions
 
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index fa4c4898..8fc1d0cb 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -7,6 +7,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.Strict.CompileOptions
 
 class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index a9086223..741393b0 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -6,6 +6,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.core.DataMirror
 import chisel3.testers.BasicTester
+import chisel3.Strict.CompileOptions
 
 class RegSpec extends ChiselFlatSpec {
   "A Reg" should "throw an exception if not given any parameters" in {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 23eed15f..6dc075d7 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -5,6 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.Strict.CompileOptions
 
 /** Extend BasicTester with a simple circuit and finish method.  TesterDriver will call the
   * finish method after the FinishTester's constructor has completed, which will alter the
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index e8bd66bd..abe483a4 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -8,6 +8,7 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.Strict.CompileOptions
 
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 07ab3444..1920b30e 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -7,6 +7,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+import chisel3.Strict.CompileOptions
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)
-- 
cgit v1.2.3


From 8e2615fd3852c7ffa5ee1884cca0f77062f3cc21 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 6 Sep 2016 08:46:16 -0700
Subject: Verify we can suppress the inclusion of default compileOptions.

---
 src/test/scala/chiselTests/CompileOptionsTest.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index f835ab0d..de75d07b 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -168,6 +168,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with directionless connections when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
+      // Verify we can suppress the inclusion of default compileOptions
+      import Chisel.{defaultCompileOptions => _, _}
       import chisel3.Strict.CompileOptions
 
       class SimpleModule extends Module {
-- 
cgit v1.2.3


From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 11:44:09 -0700
Subject: Massive rename of CompileOptions. Massage CompileOption names in an
 attempt to preserve default (Strict) CompileOptions in the absence of
 explicit imports. NOTE: Since the default is now strict, we may encounter
 errors when we generate connections for clients (i.e., in Vec.do_apply() when
 we wire up a sequence). We should really thread the CompileOptions through
 the macro system so the client's implicits are used.

---
 src/test/scala/chiselTests/AnnotatingExample.scala |  1 -
 src/test/scala/chiselTests/Assert.scala            |  1 -
 src/test/scala/chiselTests/BetterNamingTests.scala |  2 --
 src/test/scala/chiselTests/BlackBox.scala          |  2 +-
 src/test/scala/chiselTests/BundleWire.scala        |  2 +-
 .../scala/chiselTests/CompileOptionsTest.scala     | 32 +++++++++++-----------
 src/test/scala/chiselTests/ComplexAssign.scala     |  1 -
 src/test/scala/chiselTests/Counter.scala           |  1 -
 src/test/scala/chiselTests/Decoder.scala           |  1 -
 src/test/scala/chiselTests/DeqIOSpec.scala         |  1 -
 src/test/scala/chiselTests/Direction.scala         |  1 -
 .../scala/chiselTests/EnableShiftRegister.scala    |  1 -
 src/test/scala/chiselTests/GCD.scala               |  1 -
 src/test/scala/chiselTests/IOCompatibility.scala   | 17 ++++++------
 src/test/scala/chiselTests/LFSR16.scala            |  1 -
 src/test/scala/chiselTests/MemorySearch.scala      |  1 -
 src/test/scala/chiselTests/Module.scala            |  1 -
 src/test/scala/chiselTests/MulLookup.scala         |  1 -
 src/test/scala/chiselTests/MultiAssign.scala       |  1 -
 src/test/scala/chiselTests/OptionBundle.scala      |  1 -
 src/test/scala/chiselTests/Padding.scala           |  1 -
 .../scala/chiselTests/ParameterizedModule.scala    |  1 -
 src/test/scala/chiselTests/PrintableSpec.scala     |  1 -
 src/test/scala/chiselTests/Reg.scala               |  1 -
 src/test/scala/chiselTests/Risc.scala              |  1 -
 src/test/scala/chiselTests/SIntOps.scala           |  2 +-
 src/test/scala/chiselTests/Stack.scala             |  2 +-
 src/test/scala/chiselTests/Tbl.scala               |  2 +-
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  2 +-
 src/test/scala/chiselTests/UIntOps.scala           |  2 +-
 src/test/scala/chiselTests/Vec.scala               |  2 +-
 src/test/scala/chiselTests/VectorPacketIO.scala    |  2 +-
 src/test/scala/chiselTests/VendingMachine.scala    |  2 +-
 src/test/scala/chiselTests/When.scala              |  2 +-
 34 files changed, 35 insertions(+), 58 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/AnnotatingExample.scala b/src/test/scala/chiselTests/AnnotatingExample.scala
index 85b4b039..c84edf86 100644
--- a/src/test/scala/chiselTests/AnnotatingExample.scala
+++ b/src/test/scala/chiselTests/AnnotatingExample.scala
@@ -6,7 +6,6 @@ import chisel3._
 import chisel3.core.Module
 import chisel3.internal.InstanceId
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.CompileOptions
 import org.scalatest._
 
 import scala.util.DynamicVariable
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 509dedbd..efc2e1e7 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -6,7 +6,6 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
 
 class FailingAssertTester() extends BasicTester {
   assert(Bool(false))
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
index 98ca0306..f5872adb 100644
--- a/src/test/scala/chiselTests/BetterNamingTests.scala
+++ b/src/test/scala/chiselTests/BetterNamingTests.scala
@@ -5,8 +5,6 @@ import collection.mutable
 
 import chisel3._
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
-
 
 // Defined outside of the class so we don't get $ in name
 class Other(w: Int) extends Module {
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index b26b7d77..465dec4e 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -8,7 +8,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.Strict.CompileOptions
+//import chisel3.ExplicitCompileOptions.Strict
 
 class BlackBoxInverter extends BlackBox {
   val io = IO(new Bundle() {
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 15c5d5f8..07360c34 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -5,7 +5,7 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
-import chisel3.Strict.CompileOptions
+//import chisel3.ExplicitCompileOptions.Strict
 
 class Coord extends Bundle {
   val x = UInt.width( 32)
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index de75d07b..508c0849 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -5,17 +5,17 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.core.Binding.BindingException
-import chisel3.internal.ExplicitCompileOptions
+import chisel3.ExplicitImplicitCompileOptions
 import chisel3.testers.BasicTester
 
 class CompileOptionsSpec extends ChiselFlatSpec {
 
-  abstract class StrictModule extends Module()(chisel3.Strict.CompileOptions)
-  abstract class NotStrictModule extends Module()(chisel3.NotStrict.CompileOptions)
+  abstract class StrictModule extends Module()(chisel3.ExplicitCompileOptions.Strict)
+  abstract class NotStrictModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict)
 
   // Generate a set of options that do not have requireIOWrap enabled, in order to
   // ensure its definition comes from the implicit options passed to the Module constructor.
-  object StrictWithoutIOWrap extends ExplicitCompileOptions {
+  object StrictWithoutIOWrap extends ExplicitImplicitCompileOptions {
     val connectFieldsMustMatch = true
     val declaredTypeMustBeUnbound = true
     val requireIOWrap = false
@@ -35,7 +35,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class ConnectFieldMismatchModule extends Module {
         val io = IO(new Bundle {
@@ -49,7 +49,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class ConnectFieldMismatchModule extends Module {
       val io = IO(new Bundle {
@@ -63,7 +63,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class CreateRegFromBoundTypeModule extends Module {
         val io = IO(new Bundle {
@@ -77,7 +77,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class CreateRegFromBoundTypeModule extends Module {
       val io = IO(new Bundle {
@@ -90,7 +90,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in {
-    import chisel3.Strict.CompileOptions
+    import chisel3.ExplicitCompileOptions.Strict
 
     class RequireIOWrapModule extends Module {
       val io = IO(new Bundle {
@@ -103,7 +103,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 }
 
   "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class RequireIOWrapModule extends Module {
       val io = new Bundle {
@@ -117,7 +117,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class RequireIOWrapModule extends Module {
         val io = new Bundle {
@@ -134,7 +134,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -151,7 +151,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -170,7 +170,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     a [ChiselException] should be thrownBy {
       // Verify we can suppress the inclusion of default compileOptions
       import Chisel.{defaultCompileOptions => _, _}
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -191,7 +191,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -258,7 +258,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     object StrictNotIOWrap {
 
-      implicit object CompileOptions extends ExplicitCompileOptions {
+      implicit object CompileOptions extends ExplicitImplicitCompileOptions {
         val connectFieldsMustMatch = true
         val declaredTypeMustBeUnbound = true
         val requireIOWrap = false
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 48a673cf..0a1f31cc 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -8,7 +8,6 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 46ab6dfc..69d8a44a 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -8,7 +8,6 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.Strict.CompileOptions
 
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 35c83a8a..b50a80c0 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -9,7 +9,6 @@ import org.scalacheck._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 31508149..d41c50e5 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -5,7 +5,6 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
 
 /**
   * Created by chick on 2/8/16.
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 7cfe8268..949b92ed 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -6,7 +6,6 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.CompileOptions
 
 class DirectionHaver extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 15173e0f..5f3e0dd1 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -3,7 +3,6 @@
 package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.CompileOptions
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index 21082fc9..d683ce34 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -6,7 +6,6 @@ import chisel3._
 import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
-import chisel3.NotStrict.CompileOptions
 
 class GCD extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index d100df2b..7bf3dded 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -3,23 +3,22 @@
 package chiselTests
 
 import chisel3._
-import chisel3.NotStrict.CompileOptions
 
 class IOCSimpleIO extends Bundle {
-  val in  = UInt(INPUT,  32)
-  val out = UInt(OUTPUT, 32)
+  val in  = Input(UInt(width=32))
+  val out = Output(UInt(width=32))
 }
 
 class IOCPlusOne extends Module {
-  val io = new IOCSimpleIO
+  val io = IO(new IOCSimpleIO)
   io.out := io.in + UInt(1)
 }
 
 class IOCModuleVec(val n: Int) extends Module {
-  val io = new Bundle {
-    val ins  = Vec(n, UInt(INPUT,  32))
-    val outs = Vec(n, UInt(OUTPUT, 32))
-  }
+  val io = IO(new Bundle {
+    val ins  = Vec(n, Input(UInt(width=32)))
+    val outs = Vec(n, Output(UInt(width=32)))
+  })
   val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
   for (i <- 0 until n) {
     pluses(i).in := io.ins(i)
@@ -28,7 +27,7 @@ class IOCModuleVec(val n: Int) extends Module {
 }
 
 class IOCModuleWire extends Module {
-  val io = new IOCSimpleIO
+  val io = IO(new IOCSimpleIO)
   val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType)
   inc.in := io.in
   io.out := inc.out
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index 3b2b28f6..b13b67e3 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -5,7 +5,6 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
 
 class LFSR16 extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index a2a8eb8b..1d09f3c5 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -4,7 +4,6 @@ package chiselTests
 
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.CompileOptions
 
 class MemorySearch extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 1f0ab084..7a4050db 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.NotStrict.CompileOptions
 
 class SimpleIO extends Bundle {
   val in  = Input(UInt.width(32))
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 4548ae40..26ee4e03 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -6,7 +6,6 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.CompileOptions
 
 class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 8fc1d0cb..fa4c4898 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -7,7 +7,6 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.Strict.CompileOptions
 
 class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index d2165f62..8e4c7579 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -5,7 +5,6 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.CompileOptions
 
 class OptionBundle(hasIn: Boolean) extends Bundle {
   val in = if (hasIn) {
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index c7265c6c..42df6802 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.NotStrict.CompileOptions
 
 class Padder extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index b75d898b..14b21631 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -5,7 +5,6 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.CompileOptions
 
 class ParameterizedModule(invert: Boolean) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index afef3c54..12564a40 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -5,7 +5,6 @@ import scala.collection.mutable
 
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.Strict.CompileOptions
 
 /* Printable Tests */
 class PrintableSpec extends FlatSpec with Matchers {
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 741393b0..a9086223 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -6,7 +6,6 @@ import org.scalatest._
 import chisel3._
 import chisel3.core.DataMirror
 import chisel3.testers.BasicTester
-import chisel3.Strict.CompileOptions
 
 class RegSpec extends ChiselFlatSpec {
   "A Reg" should "throw an exception if not given any parameters" in {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index e27cbdca..6d5a0a76 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -4,7 +4,6 @@ package chiselTests
 
 import chisel3._
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
 
 class Risc extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index d070295c..418318fb 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
 
 class SIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index f1210260..937f1978 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -6,7 +6,7 @@ import scala.collection.mutable.Stack
 
 import chisel3._
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
 
 class ChiselStack(val depth: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index df8ce02c..5ff1aa31 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -8,7 +8,7 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 6dc075d7..a5351763 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.Strict.CompileOptions
+//import chisel3.ExplicitCompileOptions.Strict
 
 /** Extend BasicTester with a simple circuit and finish method.  TesterDriver will call the
   * finish method after the FinishTester's constructor has completed, which will alter the
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 237cea16..d80d6f17 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import org.scalatest._
 import chisel3.testers.BasicTester
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
 
 class UIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index abe483a4..a7dd975f 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -8,7 +8,7 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.Strict.CompileOptions
+//import chisel3.ExplicitCompileOptions.Strict
 
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 588e1ce2..221fd6d8 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
 
 /**
   * This test used to fail when assignment statements were
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 2a0ac824..5f65659b 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util._
-import chisel3.NotStrict.CompileOptions
+//import chisel3.ExplicitCompileOptions.NotStrict
 
 class VendingMachine extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 1920b30e..0183c29b 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -7,7 +7,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-import chisel3.Strict.CompileOptions
+//import chisel3.ExplicitCompileOptions.Strict
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)
-- 
cgit v1.2.3


From 96fb6a5e2c781b20470d02eac186b1b129c20bdf Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 14:57:42 -0700
Subject: Consolidate CompileOptions and re-enable NotStrict pending macro
 work.

---
 src/test/scala/chiselTests/BlackBox.scala          |  2 +-
 src/test/scala/chiselTests/BundleWire.scala        |  2 +-
 .../scala/chiselTests/CompileOptionsTest.scala     | 33 +++++++++++-----------
 src/test/scala/chiselTests/SIntOps.scala           |  1 -
 src/test/scala/chiselTests/Stack.scala             |  1 -
 src/test/scala/chiselTests/Tbl.scala               |  1 -
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  2 +-
 src/test/scala/chiselTests/UIntOps.scala           |  1 -
 src/test/scala/chiselTests/Vec.scala               |  2 +-
 src/test/scala/chiselTests/VectorPacketIO.scala    |  1 -
 src/test/scala/chiselTests/VendingMachine.scala    |  1 -
 src/test/scala/chiselTests/When.scala              |  2 +-
 12 files changed, 22 insertions(+), 27 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 465dec4e..344754e1 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -8,7 +8,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-//import chisel3.ExplicitCompileOptions.Strict
+//import chisel3.core.ExplicitCompileOptions.Strict
 
 class BlackBoxInverter extends BlackBox {
   val io = IO(new Bundle() {
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 07360c34..53d46e93 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -5,7 +5,7 @@ import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
-//import chisel3.ExplicitCompileOptions.Strict
+//import chisel3.core.ExplicitCompileOptions.Strict
 
 class Coord extends Bundle {
   val x = UInt.width( 32)
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 508c0849..83077544 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -5,17 +5,18 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.core.Binding.BindingException
-import chisel3.ExplicitImplicitCompileOptions
+import chisel3.core.ExplicitCompileOptions
 import chisel3.testers.BasicTester
+import chisel3.core.CompileOptions
 
 class CompileOptionsSpec extends ChiselFlatSpec {
 
-  abstract class StrictModule extends Module()(chisel3.ExplicitCompileOptions.Strict)
-  abstract class NotStrictModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict)
+  abstract class StrictModule extends Module()(chisel3.core.ExplicitCompileOptions.Strict)
+  abstract class NotStrictModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict)
 
   // Generate a set of options that do not have requireIOWrap enabled, in order to
   // ensure its definition comes from the implicit options passed to the Module constructor.
-  object StrictWithoutIOWrap extends ExplicitImplicitCompileOptions {
+  object StrictWithoutIOWrap extends CompileOptions {
     val connectFieldsMustMatch = true
     val declaredTypeMustBeUnbound = true
     val requireIOWrap = false
@@ -35,7 +36,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class ConnectFieldMismatchModule extends Module {
         val io = IO(new Bundle {
@@ -49,7 +50,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class ConnectFieldMismatchModule extends Module {
       val io = IO(new Bundle {
@@ -63,7 +64,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class CreateRegFromBoundTypeModule extends Module {
         val io = IO(new Bundle {
@@ -77,7 +78,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class CreateRegFromBoundTypeModule extends Module {
       val io = IO(new Bundle {
@@ -90,7 +91,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.Strict
+    import chisel3.core.ExplicitCompileOptions.Strict
 
     class RequireIOWrapModule extends Module {
       val io = IO(new Bundle {
@@ -103,7 +104,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 }
 
   "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class RequireIOWrapModule extends Module {
       val io = new Bundle {
@@ -117,7 +118,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class RequireIOWrapModule extends Module {
         val io = new Bundle {
@@ -134,7 +135,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -151,7 +152,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -170,7 +171,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     a [ChiselException] should be thrownBy {
       // Verify we can suppress the inclusion of default compileOptions
       import Chisel.{defaultCompileOptions => _, _}
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -191,7 +192,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -258,7 +259,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     object StrictNotIOWrap {
 
-      implicit object CompileOptions extends ExplicitImplicitCompileOptions {
+      implicit object CompileOptions extends CompileOptions {
         val connectFieldsMustMatch = true
         val declaredTypeMustBeUnbound = true
         val requireIOWrap = false
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 418318fb..392c4803 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -4,7 +4,6 @@ package chiselTests
 
 import chisel3._
 import chisel3.testers.BasicTester
-//import chisel3.ExplicitCompileOptions.NotStrict
 
 class SIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 937f1978..a72af928 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -6,7 +6,6 @@ import scala.collection.mutable.Stack
 
 import chisel3._
 import chisel3.util._
-//import chisel3.ExplicitCompileOptions.NotStrict
 
 class ChiselStack(val depth: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 5ff1aa31..66a06435 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -8,7 +8,6 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-//import chisel3.ExplicitCompileOptions.NotStrict
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index a5351763..b2e811d9 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-//import chisel3.ExplicitCompileOptions.Strict
+//import chisel3.core.ExplicitCompileOptions.Strict
 
 /** Extend BasicTester with a simple circuit and finish method.  TesterDriver will call the
   * finish method after the FinishTester's constructor has completed, which will alter the
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index d80d6f17..ad5aecd8 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -5,7 +5,6 @@ package chiselTests
 import chisel3._
 import org.scalatest._
 import chisel3.testers.BasicTester
-//import chisel3.ExplicitCompileOptions.NotStrict
 
 class UIntOps extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index a7dd975f..c5447610 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -8,7 +8,7 @@ import org.scalatest.prop._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-//import chisel3.ExplicitCompileOptions.Strict
+//import chisel3.core.ExplicitCompileOptions.Strict
 
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 221fd6d8..b8e3a154 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -5,7 +5,6 @@ package chiselTests
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-//import chisel3.ExplicitCompileOptions.NotStrict
 
 /**
   * This test used to fail when assignment statements were
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 5f65659b..00b1e7de 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -4,7 +4,6 @@ package chiselTests
 
 import chisel3._
 import chisel3.util._
-//import chisel3.ExplicitCompileOptions.NotStrict
 
 class VendingMachine extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 0183c29b..6dc2dbac 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -7,7 +7,7 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
-//import chisel3.ExplicitCompileOptions.Strict
+//import chisel3.core.ExplicitCompileOptions.Strict
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)
-- 
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