From d7697eb14a0195cc3726bf45fdf38c631b6f6507 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Fri, 20 May 2016 13:38:18 -0700
Subject: Update BackendCompilationUtilities.verilogToCpp to specify top-module

This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.
---
 src/test/scala/chiselTests/Harness.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index b06f4572..bc838766 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -55,7 +55,7 @@ int main(int argc, char **argv, char **env) {
     val cppHarness = makeCppHarness(fname)
 
     make(fname)
-    verilogToCpp(target, path, Seq(), cppHarness).!
+    verilogToCpp(target, target, path, Seq(), cppHarness).!
     cppToExe(target, path).!
     (path, target)
   }
-- 
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