From a6798adbf7567cf105f8190ebd293a4cfb3aeb11 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 13 Mar 2017 11:39:21 -1000
Subject: Revert "Change Vec creation to check if gen is lit (and hence needs
 t… (#530)

* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)"

This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2.
This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality.

* Add missing implicits to Vec.apply() signature.

* Use correct macro (CompileOptionsTransform) for indexWhere.
---
 src/test/scala/chiselTests/Vec.scala | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index c9320a96..d7c2c648 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -12,7 +12,7 @@ class LitTesterMod(vecSize: Int) extends Module {
   val io = IO(new Bundle {
     val out = Output(Vec(vecSize, UInt()))
   })
-  io.out := Vec(vecSize, 0.U)
+  io.out := Vec(Seq.fill(vecSize){0.U})
 }
 
 class RegTesterMod(vecSize: Int) extends Module {
@@ -20,7 +20,7 @@ class RegTesterMod(vecSize: Int) extends Module {
     val in = Input(Vec(vecSize, UInt()))
     val out = Output(Vec(vecSize, UInt()))
   })
-  val vecReg = RegNext(io.in, Vec(vecSize, 0.U))
+  val vecReg = RegNext(io.in, Vec(Seq.fill(vecSize){0.U}))
   io.out := vecReg
 }
 
@@ -32,6 +32,15 @@ class IOTesterMod(vecSize: Int) extends Module {
   io.out := io.in
 }
 
+class OneBitUnitRegVec extends Module {
+  val io = IO(new Bundle {
+    val out = Output(UInt(1.W))
+  })
+  val oneBitUnitRegVec = Reg(Vec(1, 1.U))
+  oneBitUnitRegVec(0) := 1.U(1.W)
+  io.out := oneBitUnitRegVec(0)
+}
+
 class LitTester(w: Int, values: List[Int]) extends BasicTester {
   val dut = Module(new LitTesterMod(values.length))
   for (a <- dut.io.out)
@@ -119,6 +128,12 @@ class HugeVecTester(n: Int) extends BasicTester {
   stop()
 }
 
+class OneBitUnitRegVecTester extends BasicTester {
+  val dut = Module(new OneBitUnitRegVec)
+  assert(dut.io.out === 1.U)
+  stop()
+}
+
 class VecSpec extends ChiselPropSpec {
   // Disable shrinking on error.
   implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
@@ -168,4 +183,8 @@ class VecSpec extends ChiselPropSpec {
   property("Infering widths on huge Vecs should not cause a stack overflow") {
     assertTesterPasses { new HugeVecTester(10000) }
   }
+
+  property("A Reg of a Vec of a single 1 bit element should compile and work") {
+    assertTesterPasses{ new OneBitUnitRegVecTester }
+  }
 }
-- 
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