From a06c411ce2ce6ddf8c20b38f90f4074af7b33b3f Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 6 Mar 2020 11:05:55 -0800
Subject: Provide API to set concrete type of implicit reset (#1361)

Introduces mutually-exclusive traits RequireAsyncReset and
RequireSyncReset to set the type of the implicit reset in
MultiIOModules. The Scala-type remains Reset, but the Chisel
elaboration-time checks apply.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/test/scala/chiselTests/ResetSpec.scala | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala
index 2a17d52f..d08be8fa 100644
--- a/src/test/scala/chiselTests/ResetSpec.scala
+++ b/src/test/scala/chiselTests/ResetSpec.scala
@@ -68,4 +68,28 @@ class ResetSpec extends ChiselFlatSpec {
     })
     async should include ("always @(posedge clk or posedge rst)")
   }
+
+  behavior of "Users"
+
+  they should "be able to force implicit reset to be synchronous" in {
+    val fir = generateFirrtl(new MultiIOModule with RequireSyncReset {
+      reset shouldBe a [Bool]
+    })
+    fir should include ("input reset : UInt<1>")
+  }
+
+  they should "be able to force implicit reset to be asynchronous" in {
+    val fir = generateFirrtl(new MultiIOModule with RequireAsyncReset {
+      reset shouldBe an [AsyncReset]
+    })
+    fir should include ("input reset : AsyncReset")
+  }
+
+  "Chisel" should "error if sync and async modules are nested" in {
+    a [ChiselException] shouldBe thrownBy {
+      elaborate(new MultiIOModule with RequireAsyncReset {
+        val mod = Module(new MultiIOModule with RequireSyncReset)
+      })
+    }
+  }
 }
-- 
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