From 3d67395ef286fb309bfb645dea2b574e77d08044 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Wed, 9 Jan 2019 18:20:14 -0500
Subject: Avoid procedural wire assignment in test resource

Verilator 4.008 dropped the hammer on procedural wire assignment to
align with the IEEE standard (first I've heard of this, though). The
VerilogVendingMachine.v test resource will error in Verilator 4.008
with a PROCASSWIRE error if you try to compile it. This fixes that
example to only assign to a register.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 src/test/resources/chisel3/VerilogVendingMachine.v | 47 ++++++++++++----------
 1 file changed, 25 insertions(+), 22 deletions(-)

(limited to 'src/test')

diff --git a/src/test/resources/chisel3/VerilogVendingMachine.v b/src/test/resources/chisel3/VerilogVendingMachine.v
index c01259bd..0902d1d2 100644
--- a/src/test/resources/chisel3/VerilogVendingMachine.v
+++ b/src/test/resources/chisel3/VerilogVendingMachine.v
@@ -10,35 +10,38 @@ module VerilogVendingMachine(
 );
   parameter sIdle = 3'd0, s5 = 3'd1, s10 = 3'd2, s15 = 3'd3, sOk = 3'd4;
   reg [2:0] state;
-  wire [2:0] next_state;
 
   assign dispense = (state == sOk) ? 1'd1 : 1'd0;
 
-  always @(*) begin
-    case (state)
-      sIdle: if (nickel) next_state <= s5;
-             else if (dime) next_state <= s10;
-             else next_state <= state;
-      s5: if (nickel) next_state <= s10;
-             else if (dime) next_state <= s15;
-             else next_state <= state;
-      s10: if (nickel) next_state <= s15;
-             else if (dime) next_state <= sOk;
-             else next_state <= state;
-      s15: if (nickel) next_state <= sOk;
-             else if (dime) next_state <= sOk;
-             else next_state <= state;
-      sOk: next_state <= sIdle;
-    endcase
-  end
-
-  // Go to next state
   always @(posedge clock) begin
     if (reset) begin
       state <= sIdle;
     end else begin
-      state <= next_state;
+      case (state)
+      sIdle: begin
+        if (nickel) state <= s5;
+        else if (dime) state <= s10;
+        else state <= state;
+      end
+      s5: begin
+        if (nickel) state <= s10;
+        else if (dime) state <= s15;
+        else state <= state;
+      end
+      s10: begin
+        if (nickel) state <= s15;
+        else if (dime) state <= sOk;
+        else state <= state;
+      end
+      s15: begin
+        if (nickel) state <= sOk;
+        else if (dime) state <= sOk;
+        else state <= state;
+      end
+      sOk: begin
+        state <= sIdle;
+      end
+      endcase
     end
   end
 endmodule
-
-- 
cgit v1.2.3


From 685790b2c6c7ff8ddfd34f2f84572a985d3416cc Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Fri, 11 Jan 2019 15:06:29 -0800
Subject: Add test for chiselNaming of Seq[Data]

---
 src/test/scala/chiselTests/NamingAnnotationTest.scala | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala
index 07962aaf..ec0874fc 100644
--- a/src/test/scala/chiselTests/NamingAnnotationTest.scala
+++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala
@@ -67,6 +67,11 @@ class NamedModule extends NamedModuleTester {
     val myA = expectName(1.U + myNested, "test_myA")
     val myB = expectName(myA +& 2.U, "test_myB")
     val myC = expectName(myB +& 3.U, "test_myC")
+
+    val myD = Seq(myC +& 1.U, myC +& 2.U)
+    for ((d, i) <- myD.zipWithIndex)
+      expectName(d, s"test_myD_$i")
+
     myC +& 4.U  // named at enclosing scope
   }
 
-- 
cgit v1.2.3