From 3ef63639284b2b56f415e1540c58d85d88c360db Mon Sep 17 00:00:00 2001
From: Jack
Date: Mon, 30 Jan 2017 22:42:57 -0800
Subject: Make Module and Bundle properly use empty namespaces

Fix default suggested name of Module instances (now based on desired name
rather than actual assigned name).
Remove parent/child relationship from Namespace.

Previously, Module and Bundle namespaces were "children" of the Module
definition namespace. This could lead to collisions that would give unexpected
names for module instances or Bundle elements. In particular, otherwise
identical modules that instantiate other identical modules in such a way that
the instance cannot be named via reflection would not be deduplicated because
the names of the instances would collide with the names of the modules in the
Builder.globalNamespace.
---
 src/test/scala/chiselTests/DedupSpec.scala | 57 ++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 src/test/scala/chiselTests/DedupSpec.scala

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/DedupSpec.scala b/src/test/scala/chiselTests/DedupSpec.scala
new file mode 100644
index 00000000..b8fe075e
--- /dev/null
+++ b/src/test/scala/chiselTests/DedupSpec.scala
@@ -0,0 +1,57 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import chisel3.util._
+
+class DedupIO extends Bundle {
+  val in = Flipped(Decoupled(UInt(32.W)))
+  val out = Decoupled(UInt(32.W))
+}
+
+class DedupQueues(n: Int) extends Module {
+  require(n > 0)
+  val io = IO(new DedupIO)
+  val queues = Seq.fill(n)(Module(new Queue(UInt(32.W), 4)))
+  var port = io.in
+  for (q <- queues) {
+    q.io.enq <> port
+    port = q.io.deq
+  }
+  io.out <> port
+}
+
+/* This module creates a Queue in a nested function (such that it is not named via reflection). The
+ * default naming for instances prior to #470 caused otherwise identical instantiations of this
+ * module to have different instance names for the queues which prevented deduplication.
+ * NestedDedup instantiates this module twice to ensure it is deduplicated properly.
+ */
+class DedupSubModule extends Module {
+  val io = IO(new DedupIO)
+  io.out <> Queue(io.in, 4)
+}
+
+class NestedDedup extends Module {
+  val io = IO(new DedupIO)
+  val inst0 = Module(new DedupSubModule)
+  val inst1 = Module(new DedupSubModule)
+  inst0.io.in <> io.in
+  inst1.io.in <> inst0.io.out
+  io.out <> inst1.io.out
+}
+
+class DedupSpec extends ChiselFlatSpec {
+  private val ModuleRegex = """\s*module\s+(\w+)\b.*""".r
+  def countModules(verilog: String): Int =
+    (verilog split "\n"  collect { case ModuleRegex(name) => name }).size
+
+  "Deduplication" should "occur" in {
+    assert(countModules(compile { new DedupQueues(4) }) === 2)
+  }
+
+  it should "properly dedup modules with deduped submodules" in {
+    assert(countModules(compile { new NestedDedup }) === 3)
+  }
+}
+
-- 
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