From 7bad3d2ec316f24f3da79d1dfef19e128cfe8bf5 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Fri, 12 Aug 2022 20:04:33 +0000
Subject: Add ability to suppress enum cast warnings (#2671) (#2674)

(cherry picked from commit 1ad820f7f549eddcd7188b737f59a240e48a7f0a)

Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>---
 src/test/scala/chiselTests/StrongEnum.scala | 41 +++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala
index 44ed77f9..5b1b13fd 100644
--- a/src/test/scala/chiselTests/StrongEnum.scala
+++ b/src/test/scala/chiselTests/StrongEnum.scala
@@ -5,6 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.experimental.ChiselEnum
 import chisel3.experimental.AffectsChiselPrefix
+import chisel3.experimental.suppressEnumCastWarning
 import chisel3.internal.firrtl.UnknownWidth
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
@@ -481,6 +482,46 @@ class StrongEnumSpec extends ChiselFlatSpec with Utils {
     (log should not).include("warn")
   }
 
+  it should "suppress warning using suppressEnumCastWarning" in {
+    object TestEnum extends ChiselEnum {
+      val e0, e1, e2 = Value
+    }
+
+    class MyModule extends Module {
+      val in = IO(Input(UInt(2.W)))
+      val out = IO(Output(TestEnum()))
+      suppressEnumCastWarning {
+        val res = TestEnum(in)
+        out := res
+      }
+    }
+    val (log, _) = grabLog(ChiselStage.elaborate(new MyModule))
+    (log should not).include("warn")
+  }
+
+  it should "suppress exactly one warning using suppressEnumCastWarning" in {
+    object TestEnum1 extends ChiselEnum {
+      val e0, e1, e2 = Value
+    }
+    object TestEnum2 extends ChiselEnum {
+      val e0, e1, e2 = Value
+    }
+
+    class MyModule extends Module {
+      val in = IO(Input(UInt(2.W)))
+      val out1 = IO(Output(TestEnum1()))
+      val out2 = IO(Output(TestEnum2()))
+      suppressEnumCastWarning {
+        out1 := TestEnum1(in)
+      }
+      out2 := TestEnum2(in)
+    }
+    val (log, _) = grabLog(ChiselStage.elaborate(new MyModule))
+    log should include("warn")
+    log should include("TestEnum2") // not suppressed
+    (log should not).include("TestEnum1") // suppressed
+  }
+
   "Casting a UInt to an Enum with .safe" should "NOT warn" in {
     object MyEnum extends ChiselEnum {
       val e0, e1, e2 = Value
-- 
cgit v1.2.3


From d344e8a91bdbfedc28527c3fc7d6d243dff9e3e6 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Fri, 12 Aug 2022 20:56:42 +0000
Subject: Show equivalent warnings/errors only once (#2673) (#2675)

(cherry picked from commit ae76ff4cb303a6646e48dc044be47051b67e7cbb)

Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>---
 src/test/scala/chiselTests/WarningSpec.scala | 35 ++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 src/test/scala/chiselTests/WarningSpec.scala

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/WarningSpec.scala b/src/test/scala/chiselTests/WarningSpec.scala
new file mode 100644
index 00000000..bf3830d6
--- /dev/null
+++ b/src/test/scala/chiselTests/WarningSpec.scala
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests
+
+import chisel3._
+import chisel3.util._
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.experimental.ChiselEnum
+import chisel3.experimental.EnumType
+import chiselTests.ChiselFlatSpec
+
+class WarningSpec extends ChiselFlatSpec with Utils {
+  behavior.of("Warnings")
+
+  "Warnings" should "be de-duplicated" in {
+    object MyEnum extends ChiselEnum {
+      val e0, e1, e2 = Value
+    }
+
+    class MyModule extends Module {
+      val in = IO(Input(UInt(2.W)))
+      val out1 = IO(Output(MyEnum()))
+      val out2 = IO(Output(MyEnum()))
+      def func(out: EnumType): Unit = {
+        out := MyEnum(in)
+      }
+      func(out1)
+      func(out2)
+    }
+    val (log, _) = grabLog(ChiselStage.elaborate(new MyModule))
+    def countSubstring(s: String, sub: String) =
+      s.sliding(sub.length).count(_ == sub)
+    countSubstring(log, "Casting non-literal UInt") should be(1)
+  }
+}
-- 
cgit v1.2.3


From c4dec947d54a52c3092bd7855180d42afaae3776 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Sat, 13 Aug 2022 00:17:56 +0000
Subject: Add option to treat warnings as errors (backport #2676) (#2677)

* Add option to treat warnings as errors (#2676)

Add --warnings-as-errors option

(cherry picked from commit 498946663726955c380a1e420f5d7b9630000aad)

# Conflicts:
#	core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala
#	core/src/main/scala/chisel3/internal/Builder.scala
#	src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
#	src/main/scala/chisel3/stage/ChiselOptions.scala
#	src/main/scala/chisel3/stage/package.scala
#	src/main/scala/chisel3/stage/phases/Elaborate.scala

* Resolve backport conflicts

Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/WarningSpec.scala | 37 +++++++++++++++++-----------
 1 file changed, 22 insertions(+), 15 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/WarningSpec.scala b/src/test/scala/chiselTests/WarningSpec.scala
index bf3830d6..1cef1ffc 100644
--- a/src/test/scala/chiselTests/WarningSpec.scala
+++ b/src/test/scala/chiselTests/WarningSpec.scala
@@ -4,32 +4,39 @@ package chiselTests
 
 import chisel3._
 import chisel3.util._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.stage.ChiselStage
 import chisel3.experimental.ChiselEnum
 import chisel3.experimental.EnumType
-import chiselTests.ChiselFlatSpec
 
 class WarningSpec extends ChiselFlatSpec with Utils {
   behavior.of("Warnings")
 
-  "Warnings" should "be de-duplicated" in {
-    object MyEnum extends ChiselEnum {
-      val e0, e1, e2 = Value
-    }
+  object MyEnum extends ChiselEnum {
+    val e0, e1, e2 = Value
+  }
 
-    class MyModule extends Module {
-      val in = IO(Input(UInt(2.W)))
-      val out1 = IO(Output(MyEnum()))
-      val out2 = IO(Output(MyEnum()))
-      def func(out: EnumType): Unit = {
-        out := MyEnum(in)
-      }
-      func(out1)
-      func(out2)
+  class MyModule extends Module {
+    val in = IO(Input(UInt(2.W)))
+    val out1 = IO(Output(MyEnum()))
+    val out2 = IO(Output(MyEnum()))
+    def func(out: EnumType): Unit = {
+      out := MyEnum(in)
     }
+    func(out1)
+    func(out2)
+  }
+
+  "Warnings" should "be de-duplicated" in {
     val (log, _) = grabLog(ChiselStage.elaborate(new MyModule))
     def countSubstring(s: String, sub: String) =
       s.sliding(sub.length).count(_ == sub)
     countSubstring(log, "Casting non-literal UInt") should be(1)
   }
+
+  "Warnings" should "be treated as errors with warningsAsErrors" in {
+    a[ChiselException] should be thrownBy extractCause[ChiselException] {
+      val args = Array("--warnings-as-errors")
+      (new ChiselStage).emitChirrtl(new MyModule, args)
+    }
+  }
 }
-- 
cgit v1.2.3


From 29702d7dd10a9eb7595a102bfffcee665bcf7394 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Mon, 15 Aug 2022 20:37:55 +0000
Subject: Printables for verification preconditions (backport #2663) (#2680)

* Printables for verification preconditions (#2663)

Add support for printable within assert and assume verification statements

Co-authored-by: Girish Pai <girish.pai@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 7df5653309b5e48e1732b335610d9a7e8449f903)

* Waive MiMa false positive

Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/Assert.scala | 41 +++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 1849ddf8..d7885a3b 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -61,6 +61,29 @@ class BadUnescapedPercentAssertTester extends BasicTester {
   stop()
 }
 
+class PrintableFormattedAssertTester extends BasicTester {
+  val foobar = Wire(UInt(32.W))
+  foobar := 123.U
+  assert(foobar === 123.U, cf"Error! Wire foobar =/= $foobar%x This is 100%% wrong.\n")
+  stop()
+}
+
+class PrintableBadUnescapedPercentAssertTester extends BasicTester {
+  assert(1.U === 1.U, p"I'm 110% sure this is an invalid message")
+  stop()
+}
+
+class PrintableAssumeTester extends Module {
+  val in = IO(Input(UInt(8.W)))
+  val out = IO(Output(UInt(8.W)))
+
+  val w = Wire(UInt(8.W))
+  w := 255.U
+  assume(w === 255.U, cf"Assumption failed, Wire w =/= $w%x")
+
+  out := in
+}
+
 class AssertSpec extends ChiselFlatSpec with Utils {
   "A failing assertion" should "fail the testbench" in {
     assert(!runTester { new FailingAssertTester })
@@ -77,6 +100,12 @@ class AssertSpec extends ChiselFlatSpec with Utils {
   they should "allow printf-style format strings with arguments" in {
     assertTesterPasses { new FormattedAssertTester }
   }
+  they should "allow printf-style format strings in Assumes" in {
+    val chirrtl = ChiselStage.emitChirrtl(new PrintableAssumeTester)
+    chirrtl should include(
+      """assume(w === 255.U, cf\"Assumption failed, Wire w =/= $w%%%%x\")\n", w)"""
+    )
+  }
   they should "not allow unescaped % in the message" in {
     a[java.util.UnknownFormatConversionException] should be thrownBy {
       extractCause[java.util.UnknownFormatConversionException] {
@@ -84,4 +113,16 @@ class AssertSpec extends ChiselFlatSpec with Utils {
       }
     }
   }
+
+  they should "allow printable format strings with arguments" in {
+    assertTesterPasses { new FormattedAssertTester }
+  }
+  they should "not allow unescaped % in the printable message" in {
+    a[java.util.UnknownFormatConversionException] should be thrownBy {
+      extractCause[java.util.UnknownFormatConversionException] {
+        ChiselStage.elaborate { new BadUnescapedPercentAssertTester }
+      }
+    }
+  }
+
 }
-- 
cgit v1.2.3


From 23ef9aa7ffef5bbf8fe124fc9be7683f005c3612 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Tue, 16 Aug 2022 19:04:28 +0000
Subject: Add OpaqueType support to Records (backport #2662) (#2679)

* Add OpaqueType support to Records (#2662)

OpaqueTypes are essentially type aliases that hide the underlying type.
They are implemented in Chisel as Records of a single, unnamed element
where the wrapping Record does not exist in the emitted FIRRTL.

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit df5afee2d41b5bcd82d4013b977965c0dfe046fd)

* Fix test compilation

* Fix OpaqueType tests in RecordSpec

Need to implement cloneType correctly and to warn instead of error when
accessing .toTarget of non-hardware types because that is a warning (not
error) in 3.5.

* Waive MiMa false positives

Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/RecordSpec.scala | 88 ++++++++++++++++++++++++++++-
 1 file changed, 87 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index 30b55812..5aa872b0 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -108,6 +108,58 @@ trait RecordSpecUtils {
     require(DataMirror.checkTypeEquivalence(wire0, wire1))
     require(!DataMirror.checkTypeEquivalence(wire1, wire2))
   }
+
+  class SingleElementRecord extends Record {
+    private val underlying = UInt(8.W)
+    val elements = SeqMap("" -> underlying)
+    override def opaqueType = elements.size == 1
+    override def cloneType: this.type = (new SingleElementRecord).asInstanceOf[this.type]
+
+    def +(that: SingleElementRecord): SingleElementRecord = {
+      val _w = Wire(new SingleElementRecord)
+      _w.underlying := this.underlying + that.underlying
+      _w
+    }
+  }
+
+  class SingleElementRecordModule extends Module {
+    val in1 = IO(Input(new SingleElementRecord))
+    val in2 = IO(Input(new SingleElementRecord))
+    val out = IO(Output(new SingleElementRecord))
+
+    val r = new SingleElementRecord
+
+    out := in1 + in2
+  }
+
+  class NamedSingleElementRecord extends Record {
+    private val underlying = UInt(8.W)
+    val elements = SeqMap("unused" -> underlying)
+
+    override def opaqueType = elements.size == 1
+    override def cloneType: this.type = (new NamedSingleElementRecord).asInstanceOf[this.type]
+  }
+
+  class NamedSingleElementModule extends Module {
+    val in = IO(Input(new NamedSingleElementRecord))
+    val out = IO(Output(new NamedSingleElementRecord))
+    out := in
+  }
+
+  class ErroneousOverride extends Record {
+    private val underlyingA = UInt(8.W)
+    private val underlyingB = UInt(8.W)
+    val elements = SeqMap("x" -> underlyingA, "y" -> underlyingB)
+
+    override def opaqueType = true
+    override def cloneType: this.type = (new ErroneousOverride).asInstanceOf[this.type]
+  }
+
+  class ErroneousOverrideModule extends Module {
+    val in = IO(Input(new ErroneousOverride))
+    val out = IO(Output(new ErroneousOverride))
+    out := in
+  }
 }
 
 class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
@@ -133,7 +185,7 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     class AliasedFieldRecord extends Record {
       val foo = UInt(8.W)
       val elements = SeqMap("foo" -> foo, "bar" -> foo)
-      override def cloneType: AliasedFieldRecord.this.type = this
+      override def cloneType: AliasedFieldRecord.this.type = (new AliasedFieldRecord).asInstanceOf[this.type]
     }
 
     val e = intercept[AliasedAggregateFieldException] {
@@ -146,6 +198,40 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     e.getMessage should include("contains aliased fields named (bar,foo)")
   }
 
+  they should "be OpaqueType for maps with single unnamed elements" in {
+    val singleElementChirrtl = ChiselStage.emitChirrtl { new SingleElementRecordModule }
+    singleElementChirrtl should include("input in1 : UInt<8>")
+    singleElementChirrtl should include("input in2 : UInt<8>")
+    singleElementChirrtl should include("add(in1, in2)")
+  }
+
+  they should "throw an error when map contains a named element and opaqueType is overriden to true" in {
+    (the[Exception] thrownBy extractCause[Exception] {
+      ChiselStage.elaborate { new NamedSingleElementModule }
+    }).getMessage should include("Opaque types must have exactly one element with an empty name")
+  }
+
+  they should "throw an error when map contains more than one element and opaqueType is overriden to true" in {
+    (the[Exception] thrownBy extractCause[Exception] {
+      ChiselStage.elaborate { new ErroneousOverrideModule }
+    }).getMessage should include("Opaque types must have exactly one element with an empty name")
+  }
+
+  they should "work with .toTarget" in {
+    var m: SingleElementRecordModule = null
+    ChiselStage.elaborate { m = new SingleElementRecordModule; m }
+    val q = m.in1.toTarget.toString
+    assert(q == "~SingleElementRecordModule|SingleElementRecordModule>in1")
+  }
+
+  they should "work (but warn) with .toTarget on non-data OpaqueType Record" in {
+    var m: SingleElementRecordModule = null
+    ChiselStage.elaborate { m = new SingleElementRecordModule; m }
+    val (log, q) = grabLog(m.r.toTarget)
+    log should include(".toTarget of non-hardware Data is deprecated.")
+    assert(q.toString == "~SingleElementRecordModule|SingleElementRecordModule>r")
+  }
+
   they should "follow UInt serialization/deserialization API" in {
     assertTesterPasses { new RecordSerializationTest }
   }
-- 
cgit v1.2.3


From 16dfc84d6667f1f6bbca46935cb445bc288c96d4 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Thu, 18 Aug 2022 00:30:39 +0000
Subject: Add generic `Data` equality (===) via extension method (#2669)
 (#2691)

(cherry picked from commit 67cff8253740f19642006dba7eff58b1e5fa1291)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>---
 src/test/scala/chiselTests/DataEqualitySpec.scala | 257 ++++++++++++++++++++++
 1 file changed, 257 insertions(+)
 create mode 100644 src/test/scala/chiselTests/DataEqualitySpec.scala

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/DataEqualitySpec.scala b/src/test/scala/chiselTests/DataEqualitySpec.scala
new file mode 100644
index 00000000..4ac3292d
--- /dev/null
+++ b/src/test/scala/chiselTests/DataEqualitySpec.scala
@@ -0,0 +1,257 @@
+package chiselTests
+
+import chisel3._
+import chisel3.experimental.VecLiterals._
+import chisel3.experimental.BundleLiterals._
+import chisel3.experimental.{Analog, ChiselEnum, ChiselRange, FixedPoint, Interval}
+import chisel3.stage.ChiselStage
+import chisel3.testers.BasicTester
+import chisel3.util.Valid
+
+class EqualityModule(lhsGen: => Data, rhsGen: => Data) extends Module {
+  val out = IO(Output(Bool()))
+
+  val lhs = lhsGen
+  val rhs = rhsGen
+
+  out := lhs === rhs
+}
+
+class EqualityTester(lhsGen: => Data, rhsGen: => Data) extends BasicTester {
+  val module = Module(new EqualityModule(lhsGen, rhsGen))
+
+  assert(module.out)
+
+  stop()
+}
+
+class AnalogBundle extends Bundle {
+  val analog = Analog(32.W)
+}
+
+class AnalogExceptionModule extends Module {
+  class AnalogExceptionModuleIO extends Bundle {
+    val bundle1 = new AnalogBundle
+    val bundle2 = new AnalogBundle
+  }
+
+  val io = IO(new AnalogExceptionModuleIO)
+}
+
+class AnalogExceptionTester extends BasicTester {
+  val module = Module(new AnalogExceptionModule)
+
+  module.io.bundle1 <> DontCare
+  module.io.bundle2 <> DontCare
+
+  assert(module.io.bundle1 === module.io.bundle2)
+
+  stop()
+}
+
+class DataEqualitySpec extends ChiselFlatSpec with Utils {
+  object MyEnum extends ChiselEnum {
+    val sA, sB = Value
+  }
+  object MyEnumB extends ChiselEnum {
+    val sA, sB = Value
+  }
+  class MyBundle extends Bundle {
+    val a = UInt(8.W)
+    val b = Bool()
+    val c = MyEnum()
+  }
+  class LongBundle extends Bundle {
+    val a = UInt(48.W)
+    val b = SInt(32.W)
+    val c = FixedPoint(16.W, 4.BP)
+  }
+  class RuntimeSensitiveBundle(gen: => Bundle) extends Bundle {
+    val a = UInt(8.W)
+    val b: Bundle = gen
+  }
+
+  behavior.of("UInt === UInt")
+  it should "pass with equal values" in {
+    assertTesterPasses {
+      new EqualityTester(0.U, 0.U)
+    }
+  }
+  it should "fail with differing values" in {
+    assertTesterFails {
+      new EqualityTester(0.U, 1.U)
+    }
+  }
+
+  behavior.of("SInt === SInt")
+  it should "pass with equal values" in {
+    assertTesterPasses {
+      new EqualityTester(0.S, 0.S)
+    }
+  }
+  it should "fail with differing values" in {
+    assertTesterFails {
+      new EqualityTester(0.S, 1.S)
+    }
+  }
+
+  behavior.of("Reset === Reset")
+  it should "pass with equal values" in {
+    assertTesterPasses {
+      new EqualityTester(true.B, true.B)
+    }
+  }
+  it should "fail with differing values" in {
+    assertTesterFails {
+      new EqualityTester(true.B, false.B)
+    }
+  }
+
+  behavior.of("AsyncReset === AsyncReset")
+  it should "pass with equal values" in {
+    assertTesterPasses {
+      new EqualityTester(true.B.asAsyncReset, true.B.asAsyncReset)
+    }
+  }
+  it should "fail with differing values" in {
+    assertTesterFails {
+      new EqualityTester(true.B.asAsyncReset, false.B.asAsyncReset)
+    }
+  }
+
+  behavior.of("Interval === Interval")
+  it should "pass with equal values" in {
+    assertTesterPasses {
+      new EqualityTester(2.I, 2.I)
+    }
+  }
+  it should "fail with differing values" in {
+    assertTesterFails {
+      new EqualityTester(2.I, 3.I)
+    }
+  }
+
+  behavior.of("FixedPoint === FixedPoint")
+  it should "pass with equal values" in {
+    assertTesterPasses {
+      new EqualityTester(4.5.F(16.W, 4.BP), 4.5.F(16.W, 4.BP))
+    }
+  }
+  it should "fail with differing values" in {
+    assertTesterFails {
+      new EqualityTester(4.5.F(16.W, 4.BP), 4.6.F(16.W, 4.BP))
+    }
+  }
+
+  behavior.of("ChiselEnum === ChiselEnum")
+  it should "pass with equal values" in {
+    assertTesterPasses {
+      new EqualityTester(MyEnum.sA, MyEnum.sA)
+    }
+  }
+  it should "fail with differing values" in {
+    assertTesterFails {
+      new EqualityTester(MyEnum.sA, MyEnum.sB)
+    }
+  }
+
+  behavior.of("Vec === Vec")
+  it should "pass with equal sizes, equal values" in {
+    assertTesterPasses {
+      new EqualityTester(
+        Vec(3, UInt(8.W)).Lit(0 -> 1.U, 1 -> 2.U, 2 -> 3.U),
+        Vec(3, UInt(8.W)).Lit(0 -> 1.U, 1 -> 2.U, 2 -> 3.U)
+      )
+    }
+  }
+  it should "fail with equal sizes, differing values" in {
+    assertTesterFails {
+      new EqualityTester(
+        Vec(3, UInt(8.W)).Lit(0 -> 1.U, 1 -> 2.U, 2 -> 3.U),
+        Vec(3, UInt(8.W)).Lit(0 -> 0.U, 1 -> 1.U, 2 -> 2.U)
+      )
+    }
+  }
+  it should "throw a ChiselException with differing sizes" in {
+    (the[ChiselException] thrownBy extractCause[ChiselException] {
+      assertTesterFails {
+        new EqualityTester(
+          Vec(3, UInt(8.W)).Lit(0 -> 1.U, 1 -> 2.U, 2 -> 3.U),
+          Vec(4, UInt(8.W)).Lit(0 -> 1.U, 1 -> 2.U, 2 -> 3.U, 3 -> 4.U)
+        )
+      }
+    }).getMessage should include("Vec sizes differ")
+  }
+
+  behavior.of("Bundle === Bundle")
+  it should "pass with equal type, equal values" in {
+    assertTesterPasses {
+      new EqualityTester(
+        (new MyBundle).Lit(_.a -> 42.U, _.b -> false.B, _.c -> MyEnum.sB),
+        (new MyBundle).Lit(_.a -> 42.U, _.b -> false.B, _.c -> MyEnum.sB)
+      )
+    }
+  }
+  it should "fail with equal type, differing values" in {
+    assertTesterFails {
+      new EqualityTester(
+        (new MyBundle).Lit(_.a -> 42.U, _.b -> false.B, _.c -> MyEnum.sB),
+        (new MyBundle).Lit(_.a -> 42.U, _.b -> false.B, _.c -> MyEnum.sA)
+      )
+    }
+  }
+  it should "throw a ChiselException with differing runtime types" in {
+    (the[ChiselException] thrownBy extractCause[ChiselException] {
+      assertTesterFails {
+        new EqualityTester(
+          (new RuntimeSensitiveBundle(new MyBundle)).Lit(
+            _.a -> 1.U,
+            _.b -> (new MyBundle).Lit(
+              _.a -> 42.U,
+              _.b -> false.B,
+              _.c -> MyEnum.sB
+            )
+          ),
+          (new RuntimeSensitiveBundle(new LongBundle)).Lit(
+            _.a -> 1.U,
+            _.b -> (new LongBundle).Lit(
+              _.a -> 42.U,
+              _.b -> 0.S,
+              _.c -> 4.5.F(16.W, 4.BP)
+            )
+          )
+        )
+      }
+    }).getMessage should include("Runtime types differ")
+  }
+
+  behavior.of("DontCare === DontCare")
+  it should "pass with two invalids" in {
+    assertTesterPasses {
+      new EqualityTester(Valid(UInt(8.W)).Lit(_.bits -> 123.U), Valid(UInt(8.W)).Lit(_.bits -> 123.U))
+    }
+  }
+  it should "exhibit the same behavior as comparing two invalidated wires" in {
+    // Also check that two invalidated wires are equal
+    assertTesterPasses {
+      new EqualityTester(WireInit(UInt(8.W), DontCare), WireInit(UInt(8.W), DontCare))
+    }
+
+    // Compare the verilog generated from both test cases and verify that they both are equal to true
+    val verilog1 = ChiselStage.emitVerilog(
+      new EqualityModule(Valid(UInt(8.W)).Lit(_.bits -> 123.U), Valid(UInt(8.W)).Lit(_.bits -> 123.U))
+    )
+    val verilog2 =
+      ChiselStage.emitVerilog(new EqualityModule(WireInit(UInt(8.W), DontCare), WireInit(UInt(8.W), DontCare)))
+
+    verilog1 should include("assign out = 1'h1;")
+    verilog2 should include("assign out = 1'h1;")
+  }
+
+  behavior.of("Analog === Analog")
+  it should "throw a ChiselException" in {
+    (the[ChiselException] thrownBy extractCause[ChiselException] {
+      assertTesterFails { new AnalogExceptionTester }
+    }).getMessage should include("Equality isn't defined for Analog values")
+  }
+}
-- 
cgit v1.2.3


From 1c5bd39a192272877cf4b8dc3d26a9284eb0c05d Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Tue, 23 Aug 2022 21:31:57 +0000
Subject: Add AffectsChiselPrefix tests to PrefixSpec (#2693) (#2695)

(cherry picked from commit 1a23b42429bf9de7dfab9f0a8e67334f8c5d4540)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>---
 src/test/scala/chiselTests/naming/PrefixSpec.scala | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index 6d52407e..b5eac1d4 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -7,6 +7,7 @@ import chisel3.stage.ChiselStage
 import chisel3.aop.Select
 import chisel3.experimental.{dump, noPrefix, prefix, treedump}
 import chiselTests.{ChiselPropSpec, Utils}
+import chisel3.experimental.AffectsChiselPrefix
 
 class PrefixSpec extends ChiselPropSpec with Utils {
   implicit val minimumMajorVersion: Int = 12
@@ -497,4 +498,27 @@ class PrefixSpec extends ChiselPropSpec with Utils {
       Select.wires(top).map(_.instanceName) should be(List("a_b_c_d"))
     }
   }
+
+  property("Prefixing of AffectsChiselPrefix objects should work") {
+    class NotAData extends AffectsChiselPrefix {
+      val value = Wire(UInt(3.W))
+    }
+    class NotADataUnprefixed {
+      val value = Wire(UInt(3.W))
+    }
+    class Test extends Module {
+      {
+        val nonData = new NotAData
+        // Instance name of nonData.value should be nonData_value
+        nonData.value := RegNext(3.U)
+
+        val nonData2 = new NotADataUnprefixed
+        // Instance name of nonData2.value should be value
+        nonData2.value := RegNext(3.U)
+      }
+    }
+    aspectTest(() => new Test) { top: Test =>
+      Select.wires(top).map(_.instanceName) should be(List("nonData_value", "value"))
+    }
+  }
 }
-- 
cgit v1.2.3


From c3b06d773f1fabd2519d6c705d68381d13f1c07f Mon Sep 17 00:00:00 2001
From: Zachary Yedidia
Date: Tue, 23 Aug 2022 17:20:12 -0700
Subject: Backport .toTarget deprecation warning information (3.5.x) (#2697)

---
 src/test/scala/chiselTests/RecordSpec.scala   |  2 +-
 src/test/scala/chiselTests/ToTargetSpec.scala | 17 +++++++++++++++++
 2 files changed, 18 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index 5aa872b0..718c1acb 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -228,7 +228,7 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     var m: SingleElementRecordModule = null
     ChiselStage.elaborate { m = new SingleElementRecordModule; m }
     val (log, q) = grabLog(m.r.toTarget)
-    log should include(".toTarget of non-hardware Data is deprecated.")
+    log should include(".toTarget of non-hardware Data is deprecated")
     assert(q.toString == "~SingleElementRecordModule|SingleElementRecordModule>r")
   }
 
diff --git a/src/test/scala/chiselTests/ToTargetSpec.scala b/src/test/scala/chiselTests/ToTargetSpec.scala
index dc4ec448..de46cdcb 100644
--- a/src/test/scala/chiselTests/ToTargetSpec.scala
+++ b/src/test/scala/chiselTests/ToTargetSpec.scala
@@ -49,4 +49,21 @@ class ToTargetSpec extends ChiselFlatSpec with Utils {
     val q = m.q.toTarget.toString
     assert(q == s"~$mn|Queue")
   }
+
+  it should "warn on non-hardware types and provide information" in {
+    class Example extends Module {
+      val tpe = UInt(8.W)
+
+      val in = IO(Input(tpe))
+      val out = IO(Output(tpe))
+      out := in
+    }
+
+    var e: Example = null
+    chisel3.stage.ChiselStage.elaborate { e = new Example; e }
+    val (log, foo) = grabLog(e.tpe.toTarget)
+    log should include(
+      "Accessing the .instanceName or .toTarget of non-hardware Data is deprecated: 'tpe', in module 'Example'"
+    )
+  }
 }
-- 
cgit v1.2.3


From 998913f9379440db26b6aeeaa09e7a11d7615351 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Thu, 25 Aug 2022 18:14:54 +0000
Subject: Bugfix - OpaqueSlot replace invalid localName (backport #2701)
 (#2702)

* Bugfix - OpaqueSlot replace invalid localName (#2701)

(cherry picked from commit fb8ea2a2fac227f2570da992d7877de2eb1cf801)

* Fix cloneTypes (#2703)

Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>---
 src/test/scala/chiselTests/RecordSpec.scala | 54 +++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index 718c1acb..5080f15f 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -132,6 +132,35 @@ trait RecordSpecUtils {
     out := in1 + in2
   }
 
+  class InnerRecord extends Record {
+    val k = new InnerInnerRecord
+    val elements = SeqMap("" -> k)
+    override def opaqueType = elements.size == 1
+    override def cloneType: this.type = (new InnerRecord).asInstanceOf[this.type]
+  }
+
+  class InnerInnerRecord extends Record {
+    val k = new SingleElementRecord
+    val elements = SeqMap("" -> k)
+    override def opaqueType = elements.size == 1
+    override def cloneType: this.type = (new InnerInnerRecord).asInstanceOf[this.type]
+  }
+
+  class NestedRecordModule extends Module {
+    val in = IO(Input(new InnerRecord))
+    val out = IO(Output(new InnerRecord))
+    val inst = Module(new InnerModule)
+    inst.foo := in
+    out := inst.bar
+  }
+  class InnerModule extends Module {
+    val foo = IO(Input(new InnerRecord))
+    val bar = IO(Output(new InnerRecord))
+
+    // DO NOT do this; just for testing element connections
+    bar.elements.head._2 := foo.elements.head._2
+  }
+
   class NamedSingleElementRecord extends Record {
     private val underlying = UInt(8.W)
     val elements = SeqMap("unused" -> underlying)
@@ -205,6 +234,31 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     singleElementChirrtl should include("add(in1, in2)")
   }
 
+  they should "work correctly for toTarget in nested opaque type Records" in {
+    var mod: NestedRecordModule = null
+    ChiselStage.elaborate { mod = new NestedRecordModule; mod }
+    val testStrings = Seq(
+      mod.in.toTarget.toString(),
+      mod.in.k.toTarget.toString(),
+      mod.in.k.k.toTarget.toString(),
+      mod.in.elements.head._2.toTarget.toString(),
+      mod.in.k.elements.head._2.toTarget.toString(),
+      mod.in.k.k.elements.head._2.toTarget.toString()
+    )
+    testStrings.foreach(x => assert(x == "~NestedRecordModule|NestedRecordModule>in"))
+  }
+
+  they should "work correctly when connecting nested opaque type elements" in {
+    val nestedRecordChirrtl = ChiselStage.emitChirrtl { new NestedRecordModule }
+    nestedRecordChirrtl should include("input in : UInt<8>")
+    nestedRecordChirrtl should include("output out : UInt<8>")
+    nestedRecordChirrtl should include("inst.foo <= in")
+    nestedRecordChirrtl should include("out <= inst.bar")
+    nestedRecordChirrtl should include("input foo : UInt<8>")
+    nestedRecordChirrtl should include("output bar : UInt<8>")
+    nestedRecordChirrtl should include("bar <= foo")
+  }
+
   they should "throw an error when map contains a named element and opaqueType is overriden to true" in {
     (the[Exception] thrownBy extractCause[Exception] {
       ChiselStage.elaborate { new NamedSingleElementModule }
-- 
cgit v1.2.3


From df5a95454ff0414d1d3ce16d06dbe27b152e3751 Mon Sep 17 00:00:00 2001
From: Zachary Yedidia
Date: Thu, 25 Aug 2022 12:04:37 -0700
Subject: Backport of eager error messages for annotations (3.5.x) (#2700)
 (#2705)

---
 .../scala/chiselTests/experimental/ForceNames.scala     | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/experimental/ForceNames.scala b/src/test/scala/chiselTests/experimental/ForceNames.scala
index 233b4a5f..9ba825c4 100644
--- a/src/test/scala/chiselTests/experimental/ForceNames.scala
+++ b/src/test/scala/chiselTests/experimental/ForceNames.scala
@@ -59,7 +59,7 @@ object ForceNamesHierarchy {
   }
 }
 
-class ForceNamesSpec extends ChiselFlatSpec {
+class ForceNamesSpec extends ChiselFlatSpec with Utils {
 
   def run[T <: RawModule](
     dut:        => T,
@@ -110,4 +110,19 @@ class ForceNamesSpec extends ChiselFlatSpec {
       )
     }
   }
+
+  "Force Name of non-hardware value" should "warn" in {
+    class Example extends Module {
+      val tpe = UInt(8.W)
+      forceName(tpe, "foobar")
+
+      val in = IO(Input(tpe))
+      val out = IO(Output(tpe))
+      out := in
+    }
+
+    val (log, foo) = grabLog(chisel3.stage.ChiselStage.elaborate(new Example))
+    log should include("deprecated")
+    log should include("Using forceName 'foobar' on non-hardware value UInt<8>")
+  }
 }
-- 
cgit v1.2.3


From 9f1484572e2e4185e87a9cfb03b253870636c12c Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Mon, 29 Aug 2022 21:05:56 +0000
Subject: Fix OpaqueSlot handling of contextual names (#2708) (#2712)

We need to ensure that contextual names stay contextual (ie. sensitive
to the module context which is important for naming ports).

(cherry picked from commit cee255216c4a1bb658a2d8ddc03d966ce7ffb877)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/RecordSpec.scala | 35 +++++++++++++++--------------
 1 file changed, 18 insertions(+), 17 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index 5080f15f..cde18da7 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -150,15 +150,17 @@ trait RecordSpecUtils {
     val in = IO(Input(new InnerRecord))
     val out = IO(Output(new InnerRecord))
     val inst = Module(new InnerModule)
-    inst.foo := in
-    out := inst.bar
+    inst.io.foo := in
+    out := inst.io.bar
   }
   class InnerModule extends Module {
-    val foo = IO(Input(new InnerRecord))
-    val bar = IO(Output(new InnerRecord))
+    val io = IO(new Bundle {
+      val foo = Input(new InnerRecord)
+      val bar = Output(new InnerRecord)
+    })
 
     // DO NOT do this; just for testing element connections
-    bar.elements.head._2 := foo.elements.head._2
+    io.bar.elements.head._2 := io.foo.elements.head._2
   }
 
   class NamedSingleElementRecord extends Record {
@@ -238,25 +240,24 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     var mod: NestedRecordModule = null
     ChiselStage.elaborate { mod = new NestedRecordModule; mod }
     val testStrings = Seq(
-      mod.in.toTarget.toString(),
-      mod.in.k.toTarget.toString(),
-      mod.in.k.k.toTarget.toString(),
-      mod.in.elements.head._2.toTarget.toString(),
-      mod.in.k.elements.head._2.toTarget.toString(),
-      mod.in.k.k.elements.head._2.toTarget.toString()
+      mod.inst.io.foo.toTarget.serialize,
+      mod.inst.io.foo.k.toTarget.serialize,
+      mod.inst.io.foo.k.k.toTarget.serialize,
+      mod.inst.io.foo.elements.head._2.toTarget.serialize,
+      mod.inst.io.foo.k.elements.head._2.toTarget.serialize,
+      mod.inst.io.foo.k.k.elements.head._2.toTarget.serialize
     )
-    testStrings.foreach(x => assert(x == "~NestedRecordModule|NestedRecordModule>in"))
+    testStrings.foreach(x => assert(x == "~NestedRecordModule|InnerModule>io.foo"))
   }
 
   they should "work correctly when connecting nested opaque type elements" in {
     val nestedRecordChirrtl = ChiselStage.emitChirrtl { new NestedRecordModule }
     nestedRecordChirrtl should include("input in : UInt<8>")
     nestedRecordChirrtl should include("output out : UInt<8>")
-    nestedRecordChirrtl should include("inst.foo <= in")
-    nestedRecordChirrtl should include("out <= inst.bar")
-    nestedRecordChirrtl should include("input foo : UInt<8>")
-    nestedRecordChirrtl should include("output bar : UInt<8>")
-    nestedRecordChirrtl should include("bar <= foo")
+    nestedRecordChirrtl should include("inst.io.foo <= in")
+    nestedRecordChirrtl should include("out <= inst.io.bar")
+    nestedRecordChirrtl should include("output io : { flip foo : UInt<8>, bar : UInt<8>}")
+    nestedRecordChirrtl should include("io.bar <= io.foo")
   }
 
   they should "throw an error when map contains a named element and opaqueType is overriden to true" in {
-- 
cgit v1.2.3


From bb3ef96d8911dbba4e22926ad4ce71eb8ab0d869 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Wed, 31 Aug 2022 01:41:09 +0000
Subject: Wires should have source location information in firrtl (#2714)
 (#2716)

- Remove line defeating having wire locators
  `implicit val noSourceInfo = UnlocatableSourceInfo` from `WireDefault#apply`
- Add test to show locators

(cherry picked from commit f701a9f8151891e3bf9019cd3229cb3f2cd1833b)

Co-authored-by: Chick Markley <chick.markley@sifive.com>---
 src/test/scala/chiselTests/WireSpec.scala | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/WireSpec.scala b/src/test/scala/chiselTests/WireSpec.scala
index 11a1f1a1..058a7f08 100644
--- a/src/test/scala/chiselTests/WireSpec.scala
+++ b/src/test/scala/chiselTests/WireSpec.scala
@@ -3,6 +3,7 @@
 package chiselTests
 
 import chisel3._
+import chisel3.stage.ChiselStage
 
 class WireSpec extends ChiselFlatSpec {
   "WireDefault.apply" should "work" in {
@@ -17,4 +18,19 @@ class WireSpec extends ChiselFlatSpec {
   it should "not allow init argument to affect type inference" in {
     assertDoesNotCompile("val x: UInt = WireDefault(UInt(4.W), 2.S)")
   }
+  it should "have source locator information on wires" in {
+    class Dummy extends chisel3.Module {
+      val in = IO(Input(Bool()))
+      val out = IO(Output(Bool()))
+
+      val wire = WireInit(Bool(), true.B)
+      val wire2 = Wire(Bool())
+      wire2 := in
+      out := in & wire & wire2
+    }
+
+    val chirrtl = ChiselStage.emitChirrtl(new Dummy)
+    chirrtl should include("wire wire : UInt<1> @[WireSpec.scala")
+    chirrtl should include("wire wire2 : UInt<1> @[WireSpec.scala")
+  }
 }
-- 
cgit v1.2.3


From 341dd51d76b8b068c59b184ceb952624d42abbfa Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Thu, 1 Sep 2022 23:55:26 +0000
Subject: Remove incorrect clock warning on Mem.read (backport #2721) (#2722)

* Remove incorrect clock warning on Mem.read (#2721)

Mem.read is combinational and thus unaffected by the clock, and so it
does not make sense to issue warnings about the current clock in this
context.

(cherry picked from commit 5fdf74f95e64cb69d6097547f20d789a83dbd735)

* Keep old version of MemBase.clockWarning for binary compatibility

This method is impossible for users to call, but it is easy enough to
keep around a version of it to make MiMa happy.

Co-authored-by: Andrew Waterman <andrew@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/MultiClockSpec.scala | 8 --------
 1 file changed, 8 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 381b4009..29ec6509 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -166,14 +166,6 @@ class MultiClockSpec extends ChiselFlatSpec with Utils {
   }
 
   "Differing clocks at memory and read accessor instantiation" should "warn" in {
-    class modMemReadDifferingClock extends Module {
-      val myClock = IO(Input(Clock()))
-      val mem = withClock(myClock) { Mem(4, UInt(8.W)) }
-      val readVal = mem.read(0.U)
-    }
-    val (logMemReadDifferingClock, _) = grabLog(ChiselStage.elaborate(new modMemReadDifferingClock))
-    logMemReadDifferingClock should include("memory is different")
-
     class modSyncReadMemReadDifferingClock extends Module {
       val myClock = IO(Input(Clock()))
       val mem = withClock(myClock) { SyncReadMem(4, UInt(8.W)) }
-- 
cgit v1.2.3


From f19556801137091fa79a6d79395985474527b72d Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Tue, 27 Sep 2022 19:36:39 +0000
Subject: Use Treadle (on pull requests only) to speed up CI (backport #2341)
 (#2748)

* Support using Treadle for 'sbt test'

Treadle will be used as the "defaultBackend" when the environment
variable CHISEL3_CI_USE_TREADLE is set. The intent is to set this
variable during CI for pre-merge CI (aka on pull requests).

(cherry picked from commit 7d39b7bd2b6f38dac90fe25064744ffc0ada0fe4)

* Use Treadle for CI on pull requests

(cherry picked from commit 82660673e56a816e68fcc068e3e04e127f076faf)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/ChiselSpec.scala | 5 ++++-
 src/test/scala/chiselTests/Vec.scala        | 4 ++--
 2 files changed, 6 insertions(+), 3 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 6f560b94..e00afcf6 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -38,7 +38,10 @@ trait ChiselRunners extends Assertions with BackendCompilationUtilities {
     annotations:          AnnotationSeq = Seq()
   ): Boolean = {
     // Change this to enable Treadle as a backend
-    val defaultBackend = chisel3.testers.TesterDriver.defaultBackend
+    val defaultBackend = {
+      val useTreadle = sys.env.get("CHISEL3_CI_USE_TREADLE").isDefined
+      if (useTreadle) chisel3.testers.TreadleBackend else chisel3.testers.TesterDriver.defaultBackend
+    }
     val hasBackend = TestUtils.containsBackend(annotations)
     val annos: Seq[Annotation] = if (hasBackend) annotations else defaultBackend +: annotations
     TesterDriver.execute(() => t, additionalVResources, annos)
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 02743187..4a871890 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -6,7 +6,7 @@ import org.scalacheck._
 
 import chisel3._
 import chisel3.stage.ChiselStage
-import chisel3.testers.BasicTester
+import chisel3.testers.{BasicTester, TesterDriver}
 import chisel3.util._
 import org.scalacheck.Shrink
 import scala.annotation.tailrec
@@ -456,7 +456,7 @@ class VecSpec extends ChiselPropSpec with Utils {
   }
 
   property("Infering widths on huge Vecs should not cause a stack overflow") {
-    assertTesterPasses { new HugeVecTester(10000) }
+    assertTesterPasses(new HugeVecTester(10000), annotations = TesterDriver.verilatorOnly)
   }
 
   property("A Reg of a Vec of a single 1 bit element should compile and work") {
-- 
cgit v1.2.3


From 5a79814631bdc8c71c5a7b4722cd43712f7ff445 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Thu, 29 Sep 2022 18:53:44 +0000
Subject: Add lexical scope checks to Assert, Assume and Printf (#2706) (#2753)

(cherry picked from commit f462c9f9307bebf3012da52432c3729cd752321c)

Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>---
 src/test/scala/chiselTests/Assert.scala | 77 +++++++++++++++++++++++++++++++++
 src/test/scala/chiselTests/Printf.scala | 39 +++++++++++++++++
 2 files changed, 116 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index d7885a3b..5e7b6496 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -84,6 +84,64 @@ class PrintableAssumeTester extends Module {
   out := in
 }
 
+class PrintableScopeTester extends Module {
+  val in = IO(Input(UInt(8.W)))
+  val out = IO(Output(UInt(8.W)))
+  out := in
+
+  val w = Wire(UInt(8.W))
+  w := 255.U
+
+  val printableWire = cf"$w"
+  val printablePort = cf"$in"
+}
+
+class AssertPrintableWireScope extends BasicTester {
+  val mod = Module(new PrintableScopeTester)
+  assert(1.U === 2.U, mod.printableWire)
+  stop()
+}
+
+class AssertPrintablePortScope extends BasicTester {
+  val mod = Module(new PrintableScopeTester)
+  mod.in := 255.U
+  assert(1.U === 1.U, mod.printablePort)
+  stop()
+}
+
+class AssertPrintableFailingWhenScope extends BasicTester {
+  val mod = Module(new PrintableWhenScopeTester)
+  assert(1.U === 1.U, mod.printable)
+  stop()
+}
+
+class AssumePrintableWireScope extends BasicTester {
+  val mod = Module(new PrintableScopeTester)
+  assume(1.U === 1.U, mod.printableWire)
+  stop()
+}
+
+class AssumePrintablePortScope extends BasicTester {
+  val mod = Module(new PrintableScopeTester)
+  mod.in := 255.U
+  assume(1.U === 1.U, mod.printablePort)
+  stop()
+}
+
+class PrintableWhenScopeTester extends Module {
+  val in = IO(Input(UInt(8.W)))
+  val out = IO(Output(UInt(8.W)))
+
+  out := in
+
+  val w = Wire(UInt(8.W))
+  w := 255.U
+  var printable = cf""
+  when(true.B) {
+    printable = cf"$w"
+  }
+}
+
 class AssertSpec extends ChiselFlatSpec with Utils {
   "A failing assertion" should "fail the testbench" in {
     assert(!runTester { new FailingAssertTester })
@@ -94,6 +152,25 @@ class AssertSpec extends ChiselFlatSpec with Utils {
   "An assertion" should "not assert until we come out of reset" in {
     assertTesterPasses { new PipelinedResetTester }
   }
+
+  "Assert Printables" should "respect port scoping" in {
+    assertTesterPasses { new AssertPrintablePortScope }
+  }
+  "Assert Printables" should "respect wire scoping" in {
+    a[ChiselException] should be thrownBy { ChiselStage.elaborate(new AssertPrintableWireScope) }
+  }
+  "Assume Printables" should "respect port scoping" in {
+    assertTesterPasses { new AssumePrintablePortScope }
+  }
+
+  "Assume Printables" should "respect wire scoping" in {
+    a[ChiselException] should be thrownBy { ChiselStage.elaborate(new AssumePrintableWireScope) }
+  }
+
+  "Assert Printables" should "respect when scope" in {
+    a[ChiselException] should be thrownBy { ChiselStage.elaborate(new AssertPrintableFailingWhenScope) }
+  }
+
   "Assertions" should "allow the modulo operator % in the message" in {
     assertTesterPasses { new ModuloAssertTester }
   }
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index 4171f97f..6c9f05f0 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.testers.BasicTester
+import chisel3.stage.ChiselStage
 
 class SinglePrintfTester() extends BasicTester {
   val x = 254.U
@@ -28,6 +29,38 @@ class ASCIIPrintableTester extends BasicTester {
   stop()
 }
 
+class ScopeTesterModule extends Module {
+  val in = IO(Input(UInt(8.W)))
+  val out = IO(Output(UInt(8.W)))
+  out := in
+
+  val w = Wire(UInt(8.W))
+  w := 125.U
+
+  val p = cf"$in"
+  val wp = cf"$w"
+}
+
+class PrintablePrintfScopeTester extends BasicTester {
+  ChiselStage.elaborate {
+    new Module {
+      val mod = Module(new ScopeTesterModule)
+      printf(mod.p)
+    }
+  }
+  stop()
+}
+
+class PrintablePrintfWireScopeTester extends BasicTester {
+  ChiselStage.elaborate {
+    new Module {
+      val mod = Module(new ScopeTesterModule)
+      printf(mod.wp)
+    }
+  }
+  stop()
+}
+
 class PrintfSpec extends ChiselFlatSpec {
   "A printf with a single argument" should "run" in {
     assertTesterPasses { new SinglePrintfTester }
@@ -41,4 +74,10 @@ class PrintfSpec extends ChiselFlatSpec {
   "A printf with Printable ASCII characters 1-127" should "run" in {
     assertTesterPasses { new ASCIIPrintableTester }
   }
+  "A printf with Printable" should "respect port scopes" in {
+    assertTesterPasses { new PrintablePrintfScopeTester }
+  }
+  "A printf with Printable" should "respect wire scopes" in {
+    a[ChiselException] should be thrownBy { assertTesterPasses { new PrintablePrintfWireScopeTester } }
+  }
 }
-- 
cgit v1.2.3


From b72cc42f4f23906db0f201b1d9543a64accbc2ec Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Thu, 6 Oct 2022 21:26:30 +0000
Subject: Update toPrintable for Enums (#2707) (#2763)

(cherry picked from commit 0ff99ca8d573e3487ef496a21c95d962689c3cba)

Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>---
 src/test/scala/chiselTests/StrongEnum.scala | 42 +++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala
index 5b1b13fd..cee1777e 100644
--- a/src/test/scala/chiselTests/StrongEnum.scala
+++ b/src/test/scala/chiselTests/StrongEnum.scala
@@ -164,6 +164,39 @@ class StrongEnumFSM extends Module {
   }
 }
 
+object Opcode extends ChiselEnum {
+  val load = Value(0x03.U)
+  val imm = Value(0x13.U)
+  val auipc = Value(0x17.U)
+  val store = Value(0x23.U)
+  val litValues = List(0x03.U, 0x13.U, 0x17.U, 0x23.U)
+}
+
+class PrintableExecutionTest extends BasicTester {
+  val (count, done) = Counter(true.B, 6)
+  val w = WireDefault(Opcode.load)
+  when(count === 0.U) {
+    w := Opcode.load
+  }
+  when(count === 1.U) {
+    w := Opcode.imm
+  }
+  when(count === 2.U) {
+    w := Opcode.auipc
+  }
+  when(count === 3.U) {
+    w := Opcode.store
+  }
+  when(count === 4.U) { // invalid state
+    val invalidWire = WireInit(UInt(6.W), 0.U)
+    w := Opcode.safe(invalidWire)._1
+  }
+  when(done) {
+    stop()
+  }
+  printf(cf"'$w'\n")
+}
+
 class CastToUIntTester extends BasicTester {
   for ((enum, lit) <- EnumExample.all.zip(EnumExample.litValues)) {
     val mod = Module(new CastToUInt)
@@ -555,6 +588,15 @@ class StrongEnumSpec extends ChiselFlatSpec with Utils {
   it should "correctly check if the enumeration is one of the values in a given sequence" in {
     assertTesterPasses(new IsOneOfTester)
   }
+
+  it should "work with Printables" in {
+    val (log, _, _) = grabStdOutErr(assertTesterPasses { new PrintableExecutionTest })
+    log should include("load")
+    log should include("imm")
+    log should include("auipc")
+    log should include("store")
+    log should include("?????")
+  }
 }
 
 class StrongEnumAnnotator extends Module {
-- 
cgit v1.2.3


From 5b13d04b28ddd05e4acbc5b9b3755c92ac0d9515 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Fri, 7 Oct 2022 19:56:19 +0000
Subject: Make nested IsInstantiables with Data in them work (#2761) (#2766)

* Add unit test for Issue 2760

* checkpoint: Fix for nested instance

* remove comments about stuff not working

* make the test check the output a little more

* relax the requirement on returning empty ioMap

* Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala

* Update core/src/main/scala/chisel3/Data.scala

* Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala

* Add another unit test which unfortunately still passes

* Update core/src/main/scala/chisel3/Data.scala

* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 1f9f26dc2bffcb4cc4daf2dc16c5cb455c6769ef)

Co-authored-by: Megan Wachs <megan@sifive.com>---
 .../experimental/hierarchy/Examples.scala          | 66 ++++++++++++++++++++++
 .../experimental/hierarchy/InstanceSpec.scala      | 10 ++++
 2 files changed, 76 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
index fa26cbde..27725c49 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/Examples.scala
@@ -271,4 +271,70 @@ object Examples {
     @public val mem = Mem(8, UInt(32.W))
     @public val syncReadMem = SyncReadMem(8, UInt(32.W))
   }
+
+  @instantiable
+  class LeafInstantiable(val bundle: Data) {
+    @public val bundle = bundle
+  }
+
+  @instantiable
+  class NestedInstantiable(val in: LeafInstantiable, val out: LeafInstantiable) {
+    @public val in = in
+    @public val out = out
+  }
+
+  @instantiable
+  class AddOneNestedInstantiableData(width: Int) extends Module {
+    @public val in = IO(Input(UInt(width.W)))
+    @public val out = IO(Output(UInt(width.W)))
+    out := in + 1.U
+
+    @public val leafOut = new LeafInstantiable(out)
+    @public val leafIn = new LeafInstantiable(in)
+    @public val nested = new NestedInstantiable(in = leafIn, out = leafOut)
+
+  }
+
+  class AddTwoNestedInstantiableData(width: Int) extends Module {
+    val in = IO(Input(UInt(width.W)))
+    val out = IO(Output(UInt(width.W)))
+    val addOneDef = Definition(new AddOneNestedInstantiableData(width))
+    val i0 = Instance(addOneDef)
+    val i1 = Instance(addOneDef)
+    i0.in := in
+    i1.in := i0.out
+    out := i1.out
+
+    // both are equivalent to the above
+    i1.leafIn.bundle := i0.leafOut.bundle
+    i1.nested.in.bundle := i0.nested.out.bundle
+  }
+
+  class AddTwoNestedInstantiableDataSubmodule(addOneDef: Definition[AddOneNestedInstantiableData]) extends Module {
+    val in = IO(Input(UInt(addOneDef.in.getWidth.W)))
+    val out = IO(Output(UInt(addOneDef.out.getWidth.W)))
+    val i0 = Instance(addOneDef)
+    val i1 = Instance(addOneDef)
+    i0.in := in
+    i1.in := i0.out
+    out := i1.out
+
+    // both are equivalent to the above
+    i1.leafIn.bundle := i0.leafOut.bundle
+    i1.nested.in.bundle := i0.nested.out.bundle
+  }
+
+  class AddTwoNestedInstantiableDataWrapper(width: Int) extends Module {
+    val in = IO(Input(UInt(width.W)))
+    val out = IO(Output(UInt(width.W)))
+
+    val original = Module(new AddOneNestedInstantiableData(width))
+    val copy = Module(new AddTwoNestedInstantiableDataSubmodule(original.toDefinition))
+
+    original.in := in
+    copy.in := original.out
+    out := copy.out
+
+  }
+
 }
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
index 8d8f7ea5..6596cd51 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
@@ -364,6 +364,16 @@ class InstanceSpec extends ChiselFunSpec with Utils {
       annos should contain(MarkAnnotation("~Top|Top/i:HasMems>mem".rt, "Mem"))
       annos should contain(MarkAnnotation("~Top|Top/i:HasMems>syncReadMem".rt, "SyncReadMem"))
     }
+    it("(3.p): should make connectable IOs on nested IsInstantiables that have IO Datas in them") {
+      val (chirrtl, _) = getFirrtlAndAnnos(new AddTwoNestedInstantiableData(4))
+      exactly(3, chirrtl.serialize.split('\n')) should include("i1.in <= i0.out")
+    }
+    it(
+      "(3.q): should make connectable IOs on nested IsInstantiables's Data when the Instance and Definition do not have the same parent"
+    ) {
+      val (chirrtl, _) = getFirrtlAndAnnos(new AddTwoNestedInstantiableDataWrapper(4))
+      exactly(3, chirrtl.serialize.split('\n')) should include("i1.in <= i0.out")
+    }
   }
   describe("4: toInstance") {
     it("4.0: should work on modules") {
-- 
cgit v1.2.3


From 0167a664c38273d7016a6f828dcafdeeff8d32cd Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Mon, 10 Oct 2022 22:32:16 +0000
Subject: Replace execution test with CHIRRTL match test (#2769) (#2770)

(cherry picked from commit 693678dbea0cc4b92a8d8de690768fdc7d90fd14)

Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>---
 src/test/scala/chiselTests/StrongEnum.scala | 45 ++++++++++-------------------
 1 file changed, 15 insertions(+), 30 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala
index cee1777e..e9f412fe 100644
--- a/src/test/scala/chiselTests/StrongEnum.scala
+++ b/src/test/scala/chiselTests/StrongEnum.scala
@@ -169,32 +169,20 @@ object Opcode extends ChiselEnum {
   val imm = Value(0x13.U)
   val auipc = Value(0x17.U)
   val store = Value(0x23.U)
-  val litValues = List(0x03.U, 0x13.U, 0x17.U, 0x23.U)
+  val reg = Value(0x33.U)
+  val lui = Value(0x37.U)
+  val br = Value(0x63.U)
+  val jalr = Value(0x67.U)
+  val jal = Value(0x6f.U)
 }
 
-class PrintableExecutionTest extends BasicTester {
-  val (count, done) = Counter(true.B, 6)
-  val w = WireDefault(Opcode.load)
-  when(count === 0.U) {
-    w := Opcode.load
-  }
-  when(count === 1.U) {
-    w := Opcode.imm
-  }
-  when(count === 2.U) {
-    w := Opcode.auipc
-  }
-  when(count === 3.U) {
-    w := Opcode.store
-  }
-  when(count === 4.U) { // invalid state
-    val invalidWire = WireInit(UInt(6.W), 0.U)
-    w := Opcode.safe(invalidWire)._1
-  }
-  when(done) {
-    stop()
-  }
-  printf(cf"'$w'\n")
+class LoadStoreExample extends Module {
+  val io = IO(new Bundle {
+    val opcode = Input(Opcode())
+    val load_or_store = Output(Bool())
+  })
+  io.load_or_store := io.opcode.isOneOf(Opcode.load, Opcode.store)
+  printf(p"${io.opcode}")
 }
 
 class CastToUIntTester extends BasicTester {
@@ -590,12 +578,9 @@ class StrongEnumSpec extends ChiselFlatSpec with Utils {
   }
 
   it should "work with Printables" in {
-    val (log, _, _) = grabStdOutErr(assertTesterPasses { new PrintableExecutionTest })
-    log should include("load")
-    log should include("imm")
-    log should include("auipc")
-    log should include("store")
-    log should include("?????")
+    ChiselStage.emitChirrtl(new LoadStoreExample) should include(
+      """printf(clock, UInt<1>("h1"), "%c%c%c%c%c", _chiselTestsOpcodePrintable[0], _chiselTestsOpcodePrintable[1], _chiselTestsOpcodePrintable[2], _chiselTestsOpcodePrintable[3], _chiselTestsOpcodePrintable[4])"""
+    )
   }
 }
 
-- 
cgit v1.2.3


From 1957f5ef5c43439144cf779a343707872ca92d6a Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Mon, 17 Oct 2022 22:50:55 +0000
Subject: Add opt-in AutoCloneType for Records (backport #2781) (#2785)

* Add opt-in AutoCloneType for Records (#2781)

There is a new trait, chisel3.experimental.AutoCloneType that is mixed
in to Bundle and can optionally be mixed in to user-defined Records. The
compiler plugin prints a deprecation warning on any user-defined
implementation of cloneType, telling the user to mix in AutoCloneType
before upgrading to 3.6.

(cherry picked from commit a234fd48ac8f5942c38fef5797292014e407b586)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala
#	plugin/src/main/scala/chisel3/internal/plugin/BundleComponent.scala

* Resolve backport conflicts

* Do not make MixedVec extend AutoCloneType

It is a binary incompatible change that can wait for 3.6.

* Waive MiMa false positives

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/AutoClonetypeSpec.scala | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/AutoClonetypeSpec.scala b/src/test/scala/chiselTests/AutoClonetypeSpec.scala
index 5d2cd496..353ae58c 100644
--- a/src/test/scala/chiselTests/AutoClonetypeSpec.scala
+++ b/src/test/scala/chiselTests/AutoClonetypeSpec.scala
@@ -6,6 +6,8 @@ import chisel3._
 import chisel3.testers.TestUtils
 import chisel3.util.QueueIO
 import chisel3.stage.ChiselStage.elaborate
+import chisel3.experimental.AutoCloneType
+import scala.collection.immutable.ListMap
 
 class BundleWithIntArg(val i: Int) extends Bundle {
   val out = UInt(i.W)
@@ -72,6 +74,25 @@ class InheritingBundle extends QueueIO(UInt(8.W), 8) {
   val error = Output(Bool())
 }
 
+class RecordAutoCloneType[T <: Data](gen: T) extends Record with AutoCloneType {
+  lazy val elements = ListMap("value" -> gen)
+  // This is a weird thing to do, but as only Bundles have these methods, it should be legal
+  protected def _elementsImpl: Iterable[(String, Any)] = elements
+  protected def _usingPlugin = false
+}
+
+// Records that don't mixin AutoCloneType should still be able to implement the related methods
+// NOTE: This is a very weird thing to do, don't do it.
+class RecordWithVerbotenMethods(w: Int) extends Record {
+  lazy val elements = ListMap("value" -> UInt(w.W))
+  override def cloneType: this.type = (new RecordWithVerbotenMethods(w)).asInstanceOf[this.type]
+  // Verboten methods
+  protected def _usingPlugin = false
+  protected override def _cloneTypeImpl = this.cloneType
+
+  protected def _elementsImpl: Iterable[(String, Any)] = Nil
+}
+
 class AutoClonetypeSpec extends ChiselFlatSpec with Utils {
 
   "Bundles with Scala args" should "not need clonetype" in {
@@ -400,4 +421,24 @@ class AutoClonetypeSpec extends ChiselFlatSpec with Utils {
     }
     elaborate(new MyModule)
   }
+
+  it should "support Records that mixin AutoCloneType" in {
+    class MyModule extends Module {
+      val gen = new RecordAutoCloneType(UInt(8.W))
+      val in = IO(Input(gen))
+      val out = IO(Output(gen))
+      out := in
+    }
+    elaborate(new MyModule)
+  }
+
+  it should "support Records that don't mixin AutoCloneType and use forbidden methods" in {
+    class MyModule extends Module {
+      val gen = new RecordWithVerbotenMethods(8)
+      val in = IO(Input(gen))
+      val out = IO(Output(gen))
+      out := in
+    }
+    elaborate(new MyModule)
+  }
 }
-- 
cgit v1.2.3


From 80b3b28f451efa85be50994f732599f043f83d86 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Wed, 19 Oct 2022 14:28:34 -0700
Subject: Don't modify the Builder prefix if reinvoking suggestName on a Data
 (backport #2789) (#2790)

* Only set the chisel3 Builder prefix during the first invocation of suggestName

(cherry picked from commit b684506abab2f7b99d56181d548cb8119d317323)

# Conflicts:
#	core/src/main/scala/chisel3/internal/Builder.scala

* Add simple test to show bug fix

(cherry picked from commit 255068b105de77a045a0016e3a157b52a81c86d6)

* Fix merge conflict

* Fix test to not use Hardware inside a bundle for prefixing

Co-authored-by: Jared Barocsi <jared.barocsi@sifive.com>---
 src/test/scala/chiselTests/naming/PrefixSpec.scala | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index b5eac1d4..d8cb3348 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -521,4 +521,30 @@ class PrefixSpec extends ChiselPropSpec with Utils {
       Select.wires(top).map(_.instanceName) should be(List("nonData_value", "value"))
     }
   }
+  property("Prefixing should not be affected by repeated calls of suggestName") {
+    class Test extends Module {
+      val in = IO(Input(UInt(3.W)))
+      val prefixed = {
+        val wire = Wire(UInt(3.W)).suggestName("wire") // "prefixed_wire"
+        wire := in
+
+        val thisShouldNotBeHere = {
+          // Second suggestName doesn't modify the instanceName since it was
+          // already suggested, but also should not modify the prefix either
+
+          // Incorrect behavior would rename the wire to
+          // "prefixed_thisShouldNotBeHere_wire"
+          wire.suggestName("wire")
+
+          val out = IO(Output(UInt(3.W)))
+          out := wire
+          out
+        }
+        thisShouldNotBeHere
+      }
+    }
+    aspectTest(() => new Test) { top: Test =>
+      Select.wires(top).map(_.instanceName) should be(List("prefixed_wire"))
+    }
+  }
 }
-- 
cgit v1.2.3


From d997acb05e5a307afb7c9ad4c136b9b4e1506efc Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Sun, 23 Oct 2022 19:01:43 +0000
Subject: Don't invalidate ExtModule ports in an explicitInvalidate = true
 context (backport #2795) (#2799)

* Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795)

* Don't invalidate ExtModule ports in an explicitInvalidate = true context

ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`.

(cherry picked from commit 8e24a281545d25f6501dcc872eabdfb30bacd69d)

# Conflicts:
#	core/src/main/scala/chisel3/BlackBox.scala

* Resolve backport conflicts

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/CompatibilitySpec.scala | 22 ++++++++++++++++++++++
 src/test/scala/chiselTests/ExtModule.scala         | 17 +++++++++++++++++
 src/test/scala/chiselTests/aop/InjectionSpec.scala |  1 +
 3 files changed, 40 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 41cfbec4..5a3b43e6 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -614,4 +614,26 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     ChiselStage.elaborate(new MyModule)
   }
 
+  behavior.of("BlackBox")
+
+  it should "have invalidated ports in a compatibility context" in {
+    class ExtModuleInvalidatedTester extends Module {
+      val io = IO(new Bundle {
+        val in = Input(UInt(8.W))
+        val out = Output(UInt(8.W))
+      })
+      val inst = Module(new BlackBox {
+        val io = IO(new Bundle {
+          val in = Input(UInt(8.W))
+          val out = Output(UInt(8.W))
+        })
+      })
+      inst.io.in := io.in
+      io.out := inst.io.out
+    }
+
+    val chirrtl = ChiselStage.emitChirrtl(new ExtModuleInvalidatedTester)
+    chirrtl should include("inst.in is invalid")
+    chirrtl should include("inst.out is invalid")
+  }
 }
diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala
index b5a8ff7c..3ab4cc32 100644
--- a/src/test/scala/chiselTests/ExtModule.scala
+++ b/src/test/scala/chiselTests/ExtModule.scala
@@ -88,6 +88,17 @@ class ExtModuleWithFlatIOTester extends Module {
   io <> inst.badIO
 }
 
+class ExtModuleInvalidatedTester extends Module {
+  val in = IO(Input(UInt(8.W)))
+  val out = IO(Output(UInt(8.W)))
+  val inst = Module(new ExtModule {
+    val in = IO(Input(UInt(8.W)))
+    val out = IO(Output(UInt(8.W)))
+  })
+  inst.in := in
+  out := inst.out
+}
+
 class ExtModuleSpec extends ChiselFlatSpec {
   "A ExtModule inverter" should "work" in {
     assertTesterPasses({ new ExtModuleTester }, Seq("/chisel3/BlackBoxTest.v"), TesterDriver.verilatorOnly)
@@ -117,4 +128,10 @@ class ExtModuleSpec extends ChiselFlatSpec {
     chirrtl should include("inst.in <= io.in")
     chirrtl shouldNot include("badIO")
   }
+
+  it should "not have invalidated ports in a chisel3._ context" in {
+    val chirrtl = ChiselStage.emitChirrtl(new ExtModuleInvalidatedTester)
+    chirrtl shouldNot include("inst.in is invalid")
+    chirrtl shouldNot include("inst.out is invalid")
+  }
 }
diff --git a/src/test/scala/chiselTests/aop/InjectionSpec.scala b/src/test/scala/chiselTests/aop/InjectionSpec.scala
index 9b29b0ba..1b69efa3 100644
--- a/src/test/scala/chiselTests/aop/InjectionSpec.scala
+++ b/src/test/scala/chiselTests/aop/InjectionSpec.scala
@@ -108,6 +108,7 @@ class InjectionSpec extends ChiselFlatSpec with Utils {
     { _: SubmoduleManipulationTester =>
       // By creating a second SubmoduleA, the module names would conflict unless they were uniquified
       val moduleSubmoduleC = Module(new SubmoduleC)
+      moduleSubmoduleC.io <> DontCare
       //if we're here then we've elaborated correctly
       stop()
     }
-- 
cgit v1.2.3


From f86c1ff7b39146f23cd1959bcc63dcb3b0b27125 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Sun, 23 Oct 2022 22:27:06 +0000
Subject: Fix for <> to BlackBox.IO with Compatibility Bundles (#2801) (#2803)

MonoConnect.traceFlow now properly handles coerced directions.
Also minor improvement to getClassName especially useful in test case printf debugging.

(cherry picked from commit 3aba755bdcf996c0fbd846d13268fd6641b29e96)

Co-authored-by: Megan Wachs <megan@sifive.com>---
 src/test/scala/chiselTests/BulkConnectSpec.scala   |  15 +-
 .../CompatibilityInteroperabilitySpec.scala        | 155 +++++++++++++++++++++
 2 files changed, 169 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala
index 281890d4..0a1616d3 100644
--- a/src/test/scala/chiselTests/BulkConnectSpec.scala
+++ b/src/test/scala/chiselTests/BulkConnectSpec.scala
@@ -54,7 +54,15 @@ class BulkConnectSpec extends ChiselPropSpec {
     })
 
     chirrtl should include("out.buzz.foo <= in.buzz.foo")
+    chirrtl should include("out.fizz <= in.fizz")
+    chirrtl should include("deq.bits <- enq.bits")
+    chirrtl should include("deq.valid <= enq.valid")
+    chirrtl should include("enq.ready <= deq.ready")
+
     chirrtl shouldNot include("deq <= enq")
+    chirrtl shouldNot include("deq.bits.foo <= enq.bits.foo")
+    chirrtl shouldNot include("deq.bits.foo <- enq.bits.foo")
+    chirrtl shouldNot include("deq.bits.bar")
   }
 
   property("Chisel connects should not emit FIRRTL bulk connects between differing FIRRTL types") {
@@ -74,7 +82,9 @@ class BulkConnectSpec extends ChiselPropSpec {
       out <> in
     })
     // out <- in is illegal FIRRTL
-    chirrtl should include("out.foo.bar <= in.foo.bar")
+    exactly(2, chirrtl.split('\n')) should include("out.foo.bar <= in.foo.bar")
+    chirrtl shouldNot include("out <= in")
+    chirrtl shouldNot include("out <- in")
   }
 
   property("Chisel connects should not emit a FIRRTL bulk connect for a bidirectional MonoConnect") {
@@ -91,6 +101,9 @@ class BulkConnectSpec extends ChiselPropSpec {
     })
 
     chirrtl shouldNot include("wire <= enq")
+    chirrtl should include("wire.bits <= enq.bits")
+    chirrtl should include("wire.valid <= enq.valid")
+    chirrtl should include("wire.ready <= enq.ready")
     chirrtl should include("deq <= enq")
   }
 
diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index 1e199297..e2fb2179 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -3,6 +3,7 @@
 package chiselTests
 
 import scala.collection.immutable.ListMap
+import chisel3.stage.ChiselStage.emitChirrtl
 
 // Keep Chisel._ separate from chisel3._ below
 object CompatibilityComponents {
@@ -390,4 +391,158 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
     compile(new Top(true))
     compile(new Top(false))
   }
+
+  "A BlackBox with Chisel._ fields in its IO" should "bulk connect in import chisel3._ code correctly" in {
+    object Compat {
+      import Chisel._
+      class LegacyChiselIO extends Bundle {
+        val foo = Output(Bool())
+        val bar = Output(Bool())
+      }
+    }
+    object Chisel3 {
+      import chisel3._
+      import chisel3.util.Valid
+
+      class FooModuleIO extends Bundle {
+        val quz = Input(new QuzIO)
+        val foo = Output(Bool())
+        val bar = Input(Bool())
+      }
+      class QuzIO extends Bundle {
+        val q = Flipped(Valid(new Compat.LegacyChiselIO))
+      }
+      class FooModule extends Module {
+        val io = IO(new FooModuleIO)
+        io <> DontCare
+      }
+      class FooMirrorBlackBox extends BlackBox {
+        val io = IO(Flipped(new FooModuleIO))
+      }
+      class Top extends Module {
+        val foo = Module(new FooModule)
+        val mirror = Module(new FooMirrorBlackBox)
+        foo.io <> mirror.io
+      }
+    }
+    val chirrtl = emitChirrtl(new Chisel3.Top)
+    chirrtl should include("foo.io.bar <= mirror.bar")
+    chirrtl should include("mirror.foo <= foo.io.foo")
+    chirrtl should include("foo.io.quz.q.bits <- mirror.quz.q.bits")
+    chirrtl should include("foo.io.quz.q.valid <= mirror.quz.q.valid")
+  }
+
+  "A chisel3.Bundle bulk connected to a Chisel Bundle in either direction" should "work even with mismatched fields" in {
+    object Compat {
+      import Chisel._
+      class FooBundle extends Bundle {
+        val foo = UInt(width = 8)
+      }
+    }
+    object Chisel3 {
+      import chisel3._
+      class BarBundle extends Bundle {
+        val bar = UInt(8.W)
+      }
+      class MyModule(swap: Boolean) extends Module {
+        val in = IO(Input(if (swap) new Compat.FooBundle else new BarBundle))
+        val out = IO(Output(if (swap) new BarBundle else new Compat.FooBundle))
+        out <> DontCare
+        out <> in
+      }
+    }
+    val chirrtl0 = emitChirrtl(new Chisel3.MyModule(true))
+    chirrtl0 shouldNot include("<=")
+    chirrtl0 should include("out <- in")
+    val chirrtl1 = emitChirrtl(new Chisel3.MyModule(true))
+    chirrtl1 shouldNot include("<=")
+    chirrtl1 should include("out <- in")
+  }
+
+  it should "work with missing fields in the Chisel._" in {
+    object Compat {
+      import Chisel._
+      class FooBundle extends Bundle {
+        val foo = UInt(width = 8)
+      }
+    }
+    object Chisel3 {
+      import chisel3._
+      class FooBarBundle extends Bundle {
+        val foo = UInt(8.W)
+        val bar = UInt(8.W)
+      }
+
+      class MyModule(swap: Boolean) extends Module {
+        val in = IO(Input(if (swap) new Compat.FooBundle else new FooBarBundle))
+        val out = IO(Output(if (swap) new FooBarBundle else new Compat.FooBundle))
+        out <> DontCare
+        out <> in
+      }
+    }
+    val chirrtl0 = emitChirrtl(new Chisel3.MyModule(true))
+    chirrtl0 shouldNot include("<=")
+    chirrtl0 should include("out <- in")
+    val chirrtl1 = emitChirrtl(new Chisel3.MyModule(true))
+    chirrtl1 shouldNot include("<=")
+    chirrtl1 should include("out <- in")
+  }
+
+  it should "work with missing fields in the chisel3._" in {
+    object Compat {
+      import Chisel._
+      class FooBundle extends Bundle {
+        val foo = UInt(width = 8)
+      }
+    }
+    object Chisel3 {
+      import chisel3._
+      class FooBarBundle extends Bundle {
+        val foo = UInt(8.W)
+        val bar = UInt(8.W)
+      }
+
+      class MyModule(swap: Boolean) extends Module {
+        val in = IO(Input(if (swap) new Compat.FooBundle else new FooBarBundle))
+        val out = IO(Output(if (swap) new FooBarBundle else new Compat.FooBundle))
+        out <> DontCare
+        out <> in
+      }
+    }
+    val chirrtl0 = emitChirrtl(new Chisel3.MyModule(true))
+    chirrtl0 shouldNot include("<=")
+    chirrtl0 should include("out <- in")
+    val chirrtl1 = emitChirrtl(new Chisel3.MyModule(true))
+    chirrtl1 shouldNot include("<=")
+    chirrtl1 should include("out <- in")
+  }
+
+  it should "emit FIRRTL connects if possible" in {
+    object Compat {
+      import Chisel._
+      class FooBarBundle extends Bundle {
+        val foo = UInt(8.W)
+        val bar = Flipped(UInt(8.W))
+      }
+    }
+    object Chisel3 {
+      import chisel3._
+      class FooBarBundle extends Bundle {
+        val foo = Output(UInt(8.W))
+        val bar = Input(UInt(8.W))
+      }
+      class MyModule(swap: Boolean) extends Module {
+        val in = IO(Flipped((if (swap) new Compat.FooBarBundle else new FooBarBundle)))
+        val out = IO(if (swap) new FooBarBundle else new Compat.FooBarBundle)
+        out <> DontCare
+        out <> in
+      }
+    }
+    val chirrtl0 = emitChirrtl(new Chisel3.MyModule(true))
+    chirrtl0 should include("out <= in")
+    chirrtl0 shouldNot include("out <- in")
+    val chirrtl1 = emitChirrtl(new Chisel3.MyModule(true))
+    chirrtl1 should include("out <= in")
+    chirrtl1 shouldNot include("out <- in")
+  }
 }
-- 
cgit v1.2.3


From 4149157df6531d124483d992daf96cf4e62a0f0c Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Fri, 4 Nov 2022 18:20:07 +0000
Subject: Add PartialDataView.supertype (backport #2826) (#2827)

* Add PartialDataView.supertype (#2826)

This factory method makes it easy to create PartialDataViews from a
Bundle type to its supertype. Because of the typing relationship, there
is no need to provide a mapping between fields. The only thing necessary
is to provide a function for constructing an instance of the supertype
from an instance of the subtype.

(cherry picked from commit 251d454a224e5a961438ba0ea41134d7da7a5992)

# Conflicts:
#	core/src/main/scala/chisel3/experimental/dataview/package.scala
#	src/test/scala/chiselTests/experimental/DataView.scala

* Resolve backport conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 .../scala/chiselTests/experimental/DataView.scala  | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
index ac8357f0..3673778b 100644
--- a/src/test/scala/chiselTests/experimental/DataView.scala
+++ b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -177,6 +177,28 @@ class DataViewSpec extends ChiselFlatSpec {
     chirrtl should include("fooOut.foo <= barIn.foo")
   }
 
+  it should "be easy to make a PartialDataView viewing a Bundle as a Parent Bundle type" in {
+    class Foo(x: Int) extends Bundle {
+      val foo = UInt(x.W)
+    }
+    class Bar(val x: Int) extends Foo(x) {
+      val bar = UInt(x.W)
+    }
+    implicit val view = PartialDataView.supertype[Bar, Foo](b => new Foo(b.x))
+    class MyModule extends Module {
+      val fooIn = IO(Input(new Foo(8)))
+      val barOut = IO(Output(new Bar(8)))
+      barOut.viewAs[Foo] := fooIn
+
+      val barIn = IO(Input(new Bar(8)))
+      val fooOut = IO(Output(new Foo(8)))
+      fooOut := barIn.viewAs[Foo]
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+    chirrtl should include("barOut.foo <= fooIn.foo")
+    chirrtl should include("fooOut.foo <= barIn.foo")
+  }
+
   it should "error if viewing a parent Bundle as a child Bundle type" in {
     assertTypeError("""
       class Foo extends Bundle {
-- 
cgit v1.2.3


From 017bd6b9c96974df2a3c4f35e069d60fec001f2e Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Sat, 5 Nov 2022 22:31:07 +0000
Subject: Support Analog in DataView (#2782) (#2828)

Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 26100a875c69bf56f7442fac82ca9c74ad3596eb)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/experimental/DataView.scala  | 12 +++++++++++-
 .../scala/chiselTests/experimental/FlatIOSpec.scala     | 17 ++++++++++++++++-
 2 files changed, 27 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
index 3673778b..cefc893c 100644
--- a/src/test/scala/chiselTests/experimental/DataView.scala
+++ b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.experimental.dataview._
 import chisel3.experimental.conversions._
 import chisel3.experimental.DataMirror.internal.chiselTypeClone
-import chisel3.experimental.HWTuple2
+import chisel3.experimental.{Analog, HWTuple2}
 import chisel3.stage.ChiselStage
 import chisel3.util.{Decoupled, DecoupledIO}
 
@@ -91,6 +91,16 @@ class DataViewSpec extends ChiselFlatSpec {
     chirrtl should include("bar <= in")
   }
 
+  it should "handle viewing Analogs as Analogs" in {
+    class MyModule extends Module {
+      val foo = IO(Analog(8.W))
+      val bar = IO(Analog(8.W))
+      foo <> bar.viewAs[Analog]
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+    chirrtl should include("attach (foo, bar)")
+  }
+
   it should "handle viewing Bundles as their same concrete type" in {
     class MyBundle extends Bundle {
       val foo = UInt(8.W)
diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
index dfce447f..ebb7cbdb 100644
--- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
+++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
@@ -5,7 +5,7 @@ package chiselTests.experimental
 import chisel3._
 import chisel3.util.Valid
 import chisel3.stage.ChiselStage.emitChirrtl
-import chisel3.experimental.FlatIO
+import chisel3.experimental.{Analog, FlatIO}
 import chiselTests.ChiselFlatSpec
 
 class FlatIOSpec extends ChiselFlatSpec {
@@ -48,4 +48,19 @@ class FlatIOSpec extends ChiselFlatSpec {
     val chirrtl = emitChirrtl(new MyModule)
     chirrtl should include("out[addr] <= in[addr]")
   }
+
+  it should "support Analog members" in {
+    class MyBundle extends Bundle {
+      val foo = Output(UInt(8.W))
+      val bar = Analog(8.W)
+    }
+    class MyModule extends RawModule {
+      val in = IO(Flipped(new MyBundle))
+      val out = IO(new MyBundle)
+      out <> in
+    }
+    val chirrtl = emitChirrtl(new MyModule)
+    chirrtl should include("out.foo <= in.foo")
+    chirrtl should include("attach (out.bar, in.bar)")
+  }
 }
-- 
cgit v1.2.3


From 086c6806708d14ad5144ca064d4c644d0f62592d Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Mon, 7 Nov 2022 18:29:31 +0000
Subject: Add DataMirror.getParent for getting parents of Modules (#2825)
 (#2833)

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit fce8394bb0ddc9ae0d9c6668e034e483bd6b71c5)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 .../chiselTests/experimental/DataMirrorSpec.scala  | 33 ++++++++++++++++++++++
 1 file changed, 33 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/experimental/DataMirrorSpec.scala b/src/test/scala/chiselTests/experimental/DataMirrorSpec.scala
index 731596ec..09fdf3c4 100644
--- a/src/test/scala/chiselTests/experimental/DataMirrorSpec.scala
+++ b/src/test/scala/chiselTests/experimental/DataMirrorSpec.scala
@@ -8,7 +8,26 @@ import chisel3.stage.ChiselStage
 import chisel3.experimental.DataMirror
 import chiselTests.ChiselFlatSpec
 
+object DataMirrorSpec {
+  import org.scalatest.matchers.should.Matchers._
+  class GrandChild(parent: RawModule) extends Module {
+    DataMirror.getParent(this) should be(Some(parent))
+  }
+  class Child(parent: RawModule) extends Module {
+    val inst = Module(new GrandChild(this))
+    DataMirror.getParent(inst) should be(Some(this))
+    DataMirror.getParent(this) should be(Some(parent))
+  }
+  class Parent extends Module {
+    val inst = Module(new Child(this))
+    DataMirror.getParent(inst) should be(Some(this))
+    DataMirror.getParent(this) should be(None)
+  }
+}
+
 class DataMirrorSpec extends ChiselFlatSpec {
+  import DataMirrorSpec._
+
   behavior.of("DataMirror")
 
   def assertBinding(x: Data, io: Boolean, wire: Boolean, reg: Boolean) = {
@@ -55,4 +74,18 @@ class DataMirrorSpec extends ChiselFlatSpec {
     }
     ChiselStage.elaborate(new MyModule)
   }
+
+  it should "support getParent for normal modules" in {
+    ChiselStage.elaborate(new Parent)
+  }
+
+  it should "support getParent for normal modules even when used in a D/I context" in {
+    import chisel3.experimental.hierarchy._
+    class Top extends Module {
+      val defn = Definition(new Parent)
+      val inst = Instance(defn)
+      DataMirror.getParent(this) should be(None)
+    }
+    ChiselStage.elaborate(new Top)
+  }
 }
-- 
cgit v1.2.3


From 76ada881d077118384907f498576b3b338291ff6 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Mon, 7 Nov 2022 19:13:49 +0000
Subject: Bugfix converter clearing flips (backport #2788) (#2832)

* Bugfix converter clearing flips (#2788)

* Bugfix: Output on Vec of bundle with mixed field orientations
* Bugfix OpaqueTypes clearing flips

(cherry picked from commit f05bff1a337589bafebd08783bb0f6a72092a95a)

# Conflicts:
#	src/test/scala/chiselTests/Direction.scala

* Resolve backport conflicts

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/test/scala/chiselTests/Direction.scala | 61 ++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 0c657273..03755e83 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -7,6 +7,8 @@ import chisel3._
 import chisel3.stage.ChiselStage
 import org.scalatest.matchers.should.Matchers
 
+import scala.collection.immutable.SeqMap
+
 class DirectionedBundle extends Bundle {
   val in = Input(UInt(32.W))
   val out = Output(UInt(32.W))
@@ -327,4 +329,63 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
       }
     }
   }
+  property("Bugfix: marking Vec fields with mixed directionality as Output/Input clears inner directions") {
+    class Decoupled extends Bundle {
+      val bits = UInt(3.W)
+      val valid = Bool()
+      val ready = Flipped(Bool())
+    }
+    class Coercing extends Bundle {
+      val source = Output(Vec(1, new Decoupled()))
+      val sink = Input(Vec(1, new Decoupled()))
+    }
+    class MyModule extends RawModule {
+      val io = IO(new Coercing())
+      val source = IO(Output(Vec(1, new Decoupled())))
+      val sink = IO(Input(Vec(1, new Decoupled())))
+    }
+
+    val emitted: String = ChiselStage.emitChirrtl(new MyModule)
+
+    assert(
+      emitted.contains(
+        "output io : { source : { bits : UInt<3>, valid : UInt<1>, ready : UInt<1>}[1], flip sink : { bits : UInt<3>, valid : UInt<1>, ready : UInt<1>}[1]}"
+      )
+    )
+    assert(
+      emitted.contains(
+        "output source : { bits : UInt<3>, valid : UInt<1>, ready : UInt<1>}[1]"
+      )
+    )
+    assert(
+      emitted.contains(
+        "input sink : { bits : UInt<3>, valid : UInt<1>, ready : UInt<1>}[1]"
+      )
+    )
+  }
+  property("Bugfix: clearing all flips inside an opaque type") {
+
+    class Decoupled extends Bundle {
+      val bits = UInt(3.W)
+      val valid = Bool()
+      val ready = Flipped(Bool())
+    }
+    class MyOpaqueType extends Record {
+      val k = new Decoupled()
+      val elements = SeqMap("" -> k)
+      override def opaqueType = elements.size == 1
+      override def cloneType: this.type = (new MyOpaqueType).asInstanceOf[this.type]
+    }
+    class MyModule extends RawModule {
+      val w = Wire(new MyOpaqueType())
+    }
+
+    val emitted: String = ChiselStage.emitChirrtl(new MyModule)
+
+    assert(
+      emitted.contains(
+        "wire w : { bits : UInt<3>, valid : UInt<1>, flip ready : UInt<1>}"
+      )
+    )
+  }
 }
-- 
cgit v1.2.3


From f2ef3a8ee378a307661bd598cd44d4b895b9352e Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Tue, 8 Nov 2022 07:05:53 +0000
Subject: Improve Record.bind and Detect Records with unstable elements
 (backport #2829) (#2831)

* Add Aggregate.elementsIterator and micro-optimize

elementsIterator provides a more efficient API for iterating on the
elements of Aggregates. It is especially useful for Records where
getElements returns a Seq and thus eagerly constructs a new
datastructure which may then just be iterated on anyway.

This new elementsIterator API is then used throughout the codebase where
it makes sense.

Also change Vec.getElements to just return the underlying self instead
of constructing a new Seq.

(cherry picked from commit defa440b349031475daeff4024fad04925cccee6)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala
#	core/src/main/scala/chisel3/Module.scala
#	core/src/main/scala/chisel3/experimental/Trace.scala

* Move Aggregate.bind inline into Record.bind

Vec overrides bind and does not call the version in Aggregate so the
version in Aggregate is misleading in that its only ever used by
Records. Now there is no version in Aggregate and the actual
functionality and use is more clear.

(cherry picked from commit b054c30ba47026cb2a9b28c696a0a0a58b1e2ee7)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala

* Extract and optimize duplicate checking Record.bind

This replaces an immutable.Map with a single mutable.HashSet and saves
the allocation of # elements Seqs.

(cherry picked from commit 832ea52bc23424bb75b9654422b725a9cafaef40)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala

* Add check for Records that define def elements

(cherry picked from commit a4f223415de19e2a732e0b6a8fe681f706a19a56)

* Resolve backport conflicts

* Make elementsIterator final and package private

* Waive false MiMa failure

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/RecordSpec.scala | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index cde18da7..509edbbc 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -325,4 +325,17 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
   "CustomBundle" should "check the types" in {
     ChiselStage.elaborate { new RecordTypeTester }
   }
+
+  "Record with unstable elements" should "error" in {
+    class MyRecord extends Record {
+      def elements = SeqMap("a" -> UInt(8.W))
+      override def cloneType: this.type = (new MyRecord).asInstanceOf[this.type]
+    }
+    val e = the[ChiselException] thrownBy {
+      ChiselStage.elaborate(new Module {
+        val io = IO(Input(new MyRecord))
+      })
+    }
+    e.getMessage should include("does not return the same objects when calling .elements multiple times")
+  }
 }
-- 
cgit v1.2.3


From bfa9f7465e6069b1e624126f9e14245b69e7c0a9 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Tue, 8 Nov 2022 17:27:07 +0000
Subject: Switch to using experimental trait for OpaqueTypes (backport #2783)
 (#2836)

* Switch to using experimental trait for OpaqueTypes (#2783)

This makes it more clear that the feature is experimental. Users may
still override the opaqueType method for more dynamic control over when
instances of a given Record are OpaqueTypes or not, but they are
discouraged from doing so.

(cherry picked from commit 7525dc71ccc2050d8e4a68b38f3b76920ba693fc)

* Fix cloneType in RecordSpec

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/Direction.scala  |  4 +-
 src/test/scala/chiselTests/RecordSpec.scala | 85 ++++++++++++++++++++++++-----
 2 files changed, 72 insertions(+), 17 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 03755e83..642a507c 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -4,6 +4,7 @@ package chiselTests
 
 import org.scalatest._
 import chisel3._
+import chisel3.experimental.OpaqueType
 import chisel3.stage.ChiselStage
 import org.scalatest.matchers.should.Matchers
 
@@ -370,10 +371,9 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
       val valid = Bool()
       val ready = Flipped(Bool())
     }
-    class MyOpaqueType extends Record {
+    class MyOpaqueType extends Record with OpaqueType {
       val k = new Decoupled()
       val elements = SeqMap("" -> k)
-      override def opaqueType = elements.size == 1
       override def cloneType: this.type = (new MyOpaqueType).asInstanceOf[this.type]
     }
     class MyModule extends RawModule {
diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index 509edbbc..3414ec8a 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -6,7 +6,7 @@ import chisel3._
 import chisel3.stage.ChiselStage
 import chisel3.testers.BasicTester
 import chisel3.util.{Counter, Queue}
-import chisel3.experimental.DataMirror
+import chisel3.experimental.{DataMirror, OpaqueType}
 
 import scala.collection.immutable.SeqMap
 
@@ -109,10 +109,9 @@ trait RecordSpecUtils {
     require(!DataMirror.checkTypeEquivalence(wire1, wire2))
   }
 
-  class SingleElementRecord extends Record {
+  class SingleElementRecord extends Record with OpaqueType {
     private val underlying = UInt(8.W)
     val elements = SeqMap("" -> underlying)
-    override def opaqueType = elements.size == 1
     override def cloneType: this.type = (new SingleElementRecord).asInstanceOf[this.type]
 
     def +(that: SingleElementRecord): SingleElementRecord = {
@@ -132,17 +131,15 @@ trait RecordSpecUtils {
     out := in1 + in2
   }
 
-  class InnerRecord extends Record {
+  class InnerRecord extends Record with OpaqueType {
     val k = new InnerInnerRecord
     val elements = SeqMap("" -> k)
-    override def opaqueType = elements.size == 1
     override def cloneType: this.type = (new InnerRecord).asInstanceOf[this.type]
   }
 
-  class InnerInnerRecord extends Record {
+  class InnerInnerRecord extends Record with OpaqueType {
     val k = new SingleElementRecord
     val elements = SeqMap("" -> k)
-    override def opaqueType = elements.size == 1
     override def cloneType: this.type = (new InnerInnerRecord).asInstanceOf[this.type]
   }
 
@@ -163,11 +160,10 @@ trait RecordSpecUtils {
     io.bar.elements.head._2 := io.foo.elements.head._2
   }
 
-  class NamedSingleElementRecord extends Record {
+  class NamedSingleElementRecord extends Record with OpaqueType {
     private val underlying = UInt(8.W)
     val elements = SeqMap("unused" -> underlying)
 
-    override def opaqueType = elements.size == 1
     override def cloneType: this.type = (new NamedSingleElementRecord).asInstanceOf[this.type]
   }
 
@@ -177,7 +173,7 @@ trait RecordSpecUtils {
     out := in
   }
 
-  class ErroneousOverride extends Record {
+  class ErroneousOverride extends Record with OpaqueType {
     private val underlyingA = UInt(8.W)
     private val underlyingB = UInt(8.W)
     val elements = SeqMap("x" -> underlyingA, "y" -> underlyingB)
@@ -191,6 +187,44 @@ trait RecordSpecUtils {
     val out = IO(Output(new ErroneousOverride))
     out := in
   }
+
+  class NotActuallyOpaqueType extends Record with OpaqueType {
+    private val underlyingA = UInt(8.W)
+    private val underlyingB = UInt(8.W)
+    val elements = SeqMap("x" -> underlyingA, "y" -> underlyingB)
+
+    override def opaqueType = false
+    override def cloneType: this.type = (new NotActuallyOpaqueType).asInstanceOf[this.type]
+  }
+
+  class NotActuallyOpaqueTypeModule extends Module {
+    val in = IO(Input(new NotActuallyOpaqueType))
+    val out = IO(Output(new NotActuallyOpaqueType))
+    out := in
+  }
+
+  // Illustrate how to dyanmically decide between OpaqueType or not
+  sealed trait MaybeBoxed[T <: Data] extends Record {
+    def underlying: T
+    def boxed:      Boolean
+  }
+  object MaybeBoxed {
+    def apply[T <: Data](gen: T, boxed: Boolean): MaybeBoxed[T] = {
+      if (boxed) new Boxed(gen) else new Unboxed(gen)
+    }
+  }
+  class Boxed[T <: Data](gen: T) extends MaybeBoxed[T] {
+    def boxed = true
+    lazy val elements = SeqMap("underlying" -> gen.cloneType)
+    def underlying = elements.head._2
+    override def cloneType: this.type = (new Boxed(gen)).asInstanceOf[this.type]
+  }
+  class Unboxed[T <: Data](gen: T) extends MaybeBoxed[T] with OpaqueType {
+    def boxed = false
+    lazy val elements = SeqMap("" -> gen.cloneType)
+    def underlying = elements.head._2
+    override def cloneType: this.type = (new Unboxed(gen)).asInstanceOf[this.type]
+  }
 }
 
 class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
@@ -229,14 +263,14 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     e.getMessage should include("contains aliased fields named (bar,foo)")
   }
 
-  they should "be OpaqueType for maps with single unnamed elements" in {
+  they should "support OpaqueType for maps with single unnamed elements" in {
     val singleElementChirrtl = ChiselStage.emitChirrtl { new SingleElementRecordModule }
     singleElementChirrtl should include("input in1 : UInt<8>")
     singleElementChirrtl should include("input in2 : UInt<8>")
     singleElementChirrtl should include("add(in1, in2)")
   }
 
-  they should "work correctly for toTarget in nested opaque type Records" in {
+  they should "work correctly for toTarget in nested OpaqueType Records" in {
     var mod: NestedRecordModule = null
     ChiselStage.elaborate { mod = new NestedRecordModule; mod }
     val testStrings = Seq(
@@ -250,7 +284,7 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     testStrings.foreach(x => assert(x == "~NestedRecordModule|InnerModule>io.foo"))
   }
 
-  they should "work correctly when connecting nested opaque type elements" in {
+  they should "work correctly when connecting nested OpaqueType elements" in {
     val nestedRecordChirrtl = ChiselStage.emitChirrtl { new NestedRecordModule }
     nestedRecordChirrtl should include("input in : UInt<8>")
     nestedRecordChirrtl should include("output out : UInt<8>")
@@ -260,18 +294,39 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     nestedRecordChirrtl should include("io.bar <= io.foo")
   }
 
-  they should "throw an error when map contains a named element and opaqueType is overriden to true" in {
+  they should "throw an error when map contains a named element and OpaqueType is mixed in" in {
     (the[Exception] thrownBy extractCause[Exception] {
       ChiselStage.elaborate { new NamedSingleElementModule }
     }).getMessage should include("Opaque types must have exactly one element with an empty name")
   }
 
-  they should "throw an error when map contains more than one element and opaqueType is overriden to true" in {
+  they should "throw an error when map contains more than one element and OpaqueType is mixed in" in {
     (the[Exception] thrownBy extractCause[Exception] {
       ChiselStage.elaborate { new ErroneousOverrideModule }
     }).getMessage should include("Opaque types must have exactly one element with an empty name")
   }
 
+  they should "work correctly when an OpaqueType overrides the def as false" in {
+    val chirrtl = ChiselStage.emitChirrtl(new NotActuallyOpaqueTypeModule)
+    chirrtl should include("input in : { y : UInt<8>, x : UInt<8>}")
+    chirrtl should include("output out : { y : UInt<8>, x : UInt<8>}")
+    chirrtl should include("out <= in")
+  }
+
+  they should "support conditional OpaqueTypes via traits and factory methods" in {
+    class MyModule extends Module {
+      val in0 = IO(Input(MaybeBoxed(UInt(8.W), true)))
+      val out0 = IO(Output(MaybeBoxed(UInt(8.W), true)))
+      val in1 = IO(Input(MaybeBoxed(UInt(8.W), false)))
+      val out1 = IO(Output(MaybeBoxed(UInt(8.W), false)))
+      out0 := in0
+      out1 := in1
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+    chirrtl should include("input in0 : { underlying : UInt<8>}")
+    chirrtl should include("input in1 : UInt<8>")
+  }
+
   they should "work with .toTarget" in {
     var m: SingleElementRecordModule = null
     ChiselStage.elaborate { m = new SingleElementRecordModule; m }
-- 
cgit v1.2.3


From be4463a7756351dcab09ba3f576f5e3687fb0ebf Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Thu, 10 Nov 2022 20:03:45 +0000
Subject: Unify Chisel2 and chisel3 directionality (backport #2634) (#2837)

* Unify Chisel2 and chisel3 directionality (#2634)

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 1aea4ef96466cbe08150d20c85c88b81e4e4f80f)

# Conflicts:
#	core/src/main/scala/chisel3/Aggregate.scala
#	core/src/main/scala/chisel3/Module.scala
#	src/test/scala/chiselTests/Direction.scala

* fix up backport

* fix up backport

* clean up diff

* make test order like it was on master

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>---
 src/test/scala/chiselTests/Direction.scala | 84 ++++++++++++++++++++++++------
 1 file changed, 68 insertions(+), 16 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 642a507c..ddbd99d2 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -86,15 +86,15 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
     })
   }
 
-  property("Empty Vecs with no direction on the sample_element *should* cause direction errors") {
-    an[Exception] should be thrownBy extractCause[Exception] {
-      ChiselStage.elaborate(new Module {
-        val io = IO(new Bundle {
-          val foo = Input(UInt(8.W))
-          val x = Vec(0, UInt(8.W))
-        })
+  property(
+    "Empty Vecs with no direction on the sample_element should not cause direction errors, as Chisel and chisel3 directions are merged"
+  ) {
+    ChiselStage.elaborate(new Module {
+      val io = IO(new Bundle {
+        val foo = Input(UInt(8.W))
+        val x = Vec(0, UInt(8.W))
       })
-    }
+    })
   }
 
   property("Empty Bundles should not cause direction errors") {
@@ -120,15 +120,15 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
     })
   }
 
-  property("Explicitly directioned but empty Bundles should cause direction errors") {
-    an[Exception] should be thrownBy extractCause[Exception] {
-      ChiselStage.elaborate(new Module {
-        val io = IO(new Bundle {
-          val foo = UInt(8.W)
-          val x = Input(new Bundle {})
-        })
+  property(
+    "Explicitly directioned but empty Bundles should not cause direction errors because Chisel and chisel3 directionality are merged"
+  ) {
+    ChiselStage.elaborate(new Module {
+      val io = IO(new Bundle {
+        val foo = UInt(8.W)
+        val x = Input(new Bundle {})
       })
-    }
+    })
   }
 
   import chisel3.experimental.{DataMirror, Direction}
@@ -330,6 +330,58 @@ class DirectionSpec extends ChiselPropSpec with Matchers with Utils {
       }
     }
   }
+  property("Can now describe a Decoupled bundle using Flipped, not Input/Output in chisel3") {
+    class Decoupled extends Bundle {
+      val bits = UInt(3.W)
+      val valid = Bool()
+      val ready = Flipped(Bool())
+    }
+    class MyModule extends RawModule {
+      val incoming = IO(Flipped(new Decoupled))
+      val outgoing = IO(new Decoupled)
+
+      outgoing <> incoming
+    }
+
+    val emitted: String = ChiselStage.emitChirrtl(new MyModule)
+
+    // Check that emitted directions are correct.
+    assert(emitted.contains("input incoming : { bits : UInt<3>, valid : UInt<1>, flip ready : UInt<1>}"))
+    assert(emitted.contains("output outgoing : { bits : UInt<3>, valid : UInt<1>, flip ready : UInt<1>}"))
+    assert(emitted.contains("outgoing <= incoming"))
+  }
+  property("Can now mix Input/Output and Flipped within the same bundle") {
+    class Decoupled extends Bundle {
+      val bits = UInt(3.W)
+      val valid = Bool()
+      val ready = Flipped(Bool())
+    }
+    class DecoupledAndMonitor extends Bundle {
+      val producer = new Decoupled()
+      val consumer = Flipped(new Decoupled())
+      val monitor = Input(new Decoupled()) // Same as Flipped(stripFlipsIn(..))
+      val driver = Output(new Decoupled()) // Same as stripFlipsIn(..)
+    }
+    class MyModule extends RawModule {
+      val io = IO(Flipped(new DecoupledAndMonitor()))
+      io.consumer <> io.producer
+      io.monitor.bits := io.driver.bits
+      io.monitor.valid := io.driver.valid
+      io.monitor.ready := io.driver.ready
+    }
+
+    val emitted: String = ChiselStage.emitChirrtl(new MyModule)
+
+    assert(
+      emitted.contains(
+        "input io : { producer : { bits : UInt<3>, valid : UInt<1>, flip ready : UInt<1>}, flip consumer : { bits : UInt<3>, valid : UInt<1>, flip ready : UInt<1>}, flip monitor : { bits : UInt<3>, valid : UInt<1>, ready : UInt<1>}, driver : { bits : UInt<3>, valid : UInt<1>, ready : UInt<1>}}"
+      )
+    )
+    assert(emitted.contains("io.consumer <= io.producer"))
+    assert(emitted.contains("io.monitor.bits <= io.driver.bits"))
+    assert(emitted.contains("io.monitor.valid <= io.driver.valid"))
+    assert(emitted.contains("io.monitor.ready <= io.driver.ready"))
+  }
   property("Bugfix: marking Vec fields with mixed directionality as Output/Input clears inner directions") {
     class Decoupled extends Bundle {
       val bits = UInt(3.W)
-- 
cgit v1.2.3


From 17c04998d8cd5eeb4eff9506465fd2d6892793d2 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Thu, 10 Nov 2022 21:11:55 +0000
Subject: Add unit tests and fix for #2794 , add unit tests for #2773 
 (backport #2792) (#2834)

* Fixup and unit tests for D/I of IOs without explicit Input/Output (#2792)

(cherry picked from commit f24a624863f0fc460fd862238688ea8612ffdf5e)

# Conflicts:
#	core/src/main/scala/chisel3/Module.scala

* Resolve backport conflicts

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 .../CompatibilityInteroperabilitySpec.scala        | 284 +++++++++++++++++++++
 1 file changed, 284 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index e2fb2179..eb5aaaba 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -392,6 +392,290 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
     compile(new Top(false))
   }
 
+  "A Chisel.Bundle with only unspecified directions" should "work with D/I" in {
+
+    object Compat {
+      import Chisel._
+      import chisel3.experimental.hierarchy.{instantiable, public}
+
+      class CompatBiDirUnspecifiedBundle extends Bundle {
+        val out = Bool()
+        val in = Flipped(Bool())
+      }
+
+      @instantiable
+      class CompatModule extends Module {
+        @public val io = IO(new CompatBiDirUnspecifiedBundle)
+      }
+    }
+
+    object Chisel3 {
+      import chisel3._
+      import chisel3.experimental.hierarchy.Instance
+      class Example extends Module {
+        val mod = Module(new Compat.CompatModule())
+        mod.io.in <> DontCare
+        val inst = Instance(mod.toDefinition)
+        inst.io.in <> mod.io.out
+        mod.io.in <> inst.io.out
+      }
+    }
+    compile(new Chisel3.Example)
+  }
+
+  "A Chisel.Bundle with mixed Specified and Unspecified directions" should "work with D/I" in {
+
+    object Compat {
+      import Chisel._
+      import chisel3.experimental.hierarchy.{instantiable, public}
+
+      class CompatBiDirMixedBundle extends Bundle {
+        val out = Bool()
+        val in = Flipped(Bool())
+        val explicit = Output(Bool())
+      }
+
+      @instantiable
+      class CompatModule extends Module {
+        @public val io = IO(new CompatBiDirMixedBundle)
+      }
+    }
+
+    object Chisel3 {
+      import chisel3._
+      import chisel3.experimental.hierarchy.Instance
+      class Example extends Module {
+        val mod = Module(new Compat.CompatModule)
+        mod.io.in <> DontCare
+        val inst = Instance(mod.toDefinition)
+        inst.io.in <> mod.io.out
+        mod.io.in <> inst.io.out
+      }
+    }
+    compile(new Chisel3.Example)
+  }
+
+  "A Chisel.Bundle with only unspecified vec direction" should "work with D/I" in {
+
+    object Compat {
+      import Chisel._
+      import chisel3.experimental.hierarchy.{instantiable, public}
+
+      class CompatBiDirUnspecifiedVecBundle extends Bundle {
+        val out = Vec(3, Bool())
+        val in = Flipped(Vec(3, Bool()))
+      }
+
+      @instantiable
+      class CompatModule extends Module {
+        @public val io = IO(new CompatBiDirUnspecifiedVecBundle)
+      }
+    }
+
+    object Chisel3 {
+      import chisel3._
+      import chisel3.experimental.hierarchy.Instance
+      class Example extends Module {
+        val mod = Module(new Compat.CompatModule())
+        mod.io.in <> DontCare
+        val inst = Instance(mod.toDefinition)
+        inst.io.in <> mod.io.out
+        mod.io.in <> inst.io.out
+      }
+    }
+    compile(new Chisel3.Example)
+  }
+
+  "A chisel3.Bundle with only unspecified directions" should "work with D/I" in {
+
+    // This test is NOT expected to work on 3.5.x, it should throw an error in the IO construction.
+
+    object Chisel3 {
+      import chisel3._
+      import chisel3.experimental.hierarchy.{instantiable, public, Instance}
+
+      class BiDirUnspecifiedBundle extends Bundle {
+        val out = Bool()
+        val in = Flipped(Bool())
+      }
+
+      @instantiable
+      class MyModule extends Module {
+        @public val io = IO(new BiDirUnspecifiedBundle)
+        io <> DontCare
+      }
+
+      class Example extends Module {
+        val mod = Module(new MyModule())
+        mod.io.in <> DontCare
+        val inst = Instance(mod.toDefinition)
+        inst.io.in <> mod.io.out
+        mod.io.in <> inst.io.out
+      }
+    }
+    compile(new Chisel3.Example)
+  }
+
+  "A chisel3.Bundle with mixed Specified and Unspecified directions" should "work with D/I" in {
+
+    // This test is NOT expected to work on 3.5.x, it should throw an error in the IO construction.
+
+    object Chisel3 {
+      import chisel3._
+      import chisel3.experimental.hierarchy.{instantiable, public, Instance}
+
+      class BiDirMixedBundle extends Bundle {
+        val out = Bool()
+        val in = Flipped(Bool())
+        val explicit = Output(Bool())
+      }
+
+      @instantiable
+      class MyModule extends Module {
+        @public val io = IO(new BiDirMixedBundle)
+        io <> DontCare
+      }
+      class Example extends Module {
+        val mod = Module(new MyModule)
+        mod.io.in <> DontCare
+        val inst = Instance(mod.toDefinition)
+        inst.io.in <> mod.io.out
+        mod.io.in <> inst.io.out
+      }
+    }
+    compile(new Chisel3.Example)
+  }
+
+  "A chisel3.Bundle with only unspecified vec direction" should "work with D/I" in {
+
+    // This test is NOT expected to work on 3.5.x, it should throw an error in the IO construction
+
+    object Chisel3 {
+      import chisel3._
+      import chisel3.experimental.hierarchy.{instantiable, public, Instance}
+
+      class BiDirUnspecifiedVecBundle extends Bundle {
+        val out = Vec(3, Bool())
+        val in = Flipped(Vec(3, Bool()))
+      }
+
+      @instantiable
+      class MyModule extends Module {
+        @public val io = IO(new BiDirUnspecifiedVecBundle)
+        io <> DontCare
+      }
+
+      class Example extends Module {
+        val mod = Module(new MyModule())
+        mod.io.in <> DontCare
+        val inst = Instance(mod.toDefinition)
+        inst.io.in <> mod.io.out
+        mod.io.in <> inst.io.out
+      }
+    }
+    compile(new Chisel3.Example)
+  }
+
+  "A chisel3.Bundle with only unspecified vec direction within an unspecified direction parent Bundle" should "work with D/I" in {
+
+    // This test is NOT expected to work in 3.5.x, it should throw an error in the IO construction.
+
+    object Chisel3 {
+      import chisel3._
+      import chisel3.experimental.hierarchy.{instantiable, public, Instance}
+
+      class UnspecifiedVecBundle extends Bundle {
+        val vec = Vec(3, Bool())
+      }
+
+      class UnspecifiedParentBundle extends Bundle {
+        val out = new UnspecifiedVecBundle
+      }
+
+      @instantiable
+      class MyModule extends Module {
+        @public val io = IO(new UnspecifiedParentBundle)
+        io <> DontCare
+      }
+
+      class Example extends Module {
+        val mod = Module(new MyModule())
+
+        val wire = Wire(new UnspecifiedParentBundle)
+        wire.out.vec <> mod.io.out.vec
+        val inst = Instance(mod.toDefinition)
+        wire.out.vec <> inst.io.out.vec
+
+      }
+    }
+    compile(new Chisel3.Example)
+  }
+
+  "A undirectioned Chisel.Bundle used in a MixedVec " should "bulk connect in import chisel3._ code correctly" in {
+
+    // This test is NOT expected to work on 3.5.x, it should throw an error in the IO construction.
+
+    object Compat {
+
+      import Chisel._
+      import chisel3.util.MixedVec
+
+      class ChiselModule extends Module {
+        val io = IO(new Bundle {
+          val out = MixedVec(Seq.fill(3) { Bool() })
+          val in = Flipped(MixedVec(Seq.fill(3) { Bool() }))
+        })
+        io.out := RegNext(io.in)
+      }
+
+    }
+    object Chisel3 {
+      import chisel3._
+
+      class Chisel3Module extends Compat.ChiselModule
+
+      class Example extends Module {
+        val oldMod = Module(new Compat.ChiselModule)
+        val newMod = Module(new Chisel3Module)
+
+        oldMod.io.in <> DontCare
+        newMod.io.in <> DontCare
+
+      }
+    }
+    compile(new Chisel3.Example)
+  }
+
+  "A undirectioned Chisel.Bundle with Records with undirectioned and directioned fields " should "work" in {
+
+    // This test should fail on 3.5.x
+
+    object Compat {
+
+      import Chisel._
+
+      class ChiselModule(gen: () => Data) extends Module {
+        val io = IO(new Bundle {
+          val mixed = new Chisel3.MyRecord(gen)
+        })
+      }
+
+    }
+    object Chisel3 {
+      import chisel3._
+      import scala.collection.immutable.SeqMap
+
+      class MyRecord(gen: () => Data) extends Record with chisel3.experimental.AutoCloneType {
+        val elements = SeqMap("genDirectioned" -> Output(gen()), "genUndirectioned" -> gen())
+      }
+
+      class Example extends Module {
+        val newMod = Module(new Compat.ChiselModule(() => Bool()))
+      }
+    }
+    compile(new Chisel3.Example)
+  }
+
   "A BlackBox with Chisel._ fields in its IO" should "bulk connect in import chisel3._ code correctly" in {
     object Compat {
       import Chisel._
-- 
cgit v1.2.3


From c51fcfea32b6c73e623657442460fb782ff0733b Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Thu, 10 Nov 2022 13:41:00 -0800
Subject:  Warn on S-interpolator usage for assert, assume and printf (backport
 #2751) (#2757)

* Add internal methods to maintain binary compatibility

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/IntervalSpec.scala   | 7 ++-----
 src/test/scala/chiselTests/Vec.scala            | 4 ++--
 src/test/scala/chiselTests/VecLiteralSpec.scala | 4 ++--
 3 files changed, 6 insertions(+), 9 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/IntervalSpec.scala b/src/test/scala/chiselTests/IntervalSpec.scala
index c0338f6d..a2d36579 100644
--- a/src/test/scala/chiselTests/IntervalSpec.scala
+++ b/src/test/scala/chiselTests/IntervalSpec.scala
@@ -211,7 +211,7 @@ class ClipSqueezeWrapDemo(
   val wrapped = counter.wrap(0.U.asInterval(targetRange))
 
   when(counter === startValue) {
-    printf(s"Target range is $range\n")
+    printf(cf"Target range is $range\n")
     printf("value     clip      squeeze      wrap\n")
   }
 
@@ -245,10 +245,7 @@ class SqueezeFunctionalityTester(range: IntervalRange, startNum: BigDecimal, end
   squeezeTemplate := toSqueeze.squeeze(squeezeInterval)
 
   printf(
-    s"SqueezeTest %d    %d.squeeze($range) => %d\n",
-    counter,
-    toSqueeze.asSInt(),
-    squeezeTemplate.asSInt()
+    cf"SqueezeTest $counter%d ${toSqueeze.asSInt()}%d.squeeze($range) => ${squeezeTemplate.asSInt()}%d\n"
   )
 }
 
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 4a871890..e46774dd 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -111,7 +111,7 @@ class FillTester(n: Int, value: Int) extends BasicTester {
   val x = VecInit(Array.fill(n)(value.U))
   val u = VecInit.fill(n)(value.U)
 
-  assert(x.asUInt() === u.asUInt(), s"Expected Vec to be filled like $x, instead VecInit.fill created $u")
+  assert(x.asUInt() === u.asUInt(), cf"Expected Vec to be filled like $x, instead VecInit.fill created $u")
   stop()
 }
 
@@ -235,7 +235,7 @@ class IterateTester(start: Int, len: Int)(f: UInt => UInt) extends BasicTester {
   val testVec = VecInit.iterate(start.U, len)(f)
   assert(
     controlVec.asUInt() === testVec.asUInt(),
-    s"Expected Vec to be filled like $controlVec, instead creaeted $testVec\n"
+    cf"Expected Vec to be filled like $controlVec, instead created $testVec\n"
   )
   stop()
 }
diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
index fa97a8c8..e2eb791d 100644
--- a/src/test/scala/chiselTests/VecLiteralSpec.scala
+++ b/src/test/scala/chiselTests/VecLiteralSpec.scala
@@ -205,7 +205,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
 
     assertTesterPasses {
       new BasicTester {
-        chisel3.assert(outsideVecLit(0) === 0xdd.U, s"v(0)")
+        chisel3.assert(outsideVecLit(0) === 0xdd.U, "v(0)")
         stop()
       }
     }
@@ -216,7 +216,7 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
 
     assertTesterPasses {
       new BasicTester {
-        chisel3.assert(outsideVecLit(0) === 0xdd.U, s"v(0)")
+        chisel3.assert(outsideVecLit(0) === 0xdd.U, "v(0)")
         chisel3.assert(outsideVecLit(1) === 0xcc.U)
         chisel3.assert(outsideVecLit(2) === 0xbb.U)
         chisel3.assert(outsideVecLit(3) === 0xaa.U)
-- 
cgit v1.2.3


From c70e5bebaeaf5b0bd54ee84dc644ddd6973a1b86 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Thu, 10 Nov 2022 23:55:25 +0000
Subject: Update CompatibilityInteroperabilitySpec.scala (#2840) (#2842)

(cherry picked from commit aa596b98d5e030294041f2e90eee1f78ca1e401b)

Co-authored-by: Megan Wachs <megan@sifive.com>---
 .../chiselTests/CompatibilityInteroperabilitySpec.scala      | 12 ------------
 1 file changed, 12 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index eb5aaaba..d388c093 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -488,8 +488,6 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
 
   "A chisel3.Bundle with only unspecified directions" should "work with D/I" in {
 
-    // This test is NOT expected to work on 3.5.x, it should throw an error in the IO construction.
-
     object Chisel3 {
       import chisel3._
       import chisel3.experimental.hierarchy.{instantiable, public, Instance}
@@ -518,8 +516,6 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
 
   "A chisel3.Bundle with mixed Specified and Unspecified directions" should "work with D/I" in {
 
-    // This test is NOT expected to work on 3.5.x, it should throw an error in the IO construction.
-
     object Chisel3 {
       import chisel3._
       import chisel3.experimental.hierarchy.{instantiable, public, Instance}
@@ -548,8 +544,6 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
 
   "A chisel3.Bundle with only unspecified vec direction" should "work with D/I" in {
 
-    // This test is NOT expected to work on 3.5.x, it should throw an error in the IO construction
-
     object Chisel3 {
       import chisel3._
       import chisel3.experimental.hierarchy.{instantiable, public, Instance}
@@ -578,8 +572,6 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
 
   "A chisel3.Bundle with only unspecified vec direction within an unspecified direction parent Bundle" should "work with D/I" in {
 
-    // This test is NOT expected to work in 3.5.x, it should throw an error in the IO construction.
-
     object Chisel3 {
       import chisel3._
       import chisel3.experimental.hierarchy.{instantiable, public, Instance}
@@ -613,8 +605,6 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
 
   "A undirectioned Chisel.Bundle used in a MixedVec " should "bulk connect in import chisel3._ code correctly" in {
 
-    // This test is NOT expected to work on 3.5.x, it should throw an error in the IO construction.
-
     object Compat {
 
       import Chisel._
@@ -648,8 +638,6 @@ class CompatibilityInteroperabilitySpec extends ChiselFlatSpec {
 
   "A undirectioned Chisel.Bundle with Records with undirectioned and directioned fields " should "work" in {
 
-    // This test should fail on 3.5.x
-
     object Compat {
 
       import Chisel._
-- 
cgit v1.2.3